JPH0522411B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a pulse signal generator that generates a pulse signal in response to a binary output of a binary counter.

Conventional Structure and Problems Conventionally, this type of pulse signal generator has been structured as shown in FIG. Flip-flops 1 to 8 each have a set function, and a binary down counter 21 is constructed by cascading unit stages. Program terminals 9 to 16 are connected to the data terminal D of each unit stage, to which the program value of each bit is applied. 17
is a clock signal input terminal connected to the clock terminal CL of flip-flop 1 of the least significant bit LSB, 18 is a common set signal input terminal connected to the set terminal S of each flip-flop 1 to 8, and 19 and 20 are the counter terminals. A detection gate that detects when the binary output has become a predetermined combination, and here it consists of a NAND gate.
The output terminal of each unit stage is connected to the gate input terminal according to the binary output to be detected. 22 is an RS flip-flop in which the output terminals of the detection gates 19 and 20 are connected to the set terminal S ₁ and the reset terminal R ₁ ;
The second output terminal is connected to the pulse signal output terminal 23.

Next, the operation will be explained. Now, suppose that the output level of the RS flip-flop 22 is set to a low level and, for example, the program value of the binary down counter 21 is a binary number [00011000] from the MSB side to the LSB side, then the down count is performed from this value. Detection gates 19, 20
When the input of is set as shown in FIG. 1, the detection gate 19 generates an output signal when the counter output reaches NPI [00001100]. This signal causes RS
The flip-flop 22 is set, and the level of the pulse signal output terminal 23 changes from low level to high level. As the count continues, the detection gate 20 generates an output signal when the counter output reaches NP2 [11010100], and this signal causes
The RS flip-flop 22 is reset, and the level of the pulse signal output terminal 23 changes from high level to low level, indicating that a predetermined pulse signal has been generated.

However, in the configuration shown in Figure 1,
Since all outputs of each unit stage are used to detect the time when the level of the output pulse signal changes from low level to high level or from high level to low level, the input terminals of detection gates 19 and 20 are Only the number of unit stages is required. Similarly, the output terminal of each unit stage and the detection gate 1
The same number of wires are required to connect the input terminals 9 and 20. In particular, when there are multiple pulse signals to be generated, the number of wires is expressed as follows: Number of wires=(number of unit stages)×(number of pulse signals to be generated)×2. Therefore, when a plurality of pulse signals are generated, the number of wires increases and each unit stage requires a large drive capacity, which poses a problem in integrated circuits.

OBJECT OF THE INVENTION The present invention solves the above-mentioned conventional drawbacks, and aims to provide a pulse signal generation device that can generate pulse signals with a smaller number of wires and elements based on the count value of a counter. purpose.

Structure of the Invention In order to achieve the above object, the pulse signal generating device of the present invention includes a binary down counter formed by using a flip-flop having a set function as a unit stage and connecting N unit stages (N≧4) in cascade; It can be distinguished by the binary outputs of the upper L (L≧1) unit stages of the binary down counter, and the binary outputs of the middle K (K≧2) unit stages are not all “0” and the lower J (J≧1), for the first and second predetermined count values NP1 and NP2 whose binary output is “0”, the upper L “1” of the first predetermined count value NP1 The non-inverting output terminals of all unit stages which become "0" and the inverting output terminals of all unit stages which become "0", all the inverting output terminals of the lower J unit stages, and the K intermediate stage , a first detection gate in which only the inverting output terminal of the unit stage which becomes "0" at the value of the predetermined count value NP1 is connected to the input terminal, and an upper L of the second predetermined count value NP2. The non-inverting output terminals of all the unit stages that become "1" and the inverting output terminals of all the unit stages that become "0", and all the inverting output terminals of the lower J unit stages, and the intermediate For the K stages, a second detection gate in which only the inverted output terminal of the unit stage which becomes "0" at the value of the predetermined count value NP2 is connected to the input terminal, and an output of the first detection gate. The RS flip-flop has an end connected to the set input end and an output end of the second detection gate connected to the reset input end.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a circuit diagram of the pulse signal generator of the present invention, and the same components as those shown in FIG. 1 are given the same reference numerals and their explanations will be omitted. The following points differ between FIG. 2 and FIG. 1. In FIG. 2, the binary value to be detected is input to the input terminal of the detection gate 19 from the MSB side to the LSB side.
In the case of NP1 [00001100] towards the side, J = 2, K
= 4, L = 2, the inverting output terminals of the upper two unit stages, the inverting output terminals of the lower two unit stages, and the flip-flop whose logic level is "0" among the four intermediate unit stages. 5,6
A total of 6 wires are connected to the inverted output terminal of
Flip-flops 3 and 4 and detection gate 19 are not connected. In Figure 2, J=2, K=4, L
= 2, but in order to increase the number of intermediate stages K, J,
By appropriately setting K and L, the number of wiring lines can be reduced. For example, J=2, K=5, L
= 1, in the binary value NP1, the inverting output terminal of the upper one unit stage, the inverting output terminal of the lower two unit stages, and the flip-flop whose logic level is "0" among the five intermediate unit stages. A total of six inverting output terminals 5, 6, and 7 are connected to the input terminal of the detection gate 19, and the flip-flops 3 and 4 are not connected to the detection gate 19. In other words, two wires connecting the flip-flops 3 and 4 and the detection gate 19 are eliminated. Similarly, the binary value NP2 becomes
The non-inverting output terminal of the upper unit stage, the inverting output terminal of the lower two unit stages, and the inverting output terminals of flip-flops 4 and 6 that have a logic level of "0" among the five intermediate unit stages. A total of five wires are connected to the input terminal of the detection gate 20,
Flip-flops 3, 5, 7 and detection gate 20 are not connected. That is, three wires connecting the flip-flops 3, 5, and 7 and the detection gate 20 are reduced. Therefore, in this case, the connections in FIG. 2, J=2, K=4, L
Compared to the case where =2, the number of wires in the detection gate 20 can be further reduced by one. Here, when the logic levels of the intermediate unit stages of the binary value to be detected are all "0", all non-inverting output terminals of flip-flops 3, 4, 5, 6, and 7 are connected to the detection gate. , the number of wires cannot be reduced. Therefore, all intermediate logic levels of the binary value to be detected must not be "0". The same goes for the detection gate 20, and the binary value to be detected is NP2.
In the case of [11010100], the non-inverting output terminals of the upper two unit stages, the inverting output terminals of the lower two unit stages, and the flip-flop 4 whose logic level is "0" among the four intermediate unit stages, 6
A total of 6 wires are connected to the inverted output terminal of
Flip-flops 3 and 5 and detection gate 20 are not connected. That is, two wiring lines between the flip-flops 4 and 6 and the detection gate 20 are eliminated.

FIG. 3 is a time chart showing the operation of the circuit shown in FIG. 2, and 17a is a clock signal input terminal 17.
1Q to 8Q are signals output from the non-inverting output terminals Q of flip-flops 1 to 8 of each unit stage, and 18a is a signal supplied to each flip-flop 1 to 8 of the binary down counter 21.
The set signal 19a is supplied to the set signal input terminal S of the detection gate 19, and 20a is the output signal of the detection gate 19.
is the output signal of the detection gate 20, and 22a is the output signal of the RS flip-flop 22.

Before time _t0 , the logic level of the set signal input terminal 18 is high level, and the preset data is sent to each unit stage from the MSB side to the LSB side.
Assuming that [00011000] is set,
Output signals 19a, 20a of detection gates 19, 20
has a high logic level. Also,
The logic level of the pulse signal output terminal 23 is set to low level. When the set signal 18a at the set signal input terminal 18 is inverted from a high level to a low level, the binary down counter 21 counts down the clock signal 17a. At time t ₁ , the binary output of the binary down counter 21 reaches the predetermined count value NP1.
When it becomes [00001100], the output level of the detection gate 19 becomes low level and outputs the detection signal 19a. The RS flip-flop 22 is set by this signal 19a, and the level of the pulse signal output terminal 23 changes from low level to high level.
When the binary output of the binary down counter 21 becomes [00001011] at time _t2 , the detection gate 1
The output level of No. 9 returns to high level, indicating that the detection has ended. The output of the detection gate 19 is
Since there is a unit stage that does not detect the output, the time
Similarly, it becomes a low level at times t ₃ , t ₅ , and t ₇ , and becomes a high level at times t ₄ , t ₆ , and t ₈ . Therefore,
The detection gate 19 outputs the detection signal 19a four times, and also outputs the detection signal 19a for binary output values other than the binary output to be detected. However, binary down counter 2
After the data is preset to 1, the detection gate 1
9 outputs the detection signal 19a for the first time at time t ₁
and the binary down counter 2 at that time
The binary output of 1 is the binary value [00001100] to be detected. First detection signal 19
Since the RS flip-flop 22 is set at a,
The output of the RS flip-flop 22 changes from low level to high level at time _t1 , and when the detection signal 19a is output at times _t3 , _t5 , and _t7 , the pulse signal output terminal 23 is already at high level. . Similarly, at time _t13 , the binary output of the binary down counter 21 reaches the predetermined count value.
When NP2 [11010100] is reached, the output level of the detection gate 20 becomes low level and outputs the detection signal 20a. The RS flip-flop 22 is reset by this signal 20a, and the level of the pulse signal output terminal 23 changes from high level to low level. The detection signal 20 is also present at times t ₁₅ , t ₂₁ , and t ₂₃ .
a is output, but it is already connected to the pulse signal output terminal 2.
3 is at low level, and the pulse signal 22a
has no effect on. Therefore, the pulse width of the output pulse signal 22a is determined by the period of the clock signal 17a input to the binary down counter 21 and the predetermined count values NP1 and NP2.

Furthermore, the number L of upper bits detected by the binary down counter 21 is determined by the output pulse signal 22a.
A signal sequence of the detection signal 19a detected by the detection signal 19 while the detection signal 19 is at a high level (detection signals at times t ₃ , t ₅ , t ₇ )
The detection signal 20 is detected while the output of the output pulse signal 22a is at low level.
It is selected so that the output of the signal sequence a (detection signals at times t ₁₅ , t ₂₁ , and t ₂₃ ) ends. That is, the count values NP1 and NP2 must be distinguished by the upper L bits. Therefore, in the embodiment of FIG. 2, L=
2, but the value of L may be any value from 1 to 4. However, if the value of L is increased, the value of K becomes smaller, and the number of wiring lines that can be reduced decreases, so an appropriate value of L must be selected.

The reason why the inverted outputs of the lower J unit stages of the binary down counter 21 are detected is to prevent a hazard that may occur when detecting the count value. A hazard occurs when the operating speed of the binary down counter 21 is slow relative to the input clock signal. For example, if a clock signal is input when the count value is [11010000], the original count value is [11001111].
However, due to the slow operation speed of the binary down counter 21, when the binary down counter 21 momentarily outputs the value [11010111], the output of the lower bit of the binary down counter 21 is sent to the detection gate 20. If it is not input, the detection gate 20 will make a false detection. Therefore, in order to prevent the detection gate 20 from erroneously detecting, the number J of bits corresponding to the time required for the operation of all bits of the binary down counter 21 to be determined is inputted to the detection gate 20.

In addition, in the example of FIG. 2, NP1 [00001100],
Although explained as NP2 [00010100], for example, if both of the upper L (L=2) values of the first predetermined count value NP1 and the second predetermined count value NP2 are (), for example, NP1
For [00001100], NP2 [00010100],
Since the number of upper bits required to distinguish between NP1 and NP2 is 4 bits, L=4. Also, J
= 2, then K = 2, and the number of wires that can be reduced is
There will be two NP1s and one NP2.

Next, other embodiments of the present invention will be described.
FIG. 4 is a circuit diagram of a pulse signal generator according to another embodiment, and the same components as those shown in FIGS. 1 and 2 are given the same reference numerals and their explanations will be omitted. In this embodiment, a plurality of necessary pulse signals are generated. The following points differ between FIG. 4 and FIG. 2. In FIG. 4, the detection gate 24
and RS flip-flop 25 are added, and if the binary value to be detected is NP3 [11011100] at the input terminal of the detection gate 24, J=2, K=
4, L=2, the non-inverting output terminals of the upper two unit stages, the inverting output terminals of the lower two unit stages, and the flip-flop which has a logic level of "0" among the four intermediate unit stages. The flip-flops 3, 4, 5 and the detection gate 24 are not connected. That is, three wiring lines between the flip-flops 3, 4, and 5 and the detection gate 24 are reduced. The output terminal of the detection gate 24 is RS
The Q output terminal of the RS flip-flop 22 is connected to the set terminal S ₂ of the flip-flop 25 and the reset terminal R ₂ of the RS flip-flop 25 .

FIG. 5 is a time chart showing the operation of the circuit shown in FIG. 4. Note that the same signals as those shown in FIG. 3 are given the same reference numerals, and their explanations will be omitted. 24a is the output signal of the detection gate 24, 25a
is the inverted output signal of the RS flip-flop 25.

A binary down counter 21 counts down the clock signal. When the binary output of the binary down counter 21 reaches the predetermined count value NP3 [11011100] at time _t9 , the detection gate 24
The output becomes low level and outputs the detection signal 24a. The RS flip-flop 25 is set by this signal 24a, and the pulse signal output terminal 26 is set.
The output level changes from high level to low level. Furthermore, the detection gate 24 is activated at times t ₁₁ , t ₁₃ , t ₁₅ ,
Also at t ₁₇ , t ₁₉ , t ₂₁ , and t ₂₃ , the detection signal 24a is output and the flip-flop 25 is attempted to be set. However, the Q output terminal of the flip-flop 22 is connected to the reset terminal _R2 of the flip-flop 25, and the flip-flop 25 is reset at time _t13 when the Q output becomes low level.
The pulse signal output terminal 26 becomes high level. Since the pulse signal output terminal 26 is connected to the inverted output terminal Q of the flip-flop 25, the set signal from the detection gate 24 after time _t13 is inhibited by the Q signal of the flip-flop 22, and has no effect on the pulse signal output terminal 26. I won't give it. Figure 5 2
5Q, the influence of the set signal 24a, which is the detection signal of the detection gate 24, appears on the non-inverting output terminal Q of the flip-flop 25.

In this way, by using the first pulse signal 22a to generate the second pulse signal 25a, the number of wires connecting the binary down counter 21 and the detection gate 24 can be reduced. The pulse width of the second pulse signal 25a is the count value NP3 first detected by the detection gate 24, and
It is determined by the count value NP2 at which the Q output of the flip-flop 22 becomes low level and the period of the clock signal 17a input to the binary down counter 21.

Effects of the Invention As explained above, according to the present invention, it is possible to generate a pulse signal according to the count value of a counter with a small number of wires and elements, and therefore, for example, the degree of integration can be significantly increased in an integrated circuit. It has extremely great industrial utility value, such as being able to improve

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional pulse signal generator.
2 is a circuit diagram of a pulse signal generator in one embodiment of the present invention, FIG. 3 is a time chart of the circuit shown in FIG. 2, and FIG. 4 is a circuit diagram of a pulse signal generator in another embodiment, FIG. 5 is a time chart of the circuit shown in FIG. 1 to 8...Flip-flop, 9 to 16...Program terminal, 17...Clock signal input terminal,
18...Set signal input terminal, 19, 20, 24
...Detection gate, 21...Binary down counter, 22, 25...RS flip-flop, 2
3, 26...Pulse signal output terminal.

Claims (1)

[Claims] 1 A flip-flop having a set function is used as a unit stage, and N units of this unit stage (N≧
4) Binary down counters connected in cascade can be distinguished by the binary outputs of the upper L (L≧1) unit stages of this binary down counter, and the binary outputs of the upper K (K≧2) unit stages of the intermediate stage. For the first and second predetermined count values NP1 and NP2 in which the binary outputs are not all "0" and the binary outputs of the lower J unit stages (J≧1) are "0", the first For the predetermined count value NP1, the non-inverting output terminals of all the upper L unit stages that become "1" and the inverting output terminals of all the unit stages that become "0", and for the lower J unit stages, All the inverting output terminals, and for the K intermediate stages, only the inverting output terminals of the unit stages which are "0" at the value of the predetermined count value NP1 are connected to the first detection gates, respectively, to the input terminals. , the non-inverting output terminals of all the upper L unit stages that become "1" and the inverting output terminals of all the unit stages that become "0" of the second predetermined count value NP2 are also the lower J units. For the stages, all the inverting output terminals are connected to the second input terminal, and for the K intermediate stages, only the inverting output terminals of the unit stages that are "0" at the value of the predetermined count value NP2 are connected to the second input terminal. A pulse signal generating device comprising: a detection gate; and an RS flip-flop in which the output terminal of the first detection gate is connected to a set input terminal and the output terminal of the second detection gate is connected to a reset input terminal.