JPS59128831A - Pulse signal generator - Google Patents

Abstract

PURPOSE:To improve the degree of circuit integration of an integrated circuit by generating a pulse signal with less number of wires and elements based on the count value of a counter. CONSTITUTION:When a set signal 18a of a set input terminal 18 is inverted from a logical high to a logical low level, a binary counter 21 counts down a clock signal 17a. When a binary output reaches a prescribed count value NP1 [00001100] at a time t1, an output level of a detecting gate 19 goes to a low potential and a detecting signal 19a is outputted. This signal 19a sets an RSFF22 and the level of a pulse signal output terminal 23 changes from a low to a high level. When a binary output of the counter 21 reaches [00001011] at a time t2, the output of the detection gate 19 is returned to high level and the detection is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pulse signal generator that generates a pulse signal in response to a binary output of a binary counter. This type of pulse signal generator is constructed as shown in FIG. (1) to (8) are flip-flops each having a set function, and each unit stage is connected in cascade to form a binary counter (in this case, a binary counter).
A down counter) is configured. (9) ~αQ
is connected to the data terminal (D) of each unit stage and is a program terminal to which the program value of each bit is applied. Oη is the clock signal input terminal connected to the clock terminal (CL) of the least significant bit (LSB) flip-flop (1), and (g) is the respective flip-flop (
A common set signal input terminal connected to the set terminals (S) of 1) to (8), α94 is a detection gate that detects that the binary output of the counter has become a predetermined combination, and here it is a NAND gate. The output terminal of each unit stage is connected to the gate input terminal. ) is an RS flip-flop in which the output terminal of the detection gate Ql (7) is connected to the set terminal (Sl) and the reset terminal (R1),
The output terminal of this RS flip-flop 4 is connected to the pulse signal output terminal (c).

Next, the operation will be explained. Now, temporarily, the output level of this RS flip-flop 4 is set to low level, and for example, the program value of the pinary counter υ is a binary number, and the LS flip-flop is input from the MSB side.
Assuming that it is (00011000) towards the B side, a down count is performed from this value. If the human power of the detection gate t-asa is set as shown in Figure 1, the counter output will be NPI ( 00001100), detection gate 4 generates an output signal. This signal causes the RS flip-flop (2) to change from the low level to the high level. One more time, the counter output is NF2 t
Detection gate (7) when it becomes llololoo)
generates an output signal, this signal resets the RS flip-flop (), and the level of the pulse signal output terminal (c) changes from high level to low level by 1, indicating that a predetermined pulse signal has been generated. .

However, in the configuration shown in FIG. 1, it takes time at each unit stage to detect time 1 when the level of the output pulse signal changes from low level to low level and from high level to low level. Since all the outputs are used, the number of input terminals of the detection gate α field (4) is equal to the number t of the unit stages. Similarly, the same number of wires are required to connect the output terminal of each unit stage and the input terminal of the detection gate (4).

In particular, when there are a plurality of pulse signals to be generated, the number of wires is expressed as: Number of wires=(ridge of unit stage)×(number of pulse signals to be generated)×2. Therefore, when a plurality of C pulse signals are generated, the number of wirings increases and each unit stage requires a large drive capacity, which poses a problem in integrated circuits.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional drawbacks, and aims to provide a pulse signal generating device that can generate pulse signals with a smaller number of wires and elements based on the count value of a counter. purpose.

In order to achieve the configuration and purpose of the invention, the pulse signal generator of the present invention has a binary counter in which a flip-flop having a set function is used as a unit stage, and N units (N22) of these unit stages are connected in cascade. , in the binary output state of the first predetermined count value NPI of this binary counter, for the higher (L≧2) unit stages, the non-inverting output terminal of the unit stage becomes the binary output 111 and 10J. The inverting output terminal of the unit stage is approximately F for J (J≧1) unit stages.
-J-L), the inverted output terminal of the unit stage whose predetermined binary output NPI is r□J or rIJ is connected to the input terminal, and the non-inverted output terminal is connected to the input terminal of , and in the binary output state of the tyr constant count value NP2 of the binary counter, for the unit stage of 1st order even, the predetermined binary output is 11.
1 and the non-inverting output end of the unit stage and 10. The inverting output terminal of the unit stage J, and the inverting output terminal or non-inverting output terminal of the lower one unit stage 1, and the predetermined binary output N of the intermediate stage.
P2 is 10. The inverting output terminal or non-inverting output terminal of the unit stage J or rIJ is connected to the input terminal, respectively, and the output terminal of the second detection gate is connected to the set input terminal, and the output terminal of the first detection gate is connected to the set input terminal. The configuration includes an RS flip-flop whose output terminal of the second detection gate is connected to a reset input terminal.

DESCRIPTION OF EMBODIMENTS The following describes one embodiment of the present invention.
- Explain based on. FIG. 2 is a circuit diagram of the pulse signal generator, and the same constituent elements as those shown in the first factor are given the same reference numerals and their explanations will be omitted.

The following points differ between FIG. 2 and FIG. 1. In the second prisoner, for example, the binary signal to be detected is connected to the input terminal of the detection gate Ql.
The value is NPI (00001) from the MSB side to the LSB side.
100:), if J=2, K=4, L=2,
The inverting output terminals of the first two unit stages, the inverting output terminals of the lower two unit stages, and the flip-flop (of which the logic level is 10J) among the four intermediate unit stages
5) A total of 6 wires are connected to the inverting output terminal of (6), and the flip-flops (3) and (4) are not connected to the detection gate 4.

The same goes for the detection gate (7), and when the binary value to be detected is NF2 (11010100), the non-inverting output terminals of the first two unit stages and the inverting output terminals of the lower two unit stages are connected. , a flip-flop (4) with a logic level of 76J among the four intermediate stage unit stages.
A total of 6 wires are connected to the inverted output terminal (6).
Flip-flops (3) (5) and detection gate (1) are not connected.

FIG. 3 is a time chart showing the operation of the circuit shown in FIG. 2, where (17a) is the clock signal supplied to the clock signal input terminal (b), and (IQ) to (8Q) are the flip-flops of each unit stage. The signal output from the non-inverting output terminal (0) of (1) to (8), (18a) is supplied to the set signal input terminal (S) of each flip-flop (1 to (8)) of binary counter 4. set signal, ' (19
(a) is the output signal of the detection gate Ql, (20a) is the output signal of the detection gate (2), and (22a) is the output signal of the RS flip-flop.

Time t. Previously, the logic level of the set signal input terminal (G) was high level, and the preset data was sent to each dedication stage from the MSB side to the I and SB sides (000110
00) is set and the temperature is 0.degree. C., the output values of the detection gates a group (4) (19a) and (20a) have a logic level of high level. Further, the logic level of the pulse signal output terminal [shares] is set to low level. And the set signal (18a) of the set signal input terminal (c)
When the aN level is reversed from high level to low level,
The binary counter 9υ counts down the clock signal @(17a). At time t, the binary output of the binary counter 2υ is a predetermined count value NPI (0
0001100), the output level of the detection gate Ql becomes a low level and outputs a detection signal (19a). This signal (19a) causes the RS flip-flop)
is set, and the level of the pulse signal output terminal (2) changes from low level to high level. Binary counter at time t2? The binary output of υ is (0000101
1), the output level of the detection gate QQ returns to the high level, and c1 detection is completed. The output of the detection gate αq is determined at times t3, t5. Similarly, it becomes low level at time ty, and changes to high level at time (4, t6, t8. Therefore, °c1 detection gate Q9 outputs the detection signal (19a) four times, and the binary signal to be detected is Binary output values other than output °C also detect signal (
19a) is output. However, after the data is preset in the binary counter, the detection gate 4 first outputs the detection signal (19a) at time 1. The binary output of the binary counter 3υ at that time is the binary value (000,01100) to be detected.
There's a lot of people. Since the RS flip-flop □□□ is set by the first detection signal Q (19a), the output of the Rs flip-flop changes from low level to high level at time tt, and at times t, , ts, and t7, the output of the RS flip-flop becomes high level. (19a).

is output, the pulse signal/signal output terminal (
) is at a high level. @ Mr. J 1 child, time t1
3, when the binary output of the binary counter ■υ reaches a predetermined count value NP2 (11010100), the output level of the detection gate (4) becomes a low level and outputs a detection signal (20a). This signal (20a) resets the RS flip-flop 4, and the level of the pulse signal output terminal (c) changes from the 1 level to the low level. The detection signal (20a) is also output at times t1s, j2+, and Lzs, but the pulse signal output Q (c) has already reached the low level, and there is no threat to the Nobun Rusu signal (22a). I won't give it. Therefore, the pulse width of the output pulse signal (22a) is determined by the period of the clock signal (17a) input to the binary counter eυ and the predetermined count value NPI, N1)2.

The number of high-order bits of the pinary counter to be detected is determined when the output pulse signal jJ (22a) is at the 71 level. It is selected so that the output of the detection signal (2Oa) of the push-out gate window ends while the pulse signal (22a) is at a low level.

The reason why the inverted output of the lower one unit stage of the binary counter ■υ is detected is to prevent a hazard that may occur when detecting the count value.

Next, another embodiment of the present invention will be explained below.

FIG. 4 is a circuit diagram of a pulse signal generator in another embodiment, and the same components as those shown in FIGS. do.

In this embodiment, a plurality of eight deaf pals 218 are generated. The following points differ between Fig. 4- and Fig. 2. In Fig. 4, a 6-output gate (C) and an R8 flip-flop) are added, and the binary value to be detected is NF2 (,,11011100) at the input terminal of the detection gate (C).
, l, then J=2. = 4°L = 2, the top 2
A flip-flop (6) that serves as the non-inverting output terminal of the unit stage, the inverting output terminal of the lower two unit stages, and the logic level 10 among the four intermediate unit stages.
A total of 5 wires are connected to the inverting output terminal of the flip-flop (3) (4) (5) and the detection gate (c).
It is not connected to °C. The output terminal of the detection gate (c) is connected to the set terminal (S2) of the RS flip-flop).
The Q output terminal of the RS flip-flop is connected to the reset terminal (R2) of the RS flip-flop.

FIG. 5 is a time chart showing the operation of the circuit shown in FIG. 4. Note that the same signals as those shown in FIG. 3 are given the same reference numerals, and their explanations will be omitted. (24a) is the output signal of the detection gate (c), and (24a) is the inverted output signal of the RS flip-flop 4.

A binary counter (c) counts the clock signal. At time t, the binary output of the pinary counter υ becomes a predetermined count value NP8 (1101110
0), the output of the detection gate (c) becomes low level and outputs the h1 detection signal (24a).

This signal e (24a) causes the RS flip-flop (c) to
is set, and the output level of the pulse signal output terminal (E) changes from high level to low level. Furthermore, the detection gate (c) quickly detects times t11, t13, t17, and t1.
At 9, t21, and t23, °C also outputs a detection signal (24a) and attempts to set the flip-flop (c). However, the reset terminal (R2
) At time t13, the Q output terminal of the flip-flop (A) is connected and the Q output becomes low level.
The flip-flop (E) is reset and the pulse signal output terminal (E) becomes high level. Since the pulse signal output terminal ■ is connected to the inverted output terminal ◎ of the flip-flop 4, the set signal J to the detection gate (c) after time t13 is inhibited by the Q signal of the flip-flop (2), and the pulse Do not apply this effect to the signal output terminal.

As shown in (25Q) in FIG. 5, the non-inverting output terminal (9) of the flip-flop is influenced by the set signal (24a) which is the detection signal of the detection gate (2).

In this way, by using the first pulse signal (22a) to generate the second pulse signal (25a)'x, a binary counter? The number of wires connecting υ and the double gate (c) can be reduced. The pulse width of the second pulse signal (25a) is determined by the count value NP8 that the convenience gate (c) first detects, the count value NP2 at which the Q output of the flip-flop becomes a lone bell, and the binary counter. wb + Clock signal input (
17a).

Effects of the Invention As explained above, according to the present invention, the number of wires and elements can be reduced by M, and the degree of integration can be improved, for example, in an integrated circuit, so that its industrial utility value is extremely high. be.

[Brief explanation of drawings]

Ayu Figure 1 is a circuit diagram of a conventional pulse double phase generator, Figure 2 is a circuit diagram of a pulse signal generator according to an embodiment of the present invention, Figure 8 is a time chart of the circuit shown in Figure 2, and Figure 4 is a circuit diagram of a pulse signal generator according to an embodiment of the present invention. The figure is a circuit diagram of a pulse signal generator in another embodiment, and Figure 5 is a time chart of the circuit shown in Figure 4. (1) - (8) ... flip-flop, (9) - head
...Program terminal, αZ...Clock signal input terminal, ((2)...Set signal input terminal, (11@J H
...Detection gate, taU...Binary down counter, 翰...RS flip-flop, cap 1...Pulse signal output terminal. Agent Yoshihiro Morimoto Figure 4

Claims (1)

[Claims] 1. A binary counter formed by cascading N4a (N22) unit stages using a flip-flop having a set function as a unit stage;
Binary of the first predetermined count value NPI of the counter
In the output state, when the upper L unit stages (L≧2) are connected, the non-inverting output end of the unit stage that becomes 11. of the binary 7 output and the inverting output end of the unit stage that becomes 10J, and the lower one For unit stages (J≧1), the inverting output terminal or non-inverting output terminal is set, and for the intermediate stages (K=N-J-L), the predetermined binary output NPI is 0. The first detection gate to which the inverting output terminal or the non-inverting output terminal of the unit stage serving as V IJ is connected to the input terminal, respectively, and the binary output state of the predetermined count value NP2 of the binary counter indicated by @u, the upper For the unit stage 1, the non-inverting output of the unit stage which becomes 11. of the predetermined binary output and the inverting output of the unit stage which becomes rOJ, and for the lower one unit stage 1, the inverting output or the non-inverting output of the unit stage becomes rOJ. The inverting output terminal is also a predetermined binary output N for intermediate stages.
a second detection gate whose input terminal is connected to an inverted output terminal or a non-inverted output terminal of a unit stage in which P2 becomes r is connected to a set input terminal, and an output terminal of the second detection gate is connected to a reset input terminal.