JPS61294925A - Power-on reset circuit - Google Patents

Abstract

PURPOSE:To make circuit constitution simple and easy and to keep the generation of a reset release signal constant by constituting the titled circuit of a AND gate or a OR circuit and two resistors only. CONSTITUTION:In applying power, a voltage at a reset signal output terminal 6 is equal to a power voltage level (logical value '1') via a resistor 4 and a flip-flop or the like in an integrated circuit is reset. In such a case, two inputs are at logical '1' and a AND ate circuit 5 keeps to output a reset signal. A clock signal is fed to a clock pulse input terminal 1 and a clock pulse goes to a common level, that is, logical '0', then an output of the AND gate circuit 5 goes to a common level, a reset release signal is outputted from a reset signal output terminal 6 to release the reset of the flip-flop or the like in the integrated circuit. Thus, the AND gate 5 keeps outputting the reset release signal independently of the inputted clock pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power-on reset circuit that sets the initial state of flip-flops and the like included in a digital circuit when power is turned on.

[Conventional technology]

Conventionally, circuits such as those shown in FIGS. 3 and 4 have been used as power-on reset circuits for this purpose.

Among these, the circuit shown in FIG. 3 has a structure in which a capacitor 15 is charged from a power supply terminal 13 through a resistor 14, and a signal is outputted via a gate circuit 16 consisting of a monostable multivibrator or the like.

It had become a reality. That is, before the charging voltage of the capacitor 15 exceeds the threshold voltage of the gate circuit 16, the output of the gate circuit 16 continues to output a voltage approximately equal to the power supply voltage, a so-called reset signal. When the threshold voltage is exceeded, the output goes to ground level and outputs a so-called reset release signal. By the way, the circuit shown in FIG. 4 is a circuit in which the resistor 14 in the circuit shown in FIG.
The principle is the same as the circuit shown in FIG.

[Problem that the invention seeks to solve]

The conventional power-on reset circuit described above has a gate circuit consisting of a capacitor, a monostable multivibrator, etc., and therefore has a problem in that the structure is complicated. Furthermore, in digital circuits, it is difficult to incorporate capacitors into integrated circuits, and even if they are incorporated, they cannot be configured with high precision.Due to manufacturing variations during mass production, the time required for the reset release signal to be generated after power-on may vary. There was a problem that it was not constant.

Each of the four hooks of the present invention has a simple and easy circuit configuration, and also has a power-on function that constantizes the generation of the reset release signal.
The purpose is to provide a reset circuit.

[Means for solving problems]

In order to achieve the above object, the power-on reset circuit according to the present invention includes a two-person gate circuit such as an AND gate circuit or an OR gate circuit, and two resistors. One end of the first resistor is connected, and the output terminal of the two-person gate circuit is connected to one end of the second resistor and the other end of the input terminal of the two-person gate circuit, and the first resistor and the second resistor are connected. Connect the other end of the resistor to the power supply terminal or ground terminal, and
The input terminal of the two-person gate circuit connected to the first resistor is connected to the clock pulse input terminal, and the reset signal and reset release signal are output from the output terminal of the two-person gate circuit.

〔Example〕

Next, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 shows a first embodiment of the present invention, in which an AND gate circuit is used as a two-person gate circuit. In Figure 1, l is a clock pulse input terminal, 2 is a power supply terminal connected to a power supply, 3 is a first resistor, 4 is a second resistor, 5 is an AND gate circuit having two input terminals, and 6 is an integrated This is a reset signal output terminal connected to a reset terminal of a flip-flop or the like in a circuit (not shown).

When the power is turned on, the voltage at the reset signal output terminal 6 becomes equal to the power supply voltage level (logical value "1#") via the resistor 4t'', and the 7 lip-flops etc. of the integrated circuit are reset. At this time, the two input terminals of the AND gate circuit 5 are
Since it is connected to the power supply through both the first resistor 3 and the second resistor 4, the two inputs are both logic ``1#'', and the AND gate circuit 5 continues to output the reset signal.

Next, a clock signal is applied to the clock pulse input terminal 1, and the clock pulse is at the ground level, that is, the logical value '
0", the output of the AND gate circuit 5 becomes the ground level, and a reset release signal is output from the reset signal output terminal 6, and the reset of the 7 lip-flops etc. in the integrated circuit is released. At this time, the AND gate circuit 5 Since one end of the output terminal and the input terminal of the circuit 5 are connected, both inputs of the AND gate circuit 5 are at ground level (logical value "o'). Next, a clock pulse at the power supply voltage level (logical value ""1#) is input to the clock pulse input terminal 1, but since the other end of the input terminal of the AND gate circuit 50 is not connected to the clock pulse input terminal 1, The input is at the ground level (logical value "O"), and the output of the AND gate circuit 5 remains at the ground level (logical value "O").

Therefore, from now on, the AND gate circuit 5 continues to output all reset release signals regardless of the input clock pulse.

FIG. 2 shows a second embodiment of the present invention, in which, like a TTL semiconductor integrated circuit, the reset signal is at the ground level (logical value "O") and the reset release signal is at the power supply voltage level (logical value "O"). This is a power-on reset circuit for an integrated circuit with a value of 1'', and an OR gate circuit is used as a two-person gate circuit. In FIG. 2, 7 is an OR gate circuit, and 8 is a ground terminal.

When the power is turned on, the reset signal output terminal 6 becomes the ground level (logical value ""0#) through the resistor 4, and the flip-flops etc. are reset (next, a clock signal is sent to the clock pulse input terminal 1). When the clock pulse reaches the power supply voltage level, that is, the logical value ``1'', the output of the OR gate circuit 7 reaches the power supply voltage level (the logical value 11).
), the reset of flip-flops, etc. is released. At this time, the output terminal and one end of the input terminal of the OR gate circuit 7 are connected, so the input of the OR gate circuit 70 is set to a logical value "1".Then, the clock pulse goes to ground level (logical value "o"), but C) R.
The input terminals that are not connected to the clock pulse input terminal 1 of the gate circuit 7 are at the power supply voltage level (logical value "1").
), the output of the OR gate circuit 7 remains at the power supply voltage level (logical value "'1"'), and thereafter the output of the OR gate circuit 7 receives the reset release signal regardless of the clock pulse. Keep putting it out.

〔Effect of the invention〕

As explained above and as follows, the present invention consists of only one AND gate circuit or OR gate circuit, which can be said to be a basic gate circuit for digital circuits, and two resistors, which can be easily incorporated into digital circuits. Simple and easy.

In addition, the first clock pulse after power-on is either the power supply voltage level (logical value ``1#'') or the ground level (logical value ``''
Since the reset release signal is generated when the reset release signal becomes 0"), the time at which the reset release signal is generated is always synchronized with the clock signal, and the generation of the reset release signal is constant regardless of manufacturing variations in integrated circuits. It has the effect of being able to be converted into

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIGS. 3 and 4 are circuit diagrams of a conventional example. 1... Clock pulse input terminal 2... Power supply terminal 3, 4... Resistor 5... AN
D gate circuit 6...Reset signal output terminal 7...OFL gate circuit 8...Ground terminal Patent applicant NEC Corporation representative Patent attorney Inoro Jusai Figure 1, Figure 2

Claims (1)

[Claims] Consisting of one 2-input gate circuit and two resistors, 2
One end of the input terminal of the input gate circuit and one end of the first resistor are connected, and the output terminal of the two-input gate circuit and the second resistor are connected.
one end of the resistor and the other end of the input terminal of the two-input gate circuit are connected, and the other ends of the first resistor and the second resistor are connected to a power supply terminal or a ground terminal, and further, the first resistor 1. A power-on reset circuit characterized in that an input terminal of a two-input gate circuit connected to a clock pulse input terminal is connected to the clock pulse input terminal, and a reset signal is taken out from an output terminal of the two-input gate circuit.