JPS6041820A - Semiconductor integrated logical circuit device - Google Patents

Abstract

PURPOSE:To set a specific internal logical circuit to a desired state by using a steady-state logical output of an integrated logical circuit device as a clock to convert an input signal from an output terminal into a latched state setting internal signal. CONSTITUTION:When a state setting external signal phi is inputted to an output terminal 4, a logical output B holds, e.g., ''0'' logical output independently of a steady-state logical output A, an output K of a latch circuit D-FF9 has temporarily a 0 output different from the state that the semiconductor integrated logical circuit device 1 performs the steady-state operation and is converted into a different state setting internal signal. Thus, an FF frequency divider 7 is reset simultaneously from the frequency dividing operation and set to the initial state.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated logic circuit device having a test function capable of setting a specified internal logic circuit to a desired state.

If you want to check whether a semiconductor integrated logic circuit device is performing logic operations correctly, there is a method that sequentially inputs different signals to the input terminals and uses the corresponding output signal as the expected value. Usually done. However, if the target logic circuit device includes sequential circuits or the like, it is often impossible to set the logic state of these sequential circuits to a desired state simply by applying a test signal to the input terminal. Conventionally, this problem has been solved by providing a separate new terminal for a specific test i; i>. however,
As semiconductor integrated circuit technology has recently become increasingly advanced in terms of aging and miniaturization, the number of external output pins that can be obtained by equipment is approaching its structural limit. However, there is no room for expansion, and we are in an extremely difficult situation. In particular, logic circuit devices sometimes have hundreds of external output pins, so the problem is very serious, and the state of the logic circuit can be easily set without providing special test terminals. It is strongly desired to obtain it.

SUMMARY OF THE INVENTION In view of the above requirements, an object of the present invention is to provide a semiconductor logic circuit device in which an output terminal also functions as a state setting terminal for a specific internal logic circuit.

The semiconductor integrated logic circuit device of the present invention has a circuit mechanism that constantly latches an output terminal outputting through a constant current logic output buffer of an internal logic circuit and an output side logic output of the output buffer using the constant logic output as a clock. The output buffer is configured to include two stages, and outputs a state setting external signal of a specific internal logic circuit input to the output terminal to make the logic output different from the normal state in response to a change in output side logic output. and state setting internal signal generation circuit means for converting the internal signal of the latch output.

According to the present invention, a state setting external signal inputted from a specific output terminal is converted into a latched state setting internal signal using the steady logic output of the integrated logic circuit device as a clock. The logic circuit can be set to a desired state. Therefore, since the conventional additional terminal for setting the state is not required, it is possible to achieve a tremendous effect in increasing the degree of integration and miniaturization of semiconductor integrated logic circuits.

The present invention will be explained in detail below with reference to the drawings.

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, in which the state to be set is shown in the case where the logic circuit is a flip-flop frequency divider circuit. The logic circuit device 1 includes an internal logic circuit 5 which outputs a steady logic output 8 to an output terminal 4 via an output buffer 3 in response to an input signal from an input terminal 2, and an internal chronograph 8 6 that outputs a steady logic output of 1/2 to 1.
Using the flip-flop frequency divider circuit 7 of the specific internal logic circuit which outputs each frequency division wave of /16 and the steady logic output A as clock input, the output 1t'l logic output B of the output buffer 3 is always latched, This state setting internal signal generating circuit 8 includes a state setting internal signal generating circuit 8 that outputs a latch output K of "1" or 0'°. It can be easily configured with an ordinary D-type flip-flop 9 (hereinafter referred to as D-FF) that always latches with a steady logic input A input to the input terminal and outputs a latch output K from an output terminal Q. As in the example, the input buffer sofa 10 may be inserted at the data terminal.In this way, the logic output B is given a further delay, and the latching operation becomes more reliable.

When the semiconductor integrated logic circuit device 1 performs a steady logic operation and outputs a steady logic output AV to the output terminal 4 via the output buffer 3, the signal content of the logic output B appearing on the output side of the output circuit 3 Needless to say, is equal to the steady logic output A itself, but the phase is delayed from the steady logic output A by the output buffer 3. Here, the output terminal 4 is connected to the ground as shown by the dotted line in the figure. When the state setting external signal φ is temporarily input to forcefully clamp it at L level, the signal content 11 of logic signal B changes greatly, and the state is clamped completely regardless of the presence or absence of the steady logic input. , this L level is maintained.

At this time, since the state setting external signal φ is input from the output terminal 4 to the output side 1 of the output buffer 3, the operation of the logic circuit 5 is not disturbed. However, the input means for the state setting external signal φ may be temporarily forced to a negative potential for the output J terminal 4, or may be temporarily set to a high potential for a short period of time.
In any case, the state setting external signal φ input to output terminal 4
acts to change the signal content of logic output i3 in the steady state. Therefore, this state setting external No. 9 φ is the state setting internal signal generating circuit 80 latch (λ low right [″).

According to
Converts to state setting external No. 9 to 3 forces.

FIGS. 2 and 3 are explanatory diagrams of the operation of the state setting internal signal generation circuit.

FIG. 2 is an explanatory diagram of the operation when the semiconductor integrated logic circuit device 1 performs a steady σ,) logic operation, in which constant ``A'' logic outputs from the internal logic circuit 5 A)j +)-F, F9
It is input to the 1/J clock terminal C and is input to the logic output Bii clock terminal of the output circuit 3. As already explained in 75hlc, logic output B is the steady logic output JA
It is a phase-delayed signal that has the same signal content as the giant. Therefore, this logic output B is latched at the falling edge to the steady logic input (for example, always constant) 9) Logic IJj
The latch output K having the output voltage J is outputted from the output terminal Q as a state setting internal signal.

Further, FIG. 3 shows an explanatory diagram of the operation when the state setting external signal φ is input to the output terminal 4. In this case, the signal content of the logic output B maintains a logic output of, for example, 0'', regardless of the presence or absence of the steady logic output while the state setting external signal φ is input, so it is the same as the steady logic input. The launch output, where the fall of A is latched at the edge, is different from the normal operation of the semiconductor integrated logic circuit device 1, and temporarily has a logic output of "0". .That is,
The state setting external signal φ input to the output terminal 4 is kept at the constant value by this latch function! F! ! State setting ljE Li1 (converted to signal,
Similarly, +1 can be output from the output terminal Q.

The launch outputs having the above two specific logic contents are input as state setting internal signals to the reset terminals (2) of the flip-flops 11, 12, 13 and 14 of the flip-flop frequency dividing circuit 7, respectively. Here, each 7
Assuming that the reset terminal R of the flip-flop operates at L level, the flip-flop frequency divider circuit 7 continues the frequency division jjb operation without any trouble during normal operation when a logic output of "1" is input. When a logic output of 0" is input and the state is set from the outside, these flip-flops are reset all at once. Set to initial state.

The above describes the case where D-F and F are used in the latch circuit to set the initial state of one specific internal logic circuit, that is, a flip-flop frequency divider circuit, but other latch circuits can be used. It goes without saying that this method can be used, but it can also be implemented to set the state of any specific internal logic circuit. For example, it can be used as a test start signal for an internal test circuit, or it can be set to, for example, 23:59 by driving a time display device. Since all of these state settings can be performed using logic output terminals without adding test terminals, this has an extremely large effect on the structural design of semiconductor integrated logic circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, and FIGS. 2 and 33 are diagrams illustrating the operation of a signal generation circuit in the state setting internal 1. 1... Semiconductor integrated logic circuit device, 2...
・Input terminal, 3... Output vane 7a, 4...
...Output terminal, 5...Internal logic circuit, 6...
...Internal clock input, 7...Flop/flop frequency divider circuit, 8...State setting internal signal generation circuit, 9...D-data/f-regulator 7 resop・71:'
l knob, 10...manual buffer, 11,12゜13.14...puff flip -70 knob, A...
...Steady logic output, B...Output side logic output of output vanor 7a, K...Latch output.

Claims (1)

[Claims] The output terminal includes an output terminal for outputting a steady logic output of an internal logic circuit via an output buffer, and a latch circuit means for always latching the output side logic output of the output buffer using the steady logic output as a clock input. A state setting internal circuit that converts a state setting external signal of a specific internal logic circuit inputted into an internal signal of a latch output whose logic output is different from that in a steady state regardless of a change in the logic output of the logic output on the output side of the output sofa. 1. A semiconductor integrated logic circuit device comprising: signal generation circuit means.