JPH0437314A - Frequency division circuit - Google Patents

Abstract

PURPOSE:To simplify the test of a circuit to be tested and to decrease the test time by adding an initial value setting circuit to the frequency dividing circuit so that the phase of a basic clock and a 1/2 frequency division clock is always fixed at the time of starting the test. CONSTITUTION:When a clock timing is inputted from a clock input terminal CLKIN, a basic clock CLK2f is outputted through inverters 1, 2. Simultaneously, a 1/2 frequency division clock CLKf is outputted from a frequency dividing circuit comprising latch circuits 3, 4 applying 1/2 frequency division to the clock inputted from the input terminal CLKIN. An initial value setting circuit 5 sets the output QC of the master side latch circuit 3 to an H level to fix the phase of a basic clock CLK2f and the 1/2 frequency division clock CLKf at the time of starting clock application.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a frequency dividing circuit for testing a circuit under test that handles a circuit that generates a clock whose frequency is divided by 1/2 from a basic clock.

[Conventional technology]

An example of a conventional general frequency dividing circuit is shown in FIG. 5 and will be described.

In the figure, 1 and 2 are inverters connected in series, 3
, 4 are latch circuits that frequency divide the input clock by 1/2, and these latch circuits 3 and 4 constitute a frequency divider circuit.

FIG. 6 is a time chart used to explain the operation of FIG. 5.

Next, the operation of the frequency dividing circuit shown in FIG. 5 will be explained with reference to FIG. 6.

In FIG. 5, when the clock timing shown in FIG. 6(8) is inputted to the clock input terminal CLK IN, the basic clock CLK2f shown in FIG. 6+b) is output through the inverter 1.2. At the same time as this, a frequency dividing circuit consisting of latch circuits 3 and 4 divides the frequency of the manually inputted clock from the clock input terminal CLKIN by 1/2.
Outputs the frequency-divided clock CLKf. Q and QC indicate the output of the latch circuit 3.

[Problem to be solved by the invention]

In the conventional frequency divider circuit as described above, the 1/2 frequency divided clock CLKf is at the "H" level at the start of clock application from the clock input terminal CLK IN, but is actually "L".
Since it is set to one of the levels and is unstable, it is difficult to set an expected value pattern when testing a circuit under test. Therefore, it is necessary to select the expected value pattern according to the state of the circuit under test, which reduces the load on the tester operator.
In addition, there was a problem in that the test time increased.

The present invention was devised to solve the above problem, and it is possible to easily test a circuit under test having a circuit that generates a clock whose frequency is divided by 1/2 from the basic clock, and to shorten the test time. The purpose is to obtain a frequency dividing circuit that can perform the following steps.

[Means to solve the problem]

The frequency divider circuit according to the present invention has a basic clock and 1/2 of the basic clock.
When testing a circuit under test that includes a circuit that generates a frequency-divided clock, an initial value setting circuit is added so that the phases of the basic clock and the 1/2 frequency-divided clock are always fixed at the start of the test. be.

[For production]

In this invention, at the start of clock application,
The phases of the basic clock and the 1/2 frequency divided clock are fixed.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a frequency dividing circuit according to the present invention.

In FIG. 1, the same reference numerals as in FIG. 5 indicate corresponding parts, and 5 is an initial value setting circuit.

In the present invention, an initial value setting circuit 5 is added so that the phases of the basic clock and the 1/2 frequency divided clock are always fixed at the start of the test.

Figure 2 is a time chart used to explain the operation of Figure 1.
(1) shows the clock applied to the clock input terminal CLKIN, and lyl is the basic clock CL
K2f, (c) is a representation of the 1/2 frequency divided clock CLKf.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

In FIG. 1, the clock input terminal CLKIN and the second
When the clock timing shown in FIG. 2(a) is input, the basic clock CLK2f shown in FIG. 2(b) is output after passing through inverters 1 and 2. At the same time, a frequency divider circuit consisting of latch circuits 3 and 4 divides the clock input from the clock input terminal CLKIN into 1/2.
A 1/2 frequency-divided clock CLKf shown in FIG. 3(C) is output.

At this time, the initial value setting circuit 5 sets the master side (previous stage)
The output of the latch circuit 3 is set to the QC1HJ level, and the basic clock CLK2f and the 1/2 frequency divided clock CL are set at the output QC1HJ level of the latch circuit 3.
Fix the phase of Kf.

In the embodiment shown in FIG. 1, the output QC of the latch circuit 3 on the master side (previous stage) of the frequency dividing circuit is initially set to the "H" level, but a circuit showing another embodiment of the present invention As shown in FIG. 3, the same effect can be expected even if the output Q of the master side (previous stage) latch circuit 3 is initially set to the "L" level by the initial value setting circuit 6. In FIG. 3, the same parts as in FIG. 1 are given the same reference numerals, and their explanation will be omitted.

FIG. 4 is a transistor configuration diagram of the latch circuit 3 of the master gI4 (previous stage) in FIG. 3.

A gate circuit 7 using an N-channel transistor shown in FIG. A similar effect can be obtained by adjusting the transistor size in the gate circuit 8 using P-channel transistors and setting the initial value.

[Effect of the invention] As explained above, this invention has a basic clock and part 1.
In a circuit under test that has a circuit that generates a clock divided by 2, an initial value setting circuit is added to ensure that the phase of the basic clock and the 1/2 clock is always fixed at the beginning of the test. , there is no need to select expected value patterns according to the state of the circuit under test, and the test time can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the frequency dividing circuit according to the invention, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 3 is a circuit diagram showing another embodiment of the invention. Fig. 4 is a transistor configuration diagram of the latch circuit of the master @ (first stage) in Fig. 3, Fig. 5 is a circuit diagram showing an example of a conventional frequency divider circuit, and Fig. 6 is a timing diagram used to explain the operation of Fig. 5. It is a chart. 3.4... Latch circuit, 5.6... Initial value setting circuit.

Claims (1)

[Claims] When testing a circuit under test that has a circuit that generates a basic clock and a clock divided by 1/2, the phases of the basic clock and the 1/2 clock are set to initial values so that they are always fixed at the start of the test. A frequency divider circuit characterized by adding a setting circuit.