JP3240713B2 - Polyphase clock generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-phase clock generation circuit, and more particularly to a multi-phase clock generation circuit for generating a multi-phase clock used in a digital circuit such as a microcomputer.

[0002]

2. Description of the Related Art Conventionally, a multi-phase clock generation circuit of this type uses a circuit as shown in FIG.

According to FIG. 5, flip-flops (hereinafter referred to as FFs) 1 to 4 which are divided by inputting a basic clock and reset by a reset signal are provided, and an output signal Q ₁ (101) of an FF 1 is provided. And FF3 output signal inversion Q ₃ (30
2) input to the AND gate 10, the output signal with the clock phi _0. The output signal Q ₁ (101) of FF1 and F
F3 output signal Q ₃ in the (301) input to AND gate 11, its output signal with the clock phi _1. FF1 and the output signal inverted Q ₁ and the output signal Q ₃ of FF3 (301) of the input to the AND gate 8, to the output signal and phi _2. FF1 and the output signal inverted Q ₃ output signal inverted Q ₁ and FF3 of input to an AND gate 9, the output signal phi ₃
As a multi-phase clock signal.

FIG. 6 is a timing chart for explaining the operation of the conventional multiphase clock generation circuit. As can be seen from the timing chart, a clock Q ₁ ,
Generate inverted Q ₁ , Q ₃ , and inverted Q ₃ . From these clocks, four-phase clocks φ ₀ , φ ₁ , φ ₂ , and φ ₃ having the same pulse width as one cycle of the basic clock and being delayed by one cycle of the basic clock are generated. .

Next, as an example in which a multi-phase clock operates during a high level period, a conventional four-phase clock microcomputer uses a conventional four-phase clock in which all clocks have the same pulse width. A description will be given based on actual example data.

FIG. 7 shows that a microcomputer made of complementary MOS (CMOS) has φ ₀ , φ ₁ , φ ₂ , φ ₃
Among the four-phase clock operation of the operation times t1, t2 in need during the period of the clock phi ₁ and phi _2, a diagram illustrating an example of the graph showing the relationship between the power supply voltage at that time.

[0007] According to the graph shown in FIG. 7, the ratio of the required operation time t2 during required operation time t1 and the clock phi ₂ periods during the clock phi ₁ is, 6V power supply voltage from 2V
The ratio is about 3 to 2. However, comparing the differences Δt _2V and Δt _5V between the required operation times t1 and t2, the difference Δt 5V at the power supply voltage of _5V is about 15 nsec.
On the other hand, the difference Δt _2V when the power supply voltage is 2 V increases to about 70 nsec. That is, in the vicinity of the power supply voltage 5V, when the combined pulse width of 4-phase clocks to the clock phi ₁ needs an operation time t1 50 nsec, the clock phi ₂ period that required time t2 is about 35 nsec, clock phi ₂ Is about 15 nsec.

However, when the pulse width of four clocks is adjusted to about 200 nsec of the required operating time t1 of the clock φ ₁ period near the power supply voltage 2 V, the required operating time t2 of the clock φ ₂ period is approximately 130 nsec. It can be seen that the pulse width of φ ₂ is about 70 nsec and increases.

This is because when operating at a low power supply voltage,
This is one of the factors that significantly lower the operation speed of the microcomputer.

[0010]

The pulse width of the clock for each phase of the multi-phase clock generated by the above-described conventional multi-phase clock generation circuit is the same regardless of the operating conditions such as the power supply voltage. On the other hand, in a digital circuit using a multi-phase clock, the pulse width of the clock for each phase required for operating the digital circuit differs depending on the operating conditions, such as when the power supply voltage is lowered. .

However, in the conventional multi-phase clock generation circuit, when the power supply voltage changes, a multi-phase clock having a different pulse width for each phase clock is supplied without changing the clock cycle of the entire multi-phase clock. Could not.

An object of the present invention is to eliminate the above-mentioned drawbacks, so that the pulse width of one of the adjacent two phases is widened and the other is not changed without changing the clock speed of the entire multiphase clock. The pulse width is to generate a multi-phase clock set narrow.

A feature of the present invention is that a fundamental clock of an arbitrary frequency used in a microcomputer is cascaded.
Four times the basic clock with multiple flip-flops
Dividing means for generating a divided clock having a period of
First and second clock delay means having the same delay value
And the output of the first stage flip-flop of the frequency dividing means.
The phase of the output clock having one polarity is changed by the first delay
A first delay clock delayed by the delay value
One of the flip-flop outputs of the third stage of the peripheral means
Of the first stage by logic synthesis with the output clock of
Clock fall timing of flip-flop output
The pulse width is wider than the pulse width determined by
First clock generating means for generating a first clock
And the other of the first-stage flip-flop outputs
The phase of the output clock having the same delay by the second delay means.
The second delay clock delayed by the extension value and the third stage clock.
Of the flip-flop output with the one polarity output clock
The first clock has a pulse width determined by logic synthesis.
The second clock whose pulse width is narrowed by the delay value
And second clock generating means for generating the first clock.
Falling of the clock and rising of the second clock
Synchronization timing same, the and corresponds to the supply voltage with the period from the rising of the first clock to the falling timing of the second clock to maintain a phase relationship corresponding to two clocks of the base clock first One
Preliminary have a multi-phase clock generation means for pulse width different from the second clock, in that the multi-phase clock generation hand stage is formed on the same semiconductor substrate of the complementary structure with the microcomputer.

Further, the first and the second delay hand stages
Is a time required for one cycle or less of the basic clock, within a range of a power supply voltage at which the microcomputer can operate, and a first required operation required by the microcomputer during the period of the first clock. Time and the second
The delay value may be set in advance so as to be within the time difference from the second required operation time required during the clock period and to be about 1/2 of the difference.

[0015]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and FIG. 2 is a timing chart for explaining its operation.

According to FIG. 1, there are cascaded FF1 to FF4 which receive and divide the frequency of a basic clock and are reset by a reset signal. The output signal Q ₁ (101) of the FF1 is provided.
When the output signal inverted Q ₃ of FF3 and (302) input to the AND gate 10, the output signal phi _0. An AND gate 11 combines a signal 701 obtained by delaying the output signal Q ₁ (101) of the FF1 through a delay circuit 7 composed of an even number of inverters for a predetermined time and an output signal Q ₃ (301) of the FF3.
Entered, the output signal phi _1. The output signal inversion to Q ₁ FF1 inputs the output signal Q ₃ with an even number of signal 601 from via the delay circuit 6 comprising inverter delays a predetermined time FF3 (301) to the AND gate 8, the output signal Is φ ₂ . FF1 output signal inverted Q ₁ (1
02) and the inverted output signal Q ₃ (301) of FF3
The multi-phase clock signal is input to the D gate 9 and its output signal is set to φ ₃ to obtain a multiphase clock signal.

FIG. 2 is a timing chart for explaining the first embodiment. As can be seen from this timing chart, the clock Q ₁ (101) and the inverted Q ₁ (1
02), Q ₃ (301) and inverted Q ₃ (302) using four-phase clocks φ ₀ , φ ₁ , φ ₂ , φ _{3 having} different pulse widths.
Have gained.

Next, the operation of the multi-phase clock generation circuit according to the first embodiment of the present invention will be described.

A reset signal and a basic clock are input to the FFs 1 to 4 shown in FIG. 1 at the timings shown in FIG. 2, and the divided clocks Q ₁ (101), Q ₁ (102), Q
₃ (301) and inverted Q ₃ (302) are obtained. Further, the clock Q ₁ (101) is input to the delay circuit 7 to obtain a signal 701 delayed by １ ／ cycle of the basic clock as shown in the timing chart of FIG.

By taking the logical product of this clock Q ₃ (301) and the delayed signal 701, the phase difference (FIG.
Of a) only the pulse width of the clock phi ₁ is widened (W ₁ in FIG. 2).

On the other hand, the clock inversion Q ₁ (102) is input to the delay circuit 6, and the signal 601 delayed by one-fourth cycle of the basic clock as shown in the timing chart of FIG.
Get. The delayed signal 601 and the clock Q ₁ (1
Phase difference by taking the logical product of 02) (pulse width of FIG. 2 a) by the clock phi ₂ so that the narrowing (W ₂ in FIG. 2).

For clocks φ ₀ and φ ₃ , respectively, clock Q ₁ (101) and clock inversion Q ₃ (302)
Is obtained by the logical product of the clock inversion Q ₁ (102) and the clock inversion Q ₃ (302) as in the conventional example.

As described above, the delay circuits 6, 7
Inserted relationship clocks phi ₁ and phi ₂ of the clock phi
The pulse width of ₁ (W _{1 in} FIG. 2) is wider by _１ ／ period of the basic clock (a in FIG. 2), and the pulse width of clock φ ₂ (W _{2 in} FIG. ₂ ) is 1 It is narrowed by / 4 cycle (a in FIG. 2).

Next, an example in which the multi-phase clock generation circuit of the present invention is used in a one-chip microcomputer having a four-phase clock operation CMOS structure will be described based on actual data.

[0026] Figure 7 is a one-chip microcomputer of the clock phi ₁ required operation period required during phi ₂ periods t1, t2, and the delay time Dt by the delay circuits 6 and 7,
It is an example in which the relationship with the power supply voltage is graphed. In order to facilitate the explanation, the delay time D
t is added.

According to FIG. 7, the delay time Dt by the delay circuits 6 and 7, the time ratio of the clock phi ₁ and phi ₂ must operation period that is required during the t1, t2, depend on the power supply voltage It turns out that it is almost constant. That is, the ratio of t1, t2, and Dt is approximately 6: 4: 1.

[0028] From the above results, the delay circuits 6 and 7 which can fastest operating the microcomputer of adding a multi-phase clock generation circuit of the present invention, necessary operations requiring during the clock phi ₁ and phi ₂ Time difference Δt between times t1 and t2
It can be understood that a delay circuit having a delay time which is equal to or more than 1/2 and smaller than the time difference Δt is sufficient.

[0029] By using this delay circuit, in the microcomputer can operate the power supply voltage range, necessary operation time requires for the duration of the clock phi ₁ and phi ₂ t1,
A multi-phase clock generation circuit that automatically generates a multi-phase clock having a pulse width of a clock equal to the ratio of t2 in accordance with the power supply voltage can be obtained.

That is, a circuit delay characteristic of a microcomputer having the multi-phase clock generation circuit of the present invention,
This is an advantage of using the similarity with the delay characteristics of the delay circuits 6 and 7 in the multi-phase clock generation circuit of the present invention. next,
A second embodiment of the present invention will be described.

FIG. 3 is a circuit diagram of the second embodiment, and FIG.
Is a timing chart for explaining the operation.

The difference from the first embodiment is that the delay circuit 6 is eliminated and the output signal 701 of the delay circuit 7 is used as one input signal of the AND gate 8 via the inverter 12 as the output signal 121. Yes, the rest is the same as in the first embodiment, so a detailed description is omitted. Since the second embodiment uses only one delay circuit, it is excellent in terms of chip size and cost when actually manufacturing a microcomputer.

In the first embodiment, the delay circuit is φ ₁ ,
As described in the example applied to the generation of φ ₂ , the clock φ ₀ ,
It is also possible to apply to each of the multiphase clocks including phi _3, it is the same second embodiment.

[0034]

As described above, the multi-phase clock generation circuit according to the present invention requires a different clock pulse width for each phase of the multi-phase clock depending on conditions, such as during low voltage operation. By controlling the delay amount of the delay circuit of the multi-phase clock generation circuit, the pulse width of the clock can be changed according to the operation speed of the microcomputer having the multi-phase clock generation circuit. Accordingly, there is an effect that a multi-phase clock capable of operating a digital circuit such as a microcomputer using the multi-phase clock generated by the present circuit at the highest speed can be supplied.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a multiphase clock generation circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first exemplary embodiment of the present invention.

FIG. 3 is a circuit diagram of a multi-phase clock generation circuit according to a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the second embodiment of the present invention.

FIG. 5 is a circuit diagram showing an example of a conventional multi-phase clock generation circuit.

FIG. 6 is a timing chart for explaining the operation of the conventional example.

FIG. 7 is a diagram showing circuit delay example data of a CMOS one-chip microcomputer.

[Explanation of symbols]

 1, 2, 3, 4 Flip-flop (FF) 101 Output signal Q of FF1₁ 102 Output signal inverted Q of FF1₁ 301 Output signal Q of FF3_Three 302 Output signal inverted Q of FF3_Three  6,7 Delay circuit 8,9,10,11 AND gate 12 Inverter φ₀, Φ₁, Φ_Two, Φ_Three Multiphase clock Dt Delay time characteristic by delay circuits 6 and 7 t1 φ of microcomputer₁Clock time
Characteristics of required operating time t2 φ of microcomputer_TwoClock time
Characteristics of required operation time △ t_2V Necessary operation of t1 and t2 at power supply voltage 2V
Time difference Dt Characteristics of delay time by delay circuits 6 and 7

Claims (2)

(57) [Claims] A plurality of flip-flops cascaded with a basic clock of an arbitrary frequency used in a microcomputer.
The frequency is divided by four times the basic clock by the flop.
The frequency divider that generates the lock and the same delay value
First and second clock delay means, and the frequency dividing means
Of the first stage flip-flop output of one polarity
The phase of the output clock by the first delay means by the delay value.
First delayed clock delayed and third stage of frequency dividing means
Output clock of one polarity among flip-flop outputs of
Output from the first stage flip-flop
Pulse width determined by fall timing of power clock
The first clock whose pulse width is wider by the delay value than
First clock generating means for generating a clock,
Output clock of the other polarity of the flip-flop output
In which the second phase is delayed by the second delay means by the delay value.
2 delay clock and the third stage flip-flop
Determined by logic synthesis with the output clock of the one polarity of force
A pulse width equal to the delay value of the first clock
The second clock for generating the second clock in which the pulse width becomes narrower
A lock generation means, and a fall of the first clock.
The rising timing of the second clock is synchronized with the
And, and maintains the phase relationship period from the rising of the first clock to the falling timing of the second clock corresponding to two clocks of the base clock Then
Said first and said both corresponding to the power supply voltage second black
Tsu pulse width of the clause have a different multi-phase clock generation means,
Multiphase clock generator circuit, wherein said multi-phase clock generation hand stage is formed on the same semiconductor substrate of the complementary structure with the microcomputer. Wherein said first and said second delay hand stage,
A time equal to or less than one cycle of the basic clock and within a power supply voltage range in which the microcomputer can operate;
And within a time difference between a first required operation time required by the microcomputer during the first clock period and a second required operation time required during the second clock period, and multiphase clock generation circuit of claim 1 wherein the chromatic said delay value set in advance to be a half near the time of the difference.