JP2006060436A - Synchronous digital filter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a device small-sized which is synchronized with a clock signal and to remove noise superposed on an input signal. <P>SOLUTION: The input signal is supplied to an input terminal D of a 1st flip-flop F/F1 and 1st input terminals of a positive input AND circuit AND1 and a negative input AND circuit AND2. The output signal of the 1st flip-flop F/F1 is supplied to 2nd input terminals of the positive input AND circuit AND1 and negative input AND circuit AND2. Output signals of the positive input AND circuit AND1 and negative input AND circuit AND2 are inputted to select signal terminals S1 and S0 of a multiplexer MUX, and data inputs to the multiplexer MUX are switched with the select signals, and the output signal of the multiplexer MUX is inputted to a 2nd flip-flop F/F2, which generates an output signal with an internal clock signal from a reference internal clock generation part OSC which is supplied to clock signal input terminals CLK of the 1st and 2nd flip-flops F/F1 and F/F2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a filter used for signal processing, and more particularly to a synchronous digital filter used for digital signal processing.

  Filters include those that perform analog signal processing and those that perform digital signal processing depending on the application of the equipment used.

  The former analog filter that performs analog signal processing uses a circuit configuration in which a signal is processed by a combination of a resistor and a capacitor, and then the signal is delayed by a receiver with hysteresis to shape the waveform.

As the digital filter for performing the latter digital signal processing, for example, a paging receiver or the like having a circuit configuration for removing a noise component of a digital signal demodulated from a received signal is used (see Patent Document 1).
JP-A-11-195963

  In recent years, the degree of integration of ASIC (Application Specific IC), which is an IC for specific users, has improved, and it is cheaper and more compact to pack as many functions as possible in an integrated circuit such as this ASIC. It is considered to incorporate a digital filter. However, in an integrated circuit such as an ASIC, there is a problem that it is impossible to incorporate a digital filter from the following.

  (B) When an integrated circuit such as an ASIC is not operated as a clock synchronization circuit, it is not fixed at which point in the clock signal the change in the input signal of the flip-flop occurs. In some cases, the integrated circuit such as the ASIC operates as a clock synchronization circuit.

  (B) In conventional digital filters, there is a filter that is asynchronous to the clock signal, but when the asynchronous signal is clock-synchronized with a flip-flop, it is not determined at what point in the clock signal the change in the input signal occurs. For this reason, there is a problem that the output of the flip-flop is not stable (an unstable state occurs) when the setup time and hold time cannot be secured.

  Therefore, in an integrated circuit such as an ASIC that requires a clock synchronization circuit in order to make the circuit operate accurately and stably from the above (a) and (b), if a digital filter is configured, the output of the flip-flops that configure the filter However, the digital filter could not be constructed.

  The present invention has been made in view of the above circumstances, and since a digital filter circuit can be configured in an integrated circuit such as an ASIC, it is not necessary to configure a digital filter outside the integrated circuit such as an ASIC. It is an object of the present invention to provide a synchronous digital filter that can be reduced in size and that can remove noise superimposed on an input signal.

  To achieve the above object, according to a first aspect of the present invention, a first flip-flop and a first input terminal to which an input signal is supplied, and the input signal of the first flip-flop are synchronized with an internal clock signal. The output signal is output when the second input terminal to which the first output signal is supplied matches the logical value of the signal transmitted to the first and second input terminals. And the negative input logical product circuit and the output signal of the positive and negative input logical product circuit are sent out as a selection signal, and a third output signal or “1” or “High” signal or “0” input by the selection signal. Alternatively, a “Low” level signal is switched, and a multiplexer that sends out these second output signals, and a second output signal that is sent out by the multiplexers are synchronized with an internal clock signal, and a third output signal is sent out. It is characterized by comprising a second flip-flop.

  According to a second aspect of the present invention, the first flip-flop and the first input terminal to which an input signal is supplied and the input signal of the first flip-flop are synchronized with an internal clock signal to send a first output signal. The second flip-flop and the second input terminal to which the output signal of 1 is supplied, and the first output signal input by the second flip-flop are synchronized with the internal clock signal to send out the second output signal. A third input terminal to which a second output signal is supplied, and a positive and negative input logical product circuit for transmitting an output signal when the logical values of the signals sent to the first, second and third input terminals match. The output signal of the positive and negative input AND circuit is sent as a selection signal, and a fourth output signal or a “1” or “High” signal or a “0” or “Low” level signal input according to the selection signal is output. Switch this And a third flip-flop for sending a fourth output signal in synchronism with the internal clock signal of the third output signal sent by the multiplexer. To do.

  According to a third aspect of the present invention, the first flip-flop and the first input terminal to which the input signal is supplied, and the input signal of the first flip-flop are synchronized with the internal clock signal to send out the first output signal. The second flip-flop and the second input terminal to which the output signal of 1 is supplied, and the first output signal input to the second flip-flop are synchronized with the internal clock signal to send out the second output signal. First positive and negative input logic for transmitting an output signal when the third input terminal to which the second output signal is supplied matches the logical value of the signal transmitted to the first, second and third input terminals The output signal of the product circuit and the first positive and negative input AND circuit is sent as a selection signal, and a fourth output signal or “1” or “High” signal or “0” or Turn off the “Low” level signal In other words, a first multiplexer that sends out these third output signals, and a third output signal that sends out a fourth output signal in synchronization with the internal clock signal of the third output signal that is sent out by the first multiplexer. A first group of digital filter circuits composed of flip-flops; first and second flip-flops and first input terminals to which the fourth output signal is supplied; and the input signals of the first to second flip-flops A fifth output signal is transmitted in synchronization with the clock signal obtained by dividing the clock signal by four, the 2-2 flip-flop and the second input terminal to which the fifth output signal is supplied, and the 2-2 A fifth output signal inputted to the flip-flop is synchronized with a clock signal obtained by dividing the internal clock signal by 4, and a sixth output signal is sent out. A second positive and negative input AND circuit for transmitting an output signal when the logical value of the signal transmitted to the first terminal, the second and third input terminals coincides, and the second positive and negative input The output signal of the AND circuit is sent as a selection signal, and the eighth output signal, “1” or “High” signal, or “0” or “Low” signal is switched according to the selection signal. A second multiplexer that sends out an output signal and a seventh output signal that the second multiplexer sends out are synchronized with a clock signal obtained by dividing the internal clock signal by four and send out an eighth output signal. -2 comprising a second group of digital filters comprising flip-flops.

  According to a fourth aspect of the present invention, the first flip-flop and the first input terminal to which the input signal is supplied and the input signal of the first flip-flop are synchronized with the internal clock signal and the first output signal is transmitted. 1st group of positive and negative input logical products for transmitting an output signal when the logical values of the second input terminal to which one output signal is supplied and the signals transmitted to the first and second input terminals coincide with each other A circuit, a first flip-flop to which an input signal is supplied and a first input terminal, and the input signal of the first flip-flop is synchronized with an internal clock signal to send a first output signal. The second flip-flop and the second input terminal to which the output signal is supplied, and the first output signal input by the second flip-flop are synchronized with the internal clock signal to send out the second output signal. Output signal is supplied A third input terminal and a second group of positive and negative input logical product circuits for sending an output signal when the logical values of the signals sent to the first, second and third input terminals coincide with each other; The output signals of the group and second group positive input AND circuits and the output signals of the first group and second group negative input AND circuits are sent as selection signals, and the selection signals are switched according to the filter time setting, A multiplexer that switches between a fourth output signal, a “1” or “High” signal, or a “0” or “Low” signal that is input according to the switched selection signal, and sends out these third output signals; And a third flip-flop for sending a fourth output signal in synchronization with the internal clock signal, and an output signal for setting the number of stages of the flip-flop and the filter time Increasing the input signal of the operation to the multiplexer, it is possible to increase the filter time.

  As described above, according to the present invention, an integrated circuit such as an ASIC can obtain an accurate and stable output signal by clock synchronization, and can eliminate noise superimposed on the input signal and relay chattering. By increasing the delay time element, the accuracy of the filter can be improved, the delay time element can be efficiently increased, and the filter time can be easily varied.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration explanatory view showing a first embodiment of the present invention, including a case where it is incorporated in an integrated circuit such as an ASIC (not shown). The input signal is supplied to the input terminal D of the first flip-flop F / F1, and is also supplied to the first input terminals of the positive input AND circuit AND1 and the negative input AND circuit AND2.

  The first output signal from the output terminal Q of the first flip-flop F / F1 is supplied to the second input terminals of the positive input AND circuit AND1 and the negative input AND circuit AND2.

  When the logical values at the input terminals of the positive input AND circuit AND1 and negative input AND circuit AND2 match, an output signal is sent from the outputs of the positive and negative input AND circuits AND1 and AND2, and the signal is sent to the multiplexer. The selection signal is input to the selection signal terminals S1 and S0 of the MUX.

  The third output signal of the second flip-flop F / F2 is supplied to the data input terminals I0 to I3 of the multiplexer MUX, and the output signal (second output signal) of the multiplexer MUX is the second flip-flop F / F2. Is supplied to the input terminal D.

  OSC is a reference internal clock signal generator, and the internal clock signal from the internal clock signal generator OSC is supplied to the clock signal input terminals CLK of the first and second flip-flops F / F1, F / F2.

  The operation of the first embodiment configured as described above will be described with reference to the timing chart of FIG. As shown in FIG. 2, the input signal input to the first flip-flop F / F1 is synchronized with the internal clock signal supplied to the clock signal input terminal CLK, and the output terminal Q of the first flip-flop F / F1. The first output signal is transmitted to

  When the first output signal and the input signal are supplied to the positive input AND circuit AND1, the input signal shown in FIG. 2 is “+ s”, and the first output signal of the first flip-flop F / F1 is “+ q”. ", The logical values match, and the AND circuit output signal is supplied as a selection signal to the selection signal terminal S0 of the multiplexer MUX.

  Further, the negative input AND circuit AND2 has the same logical value when the input signal shown in FIG. 2 is "-s" and the first output signal of the first flip-flop F / F1 is "-q", and the multiplexer An AND circuit output signal is supplied as a selection signal to the selection signal terminal S1 of the MUX.

  The multiplexer MUX has a third output signal supplied to the data input terminals I0 and I3 or a “1” or “High” signal supplied to the data input terminal I1 according to a selection signal supplied to the selection signal terminals S0 and S1. The second output signal is sent by switching the “0” or “Low” signal supplied to the data input terminal I2.

  That is, when the output of the positive input AND circuit AND1 is “1” and the output of the negative input AND circuit AND2 is “0”, the multiplexer MUX selects the data input terminal I1 and outputs “1”, and the second A second output signal is supplied to the input terminal D of the flip-flop F / F2.

  Further, when the output of the positive input AND circuit AND1 is “0” and the output of the negative input AND circuit AND2 is “1”, the multiplexer MUX selects the data input terminal I2 and outputs “0”, and the second A second output signal is supplied to the input terminal D of the flip-flop F / F2.

  Further, when both the outputs of the positive input AND circuit AND1 and the negative input AND circuit AND2 are “0” or “1”, the multiplexer MUX selects the data input terminal I0 or I3, and the second flip-flop F / F2 The third output signal is maintained as it is (the signal input to the data input terminal I0 or I3 is input to the second flip-flop F / F2 as it is).

That is, the condition that the two AND circuits AND1 and AND2 are the same is when the input signal (the input terminal D of the first flip-flop F / F1) is different from the first output signal of the first flip-flop F / F1. ON-OFF (“1”-
When “0” or High-Low), the output signal is undefined.

  FIG. 3 is an explanatory diagram showing the configuration of the second embodiment of the present invention, and includes the case where it is incorporated in an integrated circuit such as an ASIC (not shown) as in the first embodiment. The second embodiment has a configuration in which one more flip-flop is added to the above embodiment. That is, in the second embodiment, the second flip-flop F / F2-1 is increased by one stage after the first flip-flop F / F1 to increase the filter time. For this reason, the positive input and negative input AND circuits AND3 and AND4 are configured at three input terminals.

  OSC is a reference internal clock signal generator, and the internal clock signal from the internal clock signal generator OSC is the clock signals of the first, second, and third flip-flops F / F1, F / F2-1, and F / F3. It is supplied to the input terminal CLK.

  In FIG. 3, the input signal is supplied to the input terminal D of the first flip-flop F / F1 and the first input terminals of the positive and negative input AND circuits AND3 and AND4. Further, the input signal supplied to the input terminal D of the first flip-flop F / F1 sends out the first output signal from the output terminal Q in synchronization with the internal clock signal. This is supplied to the input terminal D of the second flip-flop F / F2-1 and also supplied to the second input terminals of the positive and negative input AND circuits AND3 and AND4.

  Further, the first output signal supplied to the input terminal D of the second flip-flop F / F2-1 sends a second output signal from the output terminal Q in synchronization with the internal clock signal. The two output signals are supplied to the third input terminals of the positive and negative input AND circuits AND3 and AND4. The output signals of the positive and negative input AND circuits AND3 and AND4 are supplied as selection signals to the selection signal terminals S0 and S1 of the multiplexer MUX, as in the first embodiment.

  Next, the operation of the second embodiment will be described with reference to the timing chart shown in FIG. In FIG. 4, when the input signal is a solid line, the number of pulses is applied to the output of the second flip-flop F / F2 shown in the first embodiment and the output of the third flip-flop F / F3 shown in the second embodiment. There is no difference.

  However, when the input signal becomes a broken line, the number of pulses of the second output signal of the second flip-flop F / F2-1 shown in the second embodiment increases by one. However, in the fourth output signal of the third flip-flop F / F3, the “1” or “High” signal supplied to the input terminal I1, or “0” or “Low” supplied to the input terminal I2, the number of pulses Does not increase. That is, it is filtered. Note that the multiplexer MUX sends a third output signal.

  When the third output signal is supplied to the input terminal D of the third flip-flop F / F3, the third output signal is synchronized with the internal clock signal at the output terminal Q of the fourth flip-flop F / F3. A fourth output signal is obtained.

  As described above, in the second embodiment, the filter time can be made longer than in the first embodiment. In FIG. 4, the pulse indicated by a broken line is obtained by extending the disturbance time of the input signal waveform in order to clarify the difference between the first embodiment and the second embodiment. Other operations are the same as those in the first embodiment.

  FIG. 5 is a structural explanatory view showing a third embodiment of the present invention, and includes a case where it is incorporated in an integrated circuit such as an ASIC (not shown) as in the first embodiment. In this third embodiment, instead of increasing the number of flip-flop stages receiving an input signal in cascade, a digital filter circuit is multiplexed in parallel. The configuration of the second group of digital filter circuits is the same as that of the first group of digital filters. The delay time element of the filter circuit configuration is configured to have four times. With this configuration, the filter time can be increased at a stretch. Note that the same parts as those in the second embodiment are denoted by the same reference numerals.

  The configuration will be described with reference to FIG. In FIG. 5, the configurations of the first group and the second group of digital filter circuits are the same as those of the second embodiment, and are partially different in signal supply.

  For example, in the second group of digital filter circuits, the internal clock signal of the reference internal clock signal generation unit OSC is divided into four clock signals as the 1-2 to 3-2 flip-flops F / F1-2, F / F2 -2, F / F3-2 clock signal terminal CLK is supplied. The fourth output signal transmitted from the output terminal Q of the flip-flop F / F3-1 is supplied to the input terminal D of the first and second flip-flops F / F1-2, and the positive / negative input logical product circuit Also supplied to the first input terminals of AND3-1 and AND4-1.

  The fifth output signal from the output terminal Q of the 1-2nd flip-flop F / F1-2 is supplied to the input terminal D of the 2-2 flip-flop F / F2-2, and the positive and negative input logics. It is supplied to the second input terminals of the product circuits AND3-1 and AND4-1.

  The sixth output signal from the output terminal Q of the 2-2 flip-flop F / F2-2 is supplied to the third input terminals of the positive and negative input AND circuits AND3-1 and AND4-1. The output signals of the positive and negative input AND circuits AND3-1 and AND4-1 are supplied as selection signals to the selection signal terminals S0 and S1 of the second multiplexer MUX, as in the second embodiment.

  The seventh output signal sent from the output terminal of the second multiplexer MUX is supplied to the input terminal D of the 3-2 flip-flop F / F3-2. The eighth output signal sent from the third-second flip-flop F / F3-2 is supplied to the data input terminal I0 or I3 of the second multiplexer MUX.

  Note that the signals supplied to the input terminals D of the first to second to third-second flip-flops F / F1-2 to F / F3-2 are divided into four internal clock signals as in the above embodiment. An output signal is sent to each output terminal Q in synchronization with the clock signal that has been rotated.

  FIG. 6 is an operation timing chart of the third embodiment. In FIG. 6, the timing chart up to the clock signal obtained by dividing the internal clock signal by 4 is the same as that of the second embodiment.

  When the fourth output signal sent from the third flip-flop F / F3-1 constituting the first group of digital filter circuits is inputted to the 1-2th flip-flop F / F1-2, the frequency is divided by 4 The fifth output signal of the first and second flip-flops F / F1-2 is as shown in FIG. For this reason, the sixth and eighth output signals of the 2-2 and 3-2 flip-flops F / F2-2 and F / F3-2 also become as shown in the figure, and the filter time increases at a stretch.

  FIG. 7 is an explanatory diagram showing the configuration of the fourth embodiment of the present invention, and includes the case where it is incorporated in an integrated circuit such as an ASIC (not shown) as in the first embodiment. In the fourth embodiment, the first embodiment and the second embodiment are combined, and first and second group positive and negative input AND circuits AND1 to AND4 and a multiplexer for switching filter time setting data. MUX-1 and MUX-2 are provided.

  The output signals of the first group and second group positive input AND circuits AND1 and AND3 are the ON-OFF signals of the multiplexer MUX-1, and the first group and second group negative input AND circuits AND2, AND4. Is an ON-OFF signal of the multiplexer MUX-2.

  With these ON-OFF signals, it is possible to freely select whether to use the digital filter according to the first embodiment or the digital filter according to the second embodiment.

  The selected digital filter becomes a selection signal of the multiplexer MUX, the data input of the multiplexer MUX is switched by the selection signal, and the output signal is input to the third flip-flop F / F3.

  With the configuration described above, the filter time can be increased indefinitely by increasing the number of flip-flop stages and the number of input signals of the multiplexer operating with the output signal of the filter time setting. Note that the timing chart of the fourth embodiment is the same as that of the first embodiment or the same as that of the second embodiment, depending on the ON-OFF signal input to the filter time setting.

BRIEF DESCRIPTION OF THE DRAWINGS Structure explanatory drawing which shows 1st Embodiment of this invention. The timing chart for describing operation | movement of 1st Embodiment. Structure explanatory drawing which shows 2nd Embodiment of this invention. The timing chart for describing operation | movement of 2nd Embodiment. Structure explanatory drawing which shows 3rd Embodiment of this invention. The timing chart for describing operation | movement of 3rd Embodiment. Structure explanatory drawing which shows 4th Embodiment of this invention.

Explanation of symbols

F / F1 to F / F3 ... 1st to 3rd flip-flops
F / F1-2 to F / F3-2 ... 1-2 to 3-2 flip-flop
AND1, AND3, AND3-1 ... Positive input AND circuit
AND2, AND4, AND4-1 ... negative input AND circuit
OSC: Reference internal clock signal generator
MUX, MUX-1, MUX-2 ... Multiplexer

Claims (4)

The first flip-flop and the first input terminal to which the input signal is supplied, and the input signal of the first flip-flop are synchronized with an internal clock signal to send a first output signal. A positive input circuit and a negative input logical product circuit for transmitting an output signal when a logical value of a signal sent to the first input terminal and the second input terminal supplied with the second input terminal matches;
The output signal of the positive and negative input AND circuit is sent as a selection signal, and the third output signal, “1” or “High” signal, or “0” or “Low” level signal to be input is switched according to the selection signal. A multiplexer for sending out these second output signals;
A second flip-flop for sending a third output signal in synchronization with an internal clock signal for a second output signal sent by the multiplexer;
A synchronous digital filter comprising: The first flip-flop and the first input terminal to which the input signal is supplied, and the input signal of the first flip-flop are synchronized with an internal clock signal to send a first output signal. The second output signal is sent out by synchronizing the supplied second flip-flop and the second input terminal and the first output signal inputted by the second flip-flop with the internal clock signal. A positive and negative input logical product circuit that sends out an output signal when the logical values of the signals sent to the first, second and third input terminals match,
The output signal of the positive and negative input AND circuit is sent as a selection signal, and the fourth output signal, “1” or “High” signal, or “0” or “Low” level signal is switched according to the selection signal. A multiplexer for sending out these third output signals;
A third flip-flop for sending a fourth output signal in synchronization with an internal clock signal for a third output signal sent by the multiplexer;
A synchronous digital filter comprising: The first flip-flop and the first input terminal to which the input signal is supplied, and the input signal of the first flip-flop are synchronized with an internal clock signal to send a first output signal. The second output signal is sent out by synchronizing the supplied second flip-flop and the second input terminal and the first output signal inputted to the second flip-flop with the internal clock signal. A first input circuit that outputs an output signal when the logical values of the signals sent to the first, second, and third input terminals match, and
The output signal of the first positive and negative input logical product circuit is sent as a selection signal, and the fourth output signal or “1” or “High” signal or “0” or “Low” level input by the selection signal. A first multiplexer for switching signals and sending out these third output signals;
A first group of digital filter circuits comprising a third flip-flop for transmitting a fourth output signal in synchronization with an internal clock signal for a third output signal transmitted by the first multiplexer;
The 1-2 flip-flop and the first input terminal to which the fourth output signal is supplied, and the input signal of the 1-2 flip-flop are synchronized with a clock signal obtained by dividing the internal clock signal by four. A fifth output signal is sent out, and the second output terminal to which the fifth output signal is supplied is supplied with the second output flip-flop and the second input terminal. A sixth output signal is sent in synchronization with the clock signal obtained by dividing the clock signal by four, and sent to the third input terminal to which the sixth output signal is supplied, and to the first, second and third input terminals. A second positive and negative input AND circuit for sending an output signal when the logic values of the received signals match,
The output signal of the second positive and negative input AND circuit is sent out as a selection signal, and an eighth output signal, “1” or “High” signal, or “0” or “Low” signal is input by the selection signal. And a second multiplexer for sending out these seventh output signals;
A second group of digital signals composed of a third to second flip-flops for transmitting an eighth output signal in synchronization with a clock signal obtained by dividing the seventh output signal transmitted from the second multiplexer by an internal clock signal divided by four. Filters,
A synchronous digital filter comprising: The first flip-flop and the first input terminal to which the input signal is supplied, and the input signal of the first flip-flop are synchronized with an internal clock signal to send a first output signal. A first group of positive and negative input AND circuits for sending an output signal when the supplied second input terminal and the logical values of the signals sent to the first and second input terminals match;
The first flip-flop and the first input terminal to which the input signal is supplied, and the input signal of the first flip-flop are synchronized with an internal clock signal to send a first output signal. The second output signal is sent out by synchronizing the supplied second flip-flop and the second input terminal and the first output signal inputted by the second flip-flop with the internal clock signal. And a second group of positive and negative input AND circuits for sending output signals when the logical values of the signals sent to the first, second and third input terminals match,
The output signals of the positive input AND circuits of the first group and the second group and the output signals of the negative input AND circuits of the first group and the second group are sent as selection signals, and the selection signals are sent according to the filter time setting. And a multiplexer that switches between the fourth output signal, the “1” or “High” signal, the “0” or “Low” signal, which is input according to the switched selection signal, and sends these third output signals. ,
A third flip-flop for sending a fourth output signal in synchronization with an internal clock signal for a third output signal sent by the multiplexer;
A synchronous digital filter comprising:

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