JP2004200837A - Noise rejection method, noise canceller and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To ensure high reliability and noise canceling power while digitally rejecting noise superposed on a digital signal. <P>SOLUTION: D type flip-flops (DFF) 14 and 16 output signals S14 and S16 produced by delaying an input signal Sin every specified periods. If the signals S14 and S16 have an identical level, a combination circuit 2 sets a signal S2 at that identical level otherwise sets the signal S2 at the level of an output signal Sout in current period. That signal S2 is latched in a DFF 32 upon start of next period and delivered as the output signal Sout. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a noise removal method, a noise canceller, and a program suitable for use in a signal input unit of a digital circuit.
[0002]
[Prior art]
When noise is superimposed on a signal input to a digital circuit, a malfunction occurs in the digital circuit. Therefore, a noise canceller is often provided in a signal input stage of the digital circuit. In general, a noise canceller includes an RC filter circuit that performs low-pass filtering of an input signal, and a Schmitt trigger circuit that shapes the filtered signal (sets the signal level to either “0” or “1”). Is done. However, there is a problem that a capacitor required for an RC filter circuit occupies a large area on an LSI substrate when an attempt is made to convert a digital circuit into an LSI. Further, the use of an analog circuit such as an RC filter causes a problem that the noise canceling capability may be deteriorated depending on a manufacturing process, voltage conditions, and the like.
[0003]
For this reason, Japanese Patent Application Laid-Open Publication No. H11-163873 discloses a technique for digitally removing noise. In the technique disclosed in Patent Document 1, a signal change detection circuit for detecting a change (“0” → “1” or “1” → “0”) of an input signal, and a detected signal change timing as a reference There are provided a timing circuit for measuring the time during which the level after the change is held, and a flip-flop for latching an input signal in accordance with the latch signal.
[0004]
Here, the timing circuit is configured to output the latch signal to the flip-flop when the counted time reaches a predetermined reference time. Conversely, if the input signal changes before the reference time has elapsed, no latch signal is output. That is, if the time from when the input signal changes to when it changes again is less than the reference time, the signal within the period is regarded as noise. Then, an output signal of the flip-flop, that is, a latch result is output as a result of removing noise from the input signal.
[0005]
Patent Documents 2 and 3 disclose other noise canceling techniques. These techniques use a shift register or the like to delay an input signal every predetermined clock cycle, thereby simultaneously outputting input signals over the past several cycles, and performing a majority operation on the plurality of past input signals. And outputting the majority operation result as a signal from which noise has been removed.
[0006]
[Patent Document 1] Japanese Patent Application Laid-Open No. 05-014144 [Patent Document 2] Japanese Patent Application Laid-Open No. 05-006455 [Patent Document 3] Japanese Patent Application Laid-Open No. 07-212209 [0007]
[Problems to be solved by the invention]
However, the technology disclosed in Patent Literature 1 lacks reliability. That is, when the timing at which the clock circuit outputs the latch signal coincides with the timing at which the input signal changes, the signal latched by the flip-flop becomes indefinite, and an erroneous signal is latched. Further, according to the techniques disclosed in Patent Literatures 2 and 3, there is a problem that noise canceling ability is remarkably inferior when trying to remove frequent noises such as keyboard chattering. As an example, consider a circuit that determines an output signal by majority decision of input signals in the past “3” cycles. When this circuit is supplied with an input signal that is repeated such as "1", "0", "1", "0",... Every clock cycle, "1", "0" , "1", "1" is output, and in the next cycle, "0" is output by majority, "0", "1", "0". When this is repeated, the output signal becomes a signal that repeats as "1", "0", "1", "0",... Every clock cycle, indicating that no noise has been removed.
The present invention has been made in view of the above circumstances, and has as its object to provide a noise elimination method, a noise canceller, and a program capable of securing high reliability and noise canceling capability while digitally removing noise.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, the present invention is characterized by having the following configuration. The contents in parentheses are examples.
In the noise removing method according to the first aspect, a step of generating a plurality of delay signals (S14, S16) obtained by delaying the input binary signal (Sin) at predetermined intervals, and the steps of generating a plurality of delay signals having the same value. If there is, the same value is used as the operation result (S2); otherwise, the output binary signal (Sout) of the current cycle is used as the operation result (S2). And (12) outputting the operation result (S2) as an output binary signal (Sout) in the next cycle.
According to a second aspect of the present invention, there is provided a noise canceller which executes the noise removing method according to the first aspect.
According to a third aspect of the present invention, there is provided a program for executing the noise removing method according to the first aspect.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
1． First embodiment
1.1. Next, the configuration of the noise canceller according to the first embodiment of the present invention will be described with reference to FIG.
In the figure, reference numeral 12 denotes a D-type flip-flop (hereinafter, referred to as DFF), and its data input terminal D is supplied with an input signal Sin which is a binary signal via a buffer 10. The clock signal CLK is supplied to the clock input terminal CK of the DFF 12, the signal of the data input terminal D is latched at the rise of the clock signal CLK, and the latched signal is output via the data output terminal Q. The reset input terminal SAN of the DFF 12 is supplied with a reset signal RST of negative logic. When the reset signal RST falls from "1" to "0", the output signal of the data output terminal Q is forcibly reset to "1" regardless of the signal state of the data input terminal D or the like. Thereafter, when the reset signal RST rises from “0” to “1”, the output signal switches according to the signal state of the data input terminal D and the like.
[0010]
Similarly, 14, 16, and 32 are DFFs, and a clock signal CLK is supplied to the clock input terminal CK, and a reset signal RST is supplied to the reset input terminal SAN. The output signal S12 of the DFF 12 is supplied to the data input terminal D of the DFF 14, and the output signal S14 of the DFF 14 is supplied to the data input terminal D of the DFF 16. As a result, the signals S14 and S16 become signals obtained by delaying the signal S12 for each cycle of the clock signal CLK.
[0011]
Next, reference numerals 18, 26 and 28 denote AND circuits, reference numeral 20 denotes a NOR circuit, reference numerals 22 and 30 denote OR circuits, and reference numeral 24 denotes an inverter. The combinational circuit 2 outputs the following signal S2 based on the signals S14 and S16 and the output signal Sout of the DFF 32.
(1) If the signals S14 and S16 have the same value, the signal S2 is set to the same value.
(2) In cases other than the above (1), the signal S2 is set to the same value as the output signal Sout.
In the DFF 32, the signal S2 is latched with the rise of the clock signal CLK, and the latched result is output as a new output signal Sout.
[0012]
The DFF 12 in the first stage is provided for a measure against metastable. "Meta stable" means that when the rising of the clock signal CLK and the rising of the input signal to the DFF overlap, the output of the first stage DFF becomes unstable. In the present embodiment, the first-stage DFF 12 is used only for the countermeasure against metastable, and the operation in the combinational circuit 2 uses the output signals of the second-stage DFFs 14 and 16. , Can be sufficiently suppressed.
[0013]
1.2. Operation of First Embodiment Next, the operation of this embodiment will be described with reference to FIG. In the figure, a clock signal CLK has a predetermined cycle, and its rising timing is assumed to be times t0, t1, t2,..., T18. Note that these times are referred to as “clock timing”. In the illustrated example, the reset signal RST falls to “0” at time t01, and rises to “1” at time t21 thereafter. At the time of the fall, the values latched in the DFFs 12, 14, 16, and 32 are forcibly reset to "1". After that, even after the reset signal RST rises to "1", as long as the input signal Sin is "1", "1" is continuously latched in each of the DFFs 12, 14, 16, and 32. The signal is held at "1".
[0014]
Next, it is assumed that the input signal Sin falls to "0" at time t31. This "0" signal is latched by the DFF 12 at the timing of time t4, and the signal S12 falls to "0". Since the signal S12 is latched by the DFF 14 at time t5, the signal S14 falls to "0" at time t5 as shown.
[0015]
Next, when the input signal Sin rises to "1" at the subsequent time t51, the "1" signal is latched by the DFF 14 at the rising timing of the clock signal CLK after "2" times, that is, at time t7, and the signal S14 rises. Similarly, in the example of FIG. 2, the input signal Sin is switched at times t71, t81, t101, t121, t131, and t141, and the level after the switching is held until the next clock timing. Further, the level of the signal S14 is switched at the next clock timings t9, t10, t12, t14, t15, and t16. The output signal S16 of the DFF 16 has the same waveform as the signal S14 and is a signal delayed by one clock cycle with respect to the signal S14.
[0016]
An operation result based on these signals S14 and S16 and the output signal Sout is output as a signal S2. The signal S2 is latched by the DFF 32 and output as an output signal Sout of the next cycle. In FIG. 2, when the input signal Sin and the output signal Sout are compared with each other, the section in which the clock timing of the input signal Sin occurring within the duration of the constant signal level is "1" or less (in the signals S12, S14 and S16, The section whose duration is "1" clock cycle) is set to the same signal level in the output signal Sout as in the preceding and following sections. In other words, in this embodiment, the section in the input signal Sin is regarded as noise, and the result of removing the section is output as the output signal Sout.
[0017]
As described above, in the present embodiment, the signal S2, that is, the output signal Sout is updated on the condition that the signals S14 and S16, which are the delay results of the input signal Sin over "2" clock cycles, are the same, so that high noise The ability to cancel can be demonstrated. That is, even if the input signal Sin is a signal that repeats, for example, “1”, “0”, “1”, “0”,... Every clock cycle, the output signal Sout is changed to “1” or “1”. It can be stabilized at 0 ".
[0018]
2． Second Embodiment Next, the configuration of a noise canceller according to a second embodiment of the present invention will be described with reference to FIG. Note that, in FIG. 3, parts corresponding to the respective parts in FIG. 1 are given the same reference numerals, and descriptions thereof will be omitted.
In the figure, DFFs 52, 54, and 56 are configured similarly to the DFFs 12, 14, and 16 described above. Further, a DFF 57 is connected to a stage subsequent to the DFF 56. As a result, in the DFF 52, the input signal Sin is latched every clock cycle, and the result is output as the signal S52. The DFFs 54, 56, and 57 output signals S54, S56, and S57, which are obtained by sequentially delaying the signal S52 by "1" clock cycle.
[0019]
Next, 58, 66, and 68 are AND circuits, 60 is a NOR circuit, 62 and 70 are OR circuits, and 64 is an inverter, and these constitute the combinational circuit 4. The combinational circuit 4 outputs the following signal S4 based on the signals S54, S56, S57 and the output signal Sout of the DFF 72.
(1) If the signals S54, S56 and S57 have the same value, the signal S4 is set to the same value.
(2) In cases other than the above (1), the signal S4 is set to the same value as the output signal Sout.
Then, the signal S4 is latched by the DFF 72 and output as the output signal Sout in the next clock cycle.
[0020]
As described above, in the present embodiment, the signal S2, that is, the output signal Sout is updated on the condition that the signals S54, S56, and S57, which are the delay results of the input signal Sin over "3" clock cycles, are the same. High noise canceling ability can be exhibited. That is, a section in which the clock timing of the input signal Sin occurring within the duration of the constant signal level is "2" times or less (a section in which the duration of the signals S52, S54 and S56 is "2" clock cycles or less). Is regarded as noise, and the result of removing the noise is output as the output signal Sout.
[0021]
Further, the present embodiment can exhibit a higher noise canceling ability than the first embodiment. First, in the present embodiment, similarly to the first embodiment, the input signal Sin is a signal that repeats, for example, “1”, “0”, “1”, “0”,. Even if this is the case, the output signal Sout can be stabilized at "1" or "0". Further, according to the present embodiment, noise that changes every two clock cycles, such as “1”, “1”, “0”, “0”, “1”, “1”,. Even if the output signal Sout is superimposed on the signal Sin, the output signal Sout can be stabilized at "1" or "0".
[0022]
3． Modifications The present invention is not limited to the above-described embodiment, and various modifications are possible as follows, for example.
(1) In the first embodiment, based on the continuity of the delay signal over "2" clock cycles, and in the second embodiment, based on the continuity of the delay signal over "3" clock cycles, It is determined whether or not to update the output signal Sout in the clock cycle of (1). However, the required number n of delay signals (that is, the number of DFFs) is superimposed on the signal waveform originally included in the input signal Sin and the input signal Sin. It may be set to a natural number of “4” or more according to the length of noise (the number of clocks) or the frequency of occurrence of noise.
[0023]
(2) In each of the above embodiments, each DFF is configured such that when the reset signal RST falls to “0”, the output signal of the data output terminal Q is forced to “1”. However, instead of these DFFs, those whose output signal is forcibly set to “0” in response to the fall of the reset signal RST may be used. As an example, FIG. 4 shows a circuit obtained by applying such a modification to the first embodiment. In FIG. 4, DFFs 42, 44, 46, and 48 are provided instead of the DFFs 12, 14, 16, and 32 in FIG. In these DFFs 42, 44, 46, and 48, when the reset signal RST supplied to the reset input terminal RAN falls from "1" to "0", the data output terminal Q regardless of the signal state of the data input terminal D or the like. Is forcibly reset to "0". Thereafter, when the reset signal RST rises from “0” to “1”, the output signal switches according to the signal state of the data input terminal D and the like.
[0024]
(3) Further, the same algorithm as that in the circuit diagrams of FIGS. 1, 3, and 4 or each of the above-described modified examples can be realized by a program (for example, a keyboard driver) that operates on a computer. Only this program can be stored in a recording medium such as a CD-ROM or a flexible disk and distributed, or can be distributed through a transmission path.
[0025]
【The invention's effect】
As described above, according to the present invention, when a plurality of delay signals have the same value, the same value is set to the output binary signal of the next cycle, and otherwise, the output binary signal of the current cycle is set. Since the value signal is set to the output binary signal of the next cycle, high reliability and noise canceling ability can be secured while digitally removing noise.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a noise canceller according to a first embodiment of the present invention.
FIG. 2 is a waveform chart of each part in FIG.
FIG. 3 is a circuit diagram of a noise canceller according to a second embodiment of the present invention.
FIG. 4 is a circuit diagram of a noise canceller according to a modification of the first embodiment.
[Explanation of symbols]
2, 4: combination circuit, 10: buffer, 20, 60: NOR circuit, 24, 64: inverter, 22, 30, 62, 70: OR circuit, 18, 26, 28, 58, 66, 68: AND circuit, 12, 14, 16, 32, 42, 44, 46, 48, 52, 54, 56, 57, 72: D-type flip-flop, D: data input terminal, Q: data output terminal, CK: clock input terminal, RAN , SAN: reset input terminal.

Claims (3)

A process of generating a plurality of delayed signals obtained by delaying the input binary signal at predetermined intervals,
When these delayed signals have the same value, the same value is used as the calculation result; otherwise, the calculation process uses the current period output binary signal as the calculation result,
Outputting the calculation result as an output binary signal in the next cycle for each of the cycles. A noise canceller that performs the noise removal method according to claim 1. A program for executing the noise removal method according to claim 1.

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