CN108781080B - Frequency divider circuit, splitter circuit, and semiconductor integrated circuit - Google Patents
Frequency divider circuit, splitter circuit, and semiconductor integrated circuit Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
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- H—ELECTRICITY
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- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
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Abstract
Comprising: a first frequency-division circuit unit (10) that divides a first clock signal to generate a first frequency-divided clock signal; a second frequency-dividing circuit unit (20) that generates a second frequency-divided clock signal by dividing a second clock signal having the same frequency as the first clock signal and having a first phase difference; a detection circuit (30) that detects a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit (50) that selects and outputs one of the second frequency-divided clock signal generated by the second frequency-dividing circuit unit and an inverted signal of the second frequency-divided clock signal. The selection circuit selects and outputs one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit, thereby generating and outputting a frequency-divided clock signal based on the second clock signal, the frequency-divided clock signal having a desired phase relationship with respect to the first frequency-divided clock signal.
Description
Technical Field
The invention relates to a frequency divider circuit, a splitter circuit, and a semiconductor integrated circuit.
Background
The frequency dividing circuit divides the frequency of an input clock signal by 1/N and outputs a clock signal having a period of N times (frequency of 1/N times). Fig. 7 is a diagram showing an example of the configuration of the frequency dividing circuit. Fig. 7 shows, as an example, a frequency dividing circuit that divides the frequency 1/2 of the input clock signal ICK and outputs a frequency-divided clock signal OCK having a period 2 times as long.
The frequency divider circuit shown in fig. 7 includes a D flip-flop circuit including two D latch circuits 701 and 702, and an inverter 703. The output of the D latch circuit 701 is input to the D latch circuit 702, and the output of the D latch circuit 702 is input to the D latch circuit 701 via the inverter 703. In addition, the output of the D latch circuit 702 is output as the frequency-divided clock signal OCK.
The D latch circuits 701 and 702 are driven by the clock signal ICK, and pass a data (signal) input to an output when a clock input is valid (true), and hold an output state when the clock input is invalid (false). That is, in fig. 7, when the clock signal ICK is at a low level, the D latch circuit 701 transfers the data input to the output, and the D latch circuit 702 holds the output. When the clock signal ICK is at a high level, the D latch circuit 701 holds an output, and the D latch circuit 702 transfers a data input to an output.
Therefore, in the frequency dividing circuit shown in fig. 7, every time the clock signal ICK rises (changes from low level to high level), the output of the D latch circuit 702 output as the frequency-divided clock signal OCK is inverted. Thereby, the frequency-divided clock signal OCK is generated after the frequency 1/2 of the input clock signal ICK.
Here, a case where the first clock signal and the second clock signal having the same frequency and a phase difference with respect to the first clock signal are divided by the frequency dividing circuits shown in fig. 7, respectively, is considered. The output of the frequency dividing circuit shown in fig. 7 has an uncertainty of 180 degrees in the phase of the frequency-divided clock signal due to the logic at the time of reset or the like, so that the resulting phase relationship between the two frequency-divided clock signals cannot be uniquely determined.
For example, the phase relationship between the frequency-divided clock signal OCKI and the frequency-divided clock signal OCKQ obtained by dividing the clock signal ICKI and the clock signal ICKQ having a phase difference of 90 degrees may be the phase relationship shown in fig. 8A or the phase relationship shown in fig. 8B. In fig. 8A, the divided clock signal OCKQ rises after the divided clock signal OCKI rises, and the divided clock signal OCKQ falls after the divided clock signal OCKI falls. In fig. 8B, the divided clock signal OCKQ falls after the divided clock signal OCKI rises, and the divided clock signal OCKQ rises after the divided clock signal OCKI falls. That is, the same phase relationship may be obtained between the input and the output, and the opposite phase relationship may be obtained between the input and the output.
By controlling the logic at the time of reset and the order of the clock signals after reset release, it is possible to control the frequency-divided clock signal OCKI and the frequency-divided clock signal OCKQ to have a desired phase relationship. However, if the input clock signals ICKI and ICKQ suddenly reverse due to the influence of noise or the like during operation and become unstable, the phase relationship between the divided clock signal octi and the divided clock signal OCKQ may change.
In a clock generating device that generates a plurality of divided clock signals whose phases are matched by dividing a single clock signal by a plurality of frequency dividing circuits, when a phase mismatch between the divided clock signals output from the plurality of frequency dividing circuits is detected, the internal states of all the frequency dividing circuits are simultaneously brought into the same state, thereby forcibly matching the phases of the divided clock signals (for example, patent document 1). Further, a frequency dividing method for generating a phase difference pulse signal of two output pulse train signals having the same phase relationship in a longer cycle by dividing an input phase difference pulse signal composed of two input pulse train signals has been proposed (for example, patent document 2).
Patent document 1: japanese laid-open patent publication No. 63-306732
Patent document 2: japanese laid-open patent publication No. 4-127617
Disclosure of Invention
The purpose of the present invention is to provide a frequency dividing circuit capable of generating a frequency-divided clock signal having a desired phase relationship based on a plurality of clock signals having phase differences.
One mode of the frequency dividing circuit includes: a first frequency-dividing circuit section that divides a first clock signal to generate a first frequency-divided clock signal; a second frequency-dividing circuit section that generates a second frequency-divided clock signal by dividing a second clock signal having the same frequency as the first clock signal and having a first phase difference; a detection circuit that detects a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit that selects and outputs one of the second frequency-divided clock signal generated by the second frequency-dividing circuit unit and an inverted signal of the second frequency-divided clock signal. The selection circuit selects one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal based on a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit.
The disclosed frequency dividing circuit can generate and output a frequency-divided clock signal based on the second clock signal, which maintains a desired phase relationship with respect to the first frequency-divided clock signal, by selecting and outputting one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal.
Drawings
Fig. 1 is a diagram showing an example of the configuration of a frequency dividing circuit according to an embodiment of the present invention.
Fig. 2A is a diagram showing an example of the operation of the monitor circuit in the present embodiment.
Fig. 2B is a diagram showing an example of the operation of the monitor circuit in the present embodiment.
Fig. 3 is a diagram showing an example of the configuration of the selection circuit in the present embodiment.
Fig. 4 is a diagram showing an example of the operation of the frequency dividing circuit in the present embodiment.
Fig. 5 is a diagram showing an example of the configuration of the splitter circuit in the embodiment of the present invention.
Fig. 6 is a diagram showing an example of the configuration of a semiconductor integrated circuit according to the embodiment of the present invention.
Fig. 7 is a diagram showing an example of the configuration of the frequency dividing circuit.
Fig. 8A is a diagram showing an example of the operation of the frequency dividing circuit shown in fig. 7.
Fig. 8B is a diagram showing an operation example of the frequency dividing circuit shown in fig. 7.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Fig. 1 is a diagram showing an example of a configuration of a frequency dividing circuit according to an embodiment of the present invention. The frequency dividing circuit in the present embodiment includes a first frequency dividing circuit 10, a second frequency dividing circuit 20, a monitoring circuit 30, a first selection circuit 40, and a second selection circuit 50.
The first frequency dividing circuit 10 inputs the clock signal ICKI and divides the frequency of the input clock signal ICKI to generate frequency-divided clock signals WCKI, WCKIX. The divided clock signals WCKI, WCKIX are differential signals whose phases are inverted from each other. The first frequency-dividing circuit 10 has two D latch circuits 11, 12 constituting a D flip-flop circuit. The D latch circuits 11 and 12 have a differential configuration of data input and data output.
The data output WCKIQ on the positive side of the D latch circuit 11 is input to the data input on the positive side of the D latch circuit 12, and the data output WCKIQX on the negative side of the D latch circuit 11 is input to the data input on the negative side of the D latch circuit 12. The positive data output WCKI of the D latch circuit 12 is inputted to the negative data input of the D latch circuit 11, and the negative data output WCKIX of the D latch circuit 12 is inputted to the positive data input of the D latch circuit 11.
The D latch circuits 11 and 12 are driven by a clock signal ICKI, and pass a data (signal) input to an output when a clock input is valid (true), and hold the output state when the clock input is invalid (false). That is, in the first frequency-dividing circuit 10, when the clock signal ICKI is at a low level, the D latch circuit 11 passes the data input to the data output, and the D latch circuit 12 holds the data output. When the clock signal ICKI is at a high level, the D latch circuit 11 holds the data output, and the D latch circuit 12 transfers the data input to the data output.
Therefore, in the first frequency-dividing circuit 10, the data outputs WCKI and WCKIX of the D latch circuit 12, which are frequency-divided clock signals, are inverted every time the clock signal ICKI rises (changes from low level to high level). Thereby, a frequency-divided clock signal WCKI in which the frequency 1/2 of the input clock signal ICKI is divided and a frequency-divided clock signal WCKIX which is an inverted signal of the frequency-divided clock signal WCKI are generated.
The second frequency dividing circuit 20 receives the clock signal ICKQ and divides the received clock signal ICKQ to generate frequency-divided clock signals WCKQ and WCKQX. The divided clock signals WCKQ, WCKQX are differential signals whose phases are inverted from each other. The clock signal ICKQ is a clock signal having the same frequency and a certain phase difference with respect to the clock signal ICKI, and in this example, the clock signal ICKQ is a clock signal delayed by 90 degrees in phase from the clock signal ICKI. The second frequency dividing circuit 20 has two D latch circuits 21, 22 constituting a D flip-flop circuit. The D latch circuits 21 and 22 have a differential configuration of data input and data output.
The data output WCKQQ on the positive side of the D latch circuit 21 is input to the data input on the positive side of the D latch circuit 22, and the data output wckqx on the negative side of the D latch circuit 21 is input to the data input on the negative side of the D latch circuit 22. The positive data output WCKQ of the D latch circuit 22 is input to the negative data input of the D latch circuit 21, and the negative data output WCKQX of the D latch circuit 22 is input to the positive data input of the D latch circuit 21.
The D latch circuits 21 and 22 are driven by the clock signal ICKQ, and pass a data (signal) input to an output when a clock input is valid (true), and hold an output state when the clock input is invalid (false). That is, in the second frequency dividing circuit 20, when the clock signal ICKQ is at a low level, the D latch circuit 21 transfers the data input to the data output, and the D latch circuit 22 holds the data output. When the clock signal ICKQ is at a high level, the D latch circuit 21 holds the data output, and the D latch circuit 22 transfers the data input to the data output.
Therefore, in the second frequency-dividing circuit 20, the data outputs WCKQ, WCKQX of the D latch circuit 22, which are frequency-divided clock signals, are inverted every time the clock signal ICKQ rises (changes from low level to high level). Thereby, a frequency-divided clock signal WCKQ obtained by dividing the frequency 1/2 of the input clock signal ICKQ and a frequency-divided clock signal WCKQX which is an inverted signal of the frequency-divided clock signal WCKQ are generated.
The monitor circuit 30 detects a phase relationship between the frequency-divided clock signal WCKI generated by the first frequency-dividing circuit 10 and the frequency-divided clock signal WCKQ generated by the second frequency-dividing circuit 20. The monitor circuit 30 outputs a monitor signal monosout indicating a phase relationship between the divided clock signal WCKI and the divided clock signal WCKQ based on the detected phase relationship.
The monitor circuit 30 has two D latch circuits 31, 32. The frequency-divided clock signal WCKI generated by the first frequency-dividing circuit 10 is input to the data input of the D latch circuit 31, and the data output of the D latch circuit 31 is input to the data input of the D latch circuit 32. The data output of the D latch circuit 32 is output as the monitor signal monosut.
Each of the D latch circuits 31, 32 is driven by the data output WCKQQ on the positive side of the D latch circuit 21 provided in the second frequency dividing circuit 20. The monitor circuit 30 passes a data (signal) input to an output when a data output WCKQQ as a clock input is active (true), and maintains an output state when the clock input is inactive (false). That is, in the monitor circuit 30, when the data output WCKQQ is low, the D latch circuit 31 transfers the data input to the data output, and the D latch circuit 32 holds the data output. When the data output WCKQQ is high, the D latch circuit 31 holds the data output, and the D latch circuit 32 transfers the data input to the data output.
With such a configuration, in the monitor circuit 30, when the phase relationship between the frequency-divided clock signal WCKI and the data output WCKQQ is as shown in fig. 2A, the monitor signal monosout becomes a high level. When the divided clock signal WCKI and the data output WCKQQ have a phase relationship as shown in fig. 2A, the phase relationship between the divided clock signal WCKI generated by the first frequency dividing circuit 10 and the divided clock signal WCKQ generated by the second frequency dividing circuit 20 is opposite to the phase relationship between the clock signal ICKI and the clock signal ICKQ. That is, the divided clock signal WCKQ is phase-advanced compared to the divided clock signal WCKI. Thus, the monitor circuit 30 outputs the monitor signal mono of high level in the case where the phase relationship between the frequency-divided clock signal WCKI and the frequency-divided clock signal WCKQ is opposite to the phase relationship between the clock signal ICKI and the clock signal ICKQ.
In the monitor circuit 30, when the phase relationship between the frequency-divided clock signal WCKI and the data output WCKQQ is as shown in fig. 2B, the monitor signal monosout becomes a low level. When the divided clock signal WCKI and the data output WCKQQ have a phase relationship as shown in fig. 2B, the phase relationship between the divided clock signal WCKI generated by the first frequency dividing circuit 10 and the divided clock signal WCKQ generated by the second frequency dividing circuit 20 is the same as the phase relationship between the clock signal ICKI and the clock signal ICKQ. That is, the divided clock signal WCKQ is phase-delayed compared to the divided clock signal WCKI. In this way, the monitor circuit 30 outputs the monitor signal mono of the low level in the case where the phase relationship between the frequency-divided clock signal WCKI and the frequency-divided clock signal WCKQ is the same as the phase relationship between the clock signal ICKI and the clock signal ICKQ.
The first selection circuit 40 inputs the divided clock signal WCKI generated at the first frequency dividing circuit 10 and the divided clock signal WCKIX as its inversion signal. The first selection circuit 40 outputs one of the divided clock signal WCKI and the divided clock signal WCKIX as the divided clock signal OCKI and outputs the other of the divided clock signal WCKI and the divided clock signal WCKIX as the divided clock signal OCKIX, according to the input selection signal.
In the example shown in fig. 1, the selection signal input to the first selection circuit 40 is low level, the first selection circuit 40 always outputs the divided clock signal WCKI as the divided clock signal OCKI, and outputs the divided clock signal WCKIX as the divided clock signal OCKIX. Here, in the example shown in fig. 1, since the selection of the output of the first selection circuit 40 is fixed, the first selection circuit 40 may not be provided in terms of function, but by providing the first selection circuit 40, the transmission characteristics such as delay and load can be made uniform by making the transmission paths of the respective divided clock signals have the same circuit configuration.
The second selection circuit 50 inputs the frequency-divided clock signal WCKQ generated at the second frequency dividing circuit 20 and the frequency-divided clock signal WCKQX as its inverted signal. The second selection circuit 50 outputs one of the divided clock signal WCKQ and the divided clock signal WCKQX as the divided clock signal OCKQ and the other of the divided clock signal WCKQ and the divided clock signal WCKQX as the divided clock signal OCKQX based on the monitor signal monosout input as the selection signal.
Fig. 3 is a diagram showing an example of the configuration of the second selection circuit 50. The second selection circuit 50 has switches 51, 52, 53, 54 and an inverter 55. A switch 51 is disposed between a signal line of the frequency-divided clock signal WCKQ and a signal line of the frequency-divided clock signal OCKQ, and a switch 52 is disposed between a signal line of the frequency-divided clock signal WCKQX and a signal line of the frequency-divided clock signal OCKQX. Further, a switch 53 is disposed between the signal line of the frequency-divided clock signal WCKQ and the signal line of the frequency-divided clock signal OCKQX, and a switch 54 is disposed between the signal line of the frequency-divided clock signal WCKQX and the signal line of the frequency-divided clock signal OCKQ.
The switches 51 and 52 are controlled by a monitor signal monosout supplied via an inverter 55, and the switches 53 and 54 are controlled by the monitor signal monosout. Specifically, the switches 51 and 52 are turned on (closed) when the monitor signal monosout is at a low level, and turned off (open) when the monitor signal monosout is at a high level. On the other hand, the switches 53 and 54 are turned on (closed) when the monitor signal monosout is at a high level, and turned off (open) when the monitor signal monosout is at a low level.
Therefore, the second selection circuit 50 outputs the divided clock signal WCKQ as the divided clock signal OCKQ and outputs the divided clock signal WCKQX as the divided clock signal OCKQX when the monitor signal monosout input as the selection signal is at the low level. In addition, the second selection circuit 50 outputs the divided clock signal WCKQX as the divided clock signal OCKQ and outputs the divided clock signal WCKQ as the divided clock signal OCKQX when the monitor signal monosout is at the high level.
The frequency dividing circuit in the present embodiment shown in fig. 1 outputs the frequency-divided clock signal WCKQ as the frequency-divided clock signal OCKQ in the case where the monitor signal monosout is low level, that is, the phase relationship between the frequency-divided clock signal WCKI generated by the first frequency dividing circuit 10 and the frequency-divided clock signal WCKQ generated by the second frequency dividing circuit 20 is the same as the phase relationship between the clock signal ICKI and the clock signal ICKQ. On the other hand, in the case where the monitor signal monosout is at a high level, that is, the phase relationship between the divided clock signal WCKI generated by the first frequency dividing circuit 10 and the divided clock signal WCKQ generated by the second frequency dividing circuit 20 is opposite to the phase relationship between the clock signal ICKI and the clock signal ICKQ, the divided clock signal WCKQX which is an inverted signal of the divided clock signal WCKQ is output as the divided clock signal OCKQ.
Thus, for example, as shown in fig. 4, the divided clock signal WCKQ is output as the divided clock signal OCKQ on the assumption that the phase relationship between the divided clock signal WCKI generated by the first dividing circuit 10 and the divided clock signal WCKQ generated by the second dividing circuit 20 is the same as the phase relationship between the clock signal ICKI and the clock signal ICKQ. That is, the frequency-divided clock signal WCKQ is output as the frequency-divided clock signal OCKQ so that the phase relationship with respect to the frequency-divided clock signal OCKI is the same as the phase relationship between the clock signal ICKI and the clock signal ICKQ.
At this time, when a part of the clock signal suddenly inverts due to the influence of noise or the like, and the phase relationship between the divided clock signal WCKI and the divided clock signal WCKQ is opposite to the phase relationship between the clock signal ICKI and the clock signal ICKQ, the monitor signal monosout changes to a high level, and the divided clock signal WCKQX which is an inverted signal of the divided clock signal WCKQ is output as the divided clock signal OCKQ. That is, the frequency-divided clock signal WCKQX, which is an inverted signal of the frequency-divided clock signal WCKQ, is output as the frequency-divided clock signal OCKQ so that the phase relationship with respect to the frequency-divided clock signal OCKI is the same as the phase relationship between the clock signal ICKI and the clock signal ICKQ.
Therefore, according to the frequency dividing circuit of the present embodiment shown in fig. 1, by selectively outputting one of the non-inverted and inverted frequency-divided clock signals generated by the second frequency dividing circuit 20 based on the phase relationship between the frequency-divided clock signal generated by the first frequency dividing circuit 10 and the frequency-divided clock signal generated by the second frequency dividing circuit 20, it is possible to output the frequency-divided clock signal OCKI and the frequency-divided clock signal OCKQ having the same phase relationship as the phase relationship between the input clock signal ICKI and the input clock signal ICKQ. For example, even when the phase relationship between the divided clock signal octi and the divided clock signal OCKQ is changed to a state different from the desired phase relationship due to instability of the clock signal, the desired phase relationship can be automatically restored.
In the above description, an example of outputting the frequency-divided clock signal octi and the frequency-divided clock signal OCKQ having the same phase relationship as the phase relationship between the input clock signal ICKI and the input clock signal ICKQ has been described. However, the present embodiment is not limited to this, and the divided clock signal OCKI and the divided clock signal OCKQ having a phase relationship opposite to the phase relationship between the input clock signal ICKI and the input clock signal ICKQ can be output by appropriately changing the configuration of the second selection circuit 50 and the like.
One of the circuits to which the frequency divider circuit in this embodiment is applied is a demultiplexer (demultiplexer) circuit. The splitter circuit is a circuit that converts a serial data signal into a parallel data signal, and divides a clock signal for serial-parallel conversion. In addition, in order to increase the transmission speed and to perform boundary detection for regenerative clock control, not only a single clock signal but also a plurality of clock signals having a certain phase difference are used.
Fig. 5 is a diagram showing an example of the configuration of the splitter circuit in the present embodiment. In this example, in the circuit in the preceding stage of the splitter circuit, the data signal IDT0 is obtained from the serial data signal using the clock signal IDTCLK, and the data signal IDT1 is obtained using the inverted signal (clock signal having a phase difference of 180 degrees) of the clock signal IDTCLK. The boundary signal IBD0 is obtained from the serial data signal using the clock signal IBDCLK, and the boundary signal IBD1 is obtained using the inverted signal (clock signal having a phase difference of 180 degrees) of the clock signal IBDCLK. Here, the clock signal IBDCLK has a phase difference of 90 degrees with respect to the clock signal IDTCLK, and is phase-delayed compared to the clock signal IDTCLK.
The frequency dividing circuit 101 inputs the clock signal IDTCLK and generates a frequency-divided clock signal having a frequency 1/2 of the clock signal IDTCLK. The frequency dividing circuit 101 has a configuration corresponding to the first frequency dividing circuit 10 and the first selection circuit 40 in the frequency dividing circuit shown in fig. 1. The frequency dividing circuit 102 generates a frequency-divided clock signal having a frequency of 1/2 of the frequency-divided clock signal generated by the frequency dividing circuit 101, and the frequency dividing circuit 103 generates a frequency-divided clock signal having a frequency of 1/2 of the frequency-divided clock signal generated by the frequency dividing circuit 102. The output of the frequency dividing circuit 103 is a frequency-divided clock ODTCLK, and an output data signal ODT < 15: 0 > and output boundary signal OBD < 15: 0 > are output together.
The frequency divider circuit 104 receives the clock signal IBDCLK as an input, and generates a frequency-divided clock signal having a frequency 1/2 of the clock signal IBDCLK. The frequency dividing circuit 104 has a configuration corresponding to the second frequency dividing circuit 20, the monitoring circuit 30, and the second selection circuit 50 of the frequency dividing circuit shown in fig. 1. The frequency divider circuit 104 selects and outputs one of the frequency-divided clock signal having the frequency 1/2 of the clock signal IBDCLK and the inverted signal thereof so that the phase relationship with respect to the frequency-divided clock signal generated by the frequency divider circuit 101 is the same as the phase relationship between the clock signal IDTCLK and the clock signal IBDCLK.
The splitter 105 converts a two-bit wide data signal formed of the data signal IDT0 and the data signal IDT1 into a four-bit wide data signal using the frequency-divided clock signal generated by the frequency dividing circuit 101. Splitter 106 converts the four-bit wide data signal output from splitter 105 into an eight-bit wide data signal using the frequency-divided clock signal generated by frequency divider circuit 102.
The splitter 107 converts the data signal of eight bits width output from the splitter 106 into a data signal of sixteen bits width using the frequency-divided clock signal generated by the frequency dividing circuit 103. The buffer 108 outputs the sixteen-bit wide data signal output from the demultiplexer 107 as a parallel output data signal ODT < 15: 0 >.
The splitter 109 converts a two-bit-wide boundary signal composed of the boundary signal IBD0 and the boundary signal IBD1 into a four-bit-wide boundary signal using the frequency-divided clock signal generated by the frequency divider circuit 104. In this way, the demultiplexer 109 can secure a timing margin by performing data conversion using the divided clock signal obtained by dividing the clock signal IBDCLK. Splitter 110 converts the boundary signal of four-bit width output from splitter 109 into a boundary signal of eight-bit width using the frequency-divided clock signal generated by frequency divider circuit 102.
The splitter 111 converts the boundary signal of eight bits width output from the splitter 110 into a boundary signal of sixteen bits width using the frequency-divided clock signal generated by the frequency dividing circuit 103. The buffer 112 outputs the boundary signal of sixteen bits width output from the demultiplexer 111 as a parallel output boundary signal OBD < 15: 0 >.
By using the frequency dividing circuit in the present embodiment as described above, when the data conversion is performed by the splitter 109 using the frequency-divided clock signal obtained by dividing the clock signal IBDCLK having a certain phase difference with respect to the clock signal IDTCLK, the data conversion can be performed using the frequency-divided clock signal having an appropriate phase relationship.
Fig. 6 is a diagram showing an example of the configuration of the semiconductor integrated circuit in this embodiment. The semiconductor integrated circuit 201 in this embodiment includes a receiving circuit 202 having a function of a deserializer circuit which converts an input serial signal into a parallel signal, and an internal circuit 211 such as a logic circuit which receives the parallel signal (data) from the receiving circuit 202 and performs a processing operation.
The reception circuit 202 includes a front end 203, a clock data recovery circuit 207, and a clock generation unit 208. The front end 203 includes a differential buffer 204, a comparator (comparator) 205, and a splitter circuit 206. The differential buffer 204 receives differential input serial signals RXIN, RXINX transmitted via a transmission line or the like. The comparator 205 determines the symbol (data) of the input serial signal.
The splitter circuit 206 is, for example, a splitter circuit shown in fig. 5, and performs serial-parallel conversion on the output of the phase detector 205 to output a parallel data signal DT, a boundary signal BD, and a reception data clock signal. The parallel data signal DT and the reception data clock signal output from the demultiplexer circuit 206 are output to the internal circuit 211 as a reception data signal RXOUT and a reception clock signal RXCLK.
The clock data recovery circuit 207 appropriately controls the phase of the internal clock signal output by the clock generation section 208 based on the received signal. The clock data recovery circuit 207 determines whether the phase of the internal clock signal output from the clock generation unit 208 is advanced or delayed with respect to the input serial signal based on the data signal DT and the boundary signal BD output from the splitter circuit 206. The clock data recovery circuit 207 generates and outputs a phase adjustment code for advancing or delaying the phase of the internal clock signal, based on the determination result.
The clock generation unit 208 includes a clock generator 209 and a phase interpolation circuit 210. The clock generator 209 generates a reference clock signal and supplies it to the phase interpolation circuit 210. The phase interpolation circuit 210 controls the phase of the reference clock signal supplied from the clock generator 209 in accordance with the phase adjustment code from the clock data recovery circuit 207, and outputs the reference clock signal as an internal clock signal to the comparator 205 and the splitter circuit 206.
The comparator 205 performs sampling of the input serial signal at an appropriate timing using the internal clock signal output from the clock generator 208, and the demultiplexer circuit 206 performs serial-parallel conversion. The reception data signal RXOUT output from the reception circuit 202 is taken into the internal circuit 211 by the flip-flop 212 which operates in accordance with the reception clock signal RXCLK, and is processed.
The above embodiments are merely specific examples for carrying out the present invention, and are not to be construed as limiting the scope of the technology of the present invention. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
As described above, according to the present invention, one of the second frequency-divided clock signal and the inverted signal of the second frequency-divided clock signal is selected and output based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal. Thus, the second frequency-divided clock signal and the inverted signal of the second frequency-divided clock signal can be appropriately selected and output so as to maintain a desired phase relationship with respect to the first frequency-divided clock signal.
Claims (11)
1. A frequency-division circuit, comprising:
a first frequency-dividing circuit section that divides a first clock signal to generate a first frequency-divided clock signal;
a second frequency-dividing circuit section that generates a second frequency-divided clock signal by dividing a second clock signal having the same frequency as the first clock signal and having a first phase difference;
a detection circuit that detects a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and
a first selection circuit that selects and outputs one of the second frequency-divided clock signal generated by the second frequency-dividing circuit unit and an inverted signal of the second frequency-divided clock signal based on the phase relationship detected by the detection circuit,
the detection circuit detects whether a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal is the same as a phase relationship between the first clock signal and the second clock signal.
2. The frequency dividing circuit of claim 1,
the first selection circuit selects and outputs the second divided clock signal when a phase relationship between the first divided clock signal and the second divided clock signal is the same as a phase relationship between the first clock signal and the second clock signal, and selects and outputs an inverted signal of the second divided clock signal when a phase relationship between the first divided clock signal and the second divided clock signal is opposite to a phase relationship between the first clock signal and the second clock signal.
3. The frequency dividing circuit of claim 1,
the detection circuit includes a first latch circuit to which the first divided clock signal is input at a data input, and a second latch circuit to which an output signal of a data output from the first latch circuit is input at a data input, drives the first latch circuit and the second latch circuit based on an output signal of the second divided circuit section, and outputs an output signal of a data output from the second latch circuit as a signal indicating a phase relationship between the first divided clock signal and the second divided clock signal,
the first selection circuit includes a first switch disposed between a signal line of the second divided clock signal and a signal line of the frequency divider circuit that outputs the divided clock signal, and a second switch disposed between a signal line of an inverted signal of the second divided clock signal and the signal line that outputs the divided clock signal, and the first switch and the second switch are exclusively turned on in response to a signal indicating a phase relationship between the first divided clock signal and the second divided clock signal output from the detection circuit.
4. A splitter circuit, comprising:
a splitter unit having a first splitter for converting a data signal into a parallel signal using a first conversion clock signal, and a second splitter for converting a boundary signal having a first phase difference from the data signal into a parallel signal using a second conversion clock signal having a different phase from the first conversion clock signal; and
a frequency dividing circuit that divides a first clock signal to generate the first converted clock signal, and divides a second clock signal having the same frequency as the first clock signal and the first phase difference to generate the second converted clock signal,
the frequency dividing circuit includes:
a first frequency-dividing circuit section for generating a first frequency-divided clock signal by dividing the frequency of the first clock signal;
a second frequency-dividing circuit section that divides the frequency of the second clock signal to generate a second frequency-divided clock signal;
a detection circuit that detects a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and
a first selection circuit that selects and outputs one of the second frequency-divided clock signal generated by the second frequency-dividing circuit unit and an inverted signal of the second frequency-divided clock signal based on the phase relationship detected by the detection circuit,
the first divided clock signal is output as the first converted clock signal, and one of the second divided clock signal output from the first selection circuit and an inverted signal of the second divided clock signal is output as the second converted clock signal.
5. The splitter circuit of claim 4,
the detection circuit detects whether a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal is the same as a phase relationship between the first clock signal and the second clock signal.
6. The splitter circuit of claim 5,
the first selection circuit selects and outputs the second divided clock signal when a phase relationship between the first divided clock signal and the second divided clock signal is the same as a phase relationship between the first clock signal and the second clock signal, and selects and outputs an inverted signal of the second divided clock signal when a phase relationship between the first divided clock signal and the second divided clock signal is opposite to a phase relationship between the first clock signal and the second clock signal.
7. A splitter circuit, comprising:
a first splitter that converts a first input signal having a first bit width, which is an input data signal representing data information of an input serial signal obtained by sampling the input serial signal with a first clock signal, into a first intermediate signal having a second bit width larger than the first bit width, based on a first converted clock signal generated by dividing the frequency of the first clock signal;
a second splitter that converts a second input signal, which has the first bit width and the first phase difference with respect to the first input signal and is obtained by sampling the input serial signal with the second clock signal and is an input boundary signal indicating boundary information of the input serial signal, into a second intermediate signal having the second bit width, based on a second conversion clock signal generated by dividing a second clock signal, which has the same frequency as the first clock signal and has the first phase difference;
a first frequency divider circuit that divides the frequency of the first converted clock signal to generate a third converted clock signal having a frequency lower than the frequency of the first converted clock signal;
a third splitter that converts the first intermediate signal into a first output signal having a third bit width larger than the second bit width based on the third conversion clock signal; and
and a fourth divider that converts the second intermediate signal into a second output signal having the third bit width based on the third conversion clock signal.
8. The splitter circuit of claim 7,
the first phase difference is 90 degrees.
9. Splitter circuit according to claim 7 or 8, characterized by:
a second frequency divider circuit that divides the frequency of the first clock signal to generate the first converted clock signal; and
a third frequency dividing circuit for generating the second conversion clock signal by dividing the frequency of the second clock signal,
the division ratios of the second and third frequency-dividing circuits are equal to the ratio of the second bit width to the first bit width.
10. The splitter circuit of claim 9,
the circuit further includes a conversion circuit for converting a serial signal into the first input signal and the second input signal based on the first clock signal and the second clock signal.
11. A semiconductor integrated circuit comprising:
a comparator for sampling an input serial signal using a first clock signal and a second clock signal having the same frequency as the first clock signal and having a first phase difference;
a splitter circuit for converting an output signal of the comparator into a parallel signal; and
a clock data recovery circuit which controls phases of the first clock signal and the second clock signal based on a received signal,
the splitter circuit includes:
a splitter unit having a first splitter for converting a data signal into a parallel signal using a first conversion clock signal, and a second splitter for converting a boundary signal having the first phase difference into a parallel signal using a second conversion clock signal having a different phase from the first conversion clock signal; and
a frequency divider circuit that divides the first clock signal to generate the first converted clock signal and divides the second clock signal to generate the second converted clock signal,
the frequency dividing circuit includes:
a first frequency-dividing circuit section for generating a first frequency-divided clock signal by dividing the frequency of the first clock signal;
a second frequency-dividing circuit section that divides the frequency of the second clock signal to generate a second frequency-divided clock signal;
a detection circuit that detects a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and
a first selection circuit that selects and outputs one of the second frequency-divided clock signal generated by the second frequency-dividing circuit unit and an inverted signal of the second frequency-divided clock signal based on the phase relationship detected by the detection circuit,
the first divided clock signal is output as the first converted clock signal, and one of the second divided clock signal output from the first selection circuit and an inverted signal of the second divided clock signal is output as the second converted clock signal.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2016/057719 WO2017154191A1 (en) | 2016-03-11 | 2016-03-11 | Divider circuit, demultiplexer circuit, and semiconductor integrated circuit |
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| CN108781080A CN108781080A (en) | 2018-11-09 |
| CN108781080B true CN108781080B (en) | 2022-04-08 |
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| CN201680083326.2A Active CN108781080B (en) | 2016-03-11 | 2016-03-11 | Frequency divider circuit, splitter circuit, and semiconductor integrated circuit |
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| Country | Link |
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| US (2) | US10868552B2 (en) |
| EP (2) | EP3429082B1 (en) |
| JP (1) | JP6823268B2 (en) |
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| CN113765515B (en) * | 2020-06-03 | 2024-04-19 | 瑞昱半导体股份有限公司 | Open loop fractional divider |
| JPWO2022168210A1 (en) * | 2021-02-03 | 2022-08-11 |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003266215A (en) * | 2002-03-18 | 2003-09-24 | Kyocera Corp | Inside diameter machining tool |
| JP2007243617A (en) * | 2006-03-08 | 2007-09-20 | Fujitsu Ltd | Differential output frequency divider circuit |
| CN101383675A (en) * | 2007-09-07 | 2009-03-11 | 冲电气工业株式会社 | Parallel decoder |
| CN102160292A (en) * | 2008-09-19 | 2011-08-17 | 阿尔特拉公司 | Techniques for generating fractional clock signals |
| CN102318192A (en) * | 2009-02-26 | 2012-01-11 | 松下电器产业株式会社 | Phase adjustment circuit |
| JP2012060319A (en) * | 2010-09-07 | 2012-03-22 | Fujitsu Ltd | Multi-phase clock generation circuit |
| CN102609386A (en) * | 2010-12-03 | 2012-07-25 | 罗姆股份有限公司 | Circuit and method for receiving serial data and serial data transmission system and method using the same |
| CN104079296A (en) * | 2013-03-29 | 2014-10-01 | 日本电波工业株式会社 | Oscillator |
| EP2843564A1 (en) * | 2013-08-27 | 2015-03-04 | Fujitsu Limited | Communication circuit and information processing device |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63306732A (en) * | 1987-06-09 | 1988-12-14 | Fujitsu Ltd | Clock pulse supply device |
| JPH02194721A (en) * | 1989-01-24 | 1990-08-01 | Hitachi Ltd | Semiconductor integrated circuit device |
| DE69022577T2 (en) * | 1989-04-28 | 1996-03-28 | Anritsu Corp | SIGNAL GENERATOR AND SIGNAL RECEIVER BASED ON A SYNCHRONOUS MULTIPLEX TRANSMISSION SYSTEM. |
| JP2986881B2 (en) * | 1990-09-19 | 1999-12-06 | 株式会社日立製作所 | Frequency divider for phase difference pulse signal |
| KR100608355B1 (en) * | 2004-03-25 | 2006-08-08 | 주식회사 하이닉스반도체 | A device for controlling the enabling time of the internal control signal according to the operating frequency of a memory device and the method thereof |
| JP2008011132A (en) * | 2006-06-29 | 2008-01-17 | Nec Electronics Corp | 90-degree phase shifter |
| JP2008166910A (en) * | 2006-12-27 | 2008-07-17 | Matsushita Electric Ind Co Ltd | Clock signal generator and analog/digital converter |
| KR100894811B1 (en) * | 2007-01-11 | 2009-04-24 | 삼성전자주식회사 | Deserializer of serdes and data deserializing method thereof |
| US8989214B2 (en) * | 2007-12-17 | 2015-03-24 | Altera Corporation | High-speed serial data signal receiver circuitry |
| US7928773B2 (en) * | 2008-07-09 | 2011-04-19 | Integrated Device Technology, Inc | Multiple frequency synchronized phase clock generator |
| US8760325B2 (en) * | 2012-03-23 | 2014-06-24 | Analog Devices, Inc. | Scheme for balancing skew between lanes of high-speed serial digital interface |
| JP6631117B2 (en) | 2015-09-17 | 2020-01-15 | 富士通株式会社 | Semiconductor device, demultiplexer, semiconductor circuit, data processing method and inspection method |
| JP6985579B2 (en) * | 2016-07-27 | 2021-12-22 | 株式会社ソシオネクスト | Division correction circuit, receiving circuit and integrated circuit |
-
2016
- 2016-03-11 CN CN201680083326.2A patent/CN108781080B/en active Active
- 2016-03-11 EP EP16893518.7A patent/EP3429082B1/en active Active
- 2016-03-11 WO PCT/JP2016/057719 patent/WO2017154191A1/en active Application Filing
- 2016-03-11 JP JP2018503958A patent/JP6823268B2/en active Active
- 2016-03-11 EP EP19214280.0A patent/EP3641138A1/en active Pending
-
2018
- 2018-09-10 US US16/126,908 patent/US10868552B2/en active Active
-
2020
- 2020-11-13 US US17/098,071 patent/US11251800B2/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003266215A (en) * | 2002-03-18 | 2003-09-24 | Kyocera Corp | Inside diameter machining tool |
| JP2007243617A (en) * | 2006-03-08 | 2007-09-20 | Fujitsu Ltd | Differential output frequency divider circuit |
| CN101383675A (en) * | 2007-09-07 | 2009-03-11 | 冲电气工业株式会社 | Parallel decoder |
| CN102160292A (en) * | 2008-09-19 | 2011-08-17 | 阿尔特拉公司 | Techniques for generating fractional clock signals |
| CN102318192A (en) * | 2009-02-26 | 2012-01-11 | 松下电器产业株式会社 | Phase adjustment circuit |
| JP2012060319A (en) * | 2010-09-07 | 2012-03-22 | Fujitsu Ltd | Multi-phase clock generation circuit |
| CN102609386A (en) * | 2010-12-03 | 2012-07-25 | 罗姆股份有限公司 | Circuit and method for receiving serial data and serial data transmission system and method using the same |
| CN104079296A (en) * | 2013-03-29 | 2014-10-01 | 日本电波工业株式会社 | Oscillator |
| EP2843564A1 (en) * | 2013-08-27 | 2015-03-04 | Fujitsu Limited | Communication circuit and information processing device |
Non-Patent Citations (1)
| Title |
|---|
| 一种用于高速锁相环的整数分频器设计;庞遵林等;《电子科技》;20150615;第104-107页 * |
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| Publication number | Publication date |
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| US20190007056A1 (en) | 2019-01-03 |
| WO2017154191A1 (en) | 2017-09-14 |
| EP3429082A1 (en) | 2019-01-16 |
| CN108781080A (en) | 2018-11-09 |
| JP6823268B2 (en) | 2021-02-03 |
| JPWO2017154191A1 (en) | 2019-01-17 |
| US20210067165A1 (en) | 2021-03-04 |
| US10868552B2 (en) | 2020-12-15 |
| US11251800B2 (en) | 2022-02-15 |
| EP3429082B1 (en) | 2020-12-23 |
| EP3641138A1 (en) | 2020-04-22 |
| EP3429082A4 (en) | 2019-06-12 |
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