KR100723509B1 - Digital-analog converting driver joining R-string DAC and capacitor DAC and method thereof - Google Patents

Abstract

Disclosed are a digital-analog converting driver and a digital-analog converting method that combine a resistor string digital-analog converter and a capacitor digital-analog converter. The digital-analog converting driver according to the embodiment of the present invention is a digital-analog converting driver that receives digital data of M + N bits and converts them into analog voltages and includes a first converting unit, a second converting unit, and an analog voltage output unit. . The first converter converts consecutive M bit values of the digital data into a first voltage. The second converter converts consecutive N bit values of the digital data into a second voltage. The analog voltage output unit adds the first voltage and the second voltage to output the analog voltage. The output range of the first voltage is different from the output range of the second voltage. According to the digital-analog converting driver and the digital-analog converting method according to an embodiment of the present invention, the digital-analog converting is performed by a digital-analog converting driver having a new structure combining a stable resistance string converter and an area-efficient capacitor converter. The advantages of converting drivers and digital-to-analog converting methods are to maximize the stability and area efficiency.

Resistor String Converters, Capacitor Converters, Buffers, Converting

Description

Digital-to-analog converting driver joining R-string DAC and capacitor DAC and method

BRIEF DESCRIPTION OF THE DRAWINGS In order to understand the drawings referred to in the detailed description of the invention, a brief description of each drawing is provided.

1 illustrates a resistance string digital-analog converter according to the prior art.

2 is a circuit diagram illustrating a capacitor digital-analog converter according to the prior art.

3 is a diagram schematically illustrating a digital-analog converting driver according to an embodiment of the present invention.

4 is a diagram conceptually illustrating the digital data of FIG. 3.

FIG. 5 is a circuit diagram illustrating in detail the first converter and the analog voltage output unit of FIG. 3.

6 is a circuit diagram illustrating in detail the input means of FIG. 5.

FIG. 7 is a diagram illustrating a second converter of FIG. 3.

8 is a flowchart illustrating a digital-analog converting method according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-analog converting driver, and more particularly to a digital-analog converting resistor-string digital-analog converter and a capacitor digital-analog converter. It relates to an analog converting driver.

In recent years, the size of a display panel such as a television is increasing day by day. As the size of the display panel increases, the number of digital-analog converters required for driving the panel in the source driver IC of the display device increases.

Therefore, the increase in the area of the digital-analog converter is problematic in relation to the area of the source driver of the display device. This phenomenon is more problematic in the trend of switching from a system having 8 bits of digital data to a system of 10 bits or more to realize high quality.

1 is a schematic representation of a resistive string digital-to-analog converter according to the prior art.

Referring to FIG. 1, a resistor string digital-to-analog converter (hereinafter referred to as a "resistance string converter") 10 according to the prior art includes a resistor string 12 and a decoder 14.

The resistor string 12 includes 2 ⁿ -1 resistors R1, R2, ... R2 ⁿ -1 arranged in a line when the number of bits of the digital data DTA input to the resistor string converter 10 is n. And a maximum level voltage (Vmax) and a minimum level voltage (Vmin) are applied at both ends.

At this time, the voltages Vi1, Vi2, ... Vik between the respective resistors R1, R2, ... R2 ⁿ -1 are the voltages between the maximum level voltage Vmax and the minimum level before Vmin. Have a level.

The decoder 14 receives the digital data DTA and selects and outputs a voltage corresponding to the received digital data DTA among the voltages Vi1, Vi2,... Vik of the resistance string 12.

The voltages Vo1, Vo2,... Vok selected by the decoder 14 are supplied to an external device as analog voltages through the respective buffers 20 of the buffer unit 20.

The resistor string converter according to the prior art has an advantage of performing a stable digital-analog converting operation. However, the resistance string converter has a problem that the area is doubled every time the number of bits of digital data to be converted increases by one.

For example, if the size of the decoder of the 6-bit system is 100, the decoder of the 8-bit system is 400 (100 * 2 ² ). Similarly, a decoder in a 10-bit system would be 1600 (100 * 2 ⁴ ) and a decoder in a 12-bit system would be 3200 (100 * 2 ⁶ ).

As a result, resistor string converters are not well suited for the trend towards high integration and are difficult to use in systems with more than 10 bits.

In order to overcome this disadvantage, a capacitor digital-to-analog converter (hereinafter referred to as a "capacitor converter") is proposed.

2 is a circuit diagram showing a capacitor converter according to the prior art.

According to FIG. 2, the capacitor converter 30 according to the related art includes an input unit 32 and a conversion unit 34.

The input unit 32 includes switches Sd1 and Sd2 to select and transfer the reference voltages Va and Vb according to the logic level of the bit of the digital data DTA to be input to the converter 34. .

The conversion unit 34 includes a first capacitor C1, a second capacitor C2, and switches SC1, SC2, and SC3 to correspond to the digital data DTA input through repetition of charging and dispensing. Output the voltage Vo.

The operation of the capacitor converter 30 is as follows.

Initially, the initialization switch Sc3 discharges the first capacitor C1 and the second capacitor C2 prior to the converting operation. The input unit 32 outputs one of the reference voltages Va and Vb to the converter 34 according to the logic level of the first bit of the input digital data DTA.

The first capacitor C1 is charged with the reference voltages Va and Vb transmitted by the input unit 32 while the charging switch SC1 is closed.

Next, as the charge switch SC1 is opened and the distribution switch Sc2 is closed, the charge charged in the first capacitor C1 is distributed to the second capacitor C2. At this time, the first capacitor C1 and the second capacitor C2 have the same voltages Va / 2 and Vb / 2.

Next, in response to the logic level of the second bit of the digital data DTA, the reference voltages Va and Vb are added to the first capacitor C1, and again the first capacitor C1 and the second capacitor C2 are charged. Will be distributed.

In the case of n-bit digital data, if the above-described process is repeatedly performed n times, an analog voltage Vo corresponding to the input digital data DTA is generated.

The capacitor converter according to the prior art has only a predetermined number of switches and two capacitors, regardless of the number of bits of digital data to be converted, so that the area is significantly reduced compared to the resistor string converter.

When a 10-bit system is configured using a capacitor converter, the area can be realized in an area of about 6 bits of a resistance string converter.

However, since the capacitor converter structure generates the desired analog voltage through charge distribution starting from the least significant bit of the digital data to the most significant bit, as described above, the most significant bit decoding occupies most of the error.

In particular, when only the logic level of the most significant bit is different, such as "01111111" or "10000000" data, the probability of error increases.

Referring back to FIG. 2, suppose that the reference voltages Va and Vb of the capacitor converter 30 are "5V" and "0V", respectively, and the digital data DTA is input as "01111111" (from the least significant bit). .

Corresponding to the logic level "1" of the first bit of the digital data DTA (input from the least significant bit), the analog voltage Vo is 2.5V through the charging distribution of the first capacitor C1 and the second capacitor C2. Becomes

If 5V is input again corresponding to the logic level "1" of the second bit of "11111110", it is output as a 3.75V analog voltage through the voltage distribution of the first capacitor C1 of 5V and the second capacitor C2 of 2.5V. .

When this process is repeated, the logic level "1" of the n-th bit is output as a value close to the reference voltage (5V). That is, after the n−1 th converting operation, the second capacitor C2 is charged to a voltage close to 5V.

Next, when the logic level "0" of the n-th bit of the first capacitor C1 is charged to the reference voltage (0V) and distributed with the second capacitor C2, a large voltage difference between the two capacitors C1 and C2 is applied. This causes a phenomenon such as a switching error.

This error is particularly prone to error because it occurs during the conversion of the most significant bit to produce the final analog voltage corresponding to the digital data to be converted. As the number of bits of the digital data increases, the voltage difference between the two capacitors C1 and C2 increases, so that the probability of error increases.

That is, according to the capacitor converter according to the prior art, as the number of bits of the digital data increases, the error occurrence frequency increases, which causes a problem that cannot guarantee the stability of the multi-bit system.

The technical problem to be achieved by the present invention is to provide a digital-analog converting driver that can maximize the area efficiency while maintaining stability.

Another object of the present invention is to provide a digital-analog converting method capable of maximizing area efficiency while maintaining stability.

In order to solve the above technical problem, a digital-analog converting driver combining the resistance string converter and the capacitor converter of the present invention receives a digital data of M + N bits and converts it into an analog voltage. And a second converter and an analog voltage output.

The first converter converts consecutive M bit values of the digital data into a first voltage. The second converter converts consecutive N bit values of the digital data into a second voltage. The analog voltage output unit adds the first voltage and the second voltage to output the analog voltage.

The output range of the first voltage is different from the output range of the second voltage.

The M bit value is a lower M bit value of the digital data, and the N bit value is an upper N bit value of the digital data.

The output range of the first voltage is smaller than the output range of the second voltage. The first converter and the second converter are different types of digital-to-analog converters.

The first converter is a capacitor converter and the second converter is a resistance string converter. The capacitor converter has an input means and a conversion means.

The input means has switches to output an upper or lower reference voltage corresponding to the logic level of each bit of consecutive M bits of the digital data.

The converting means comprises a first capacitor, a second capacitor and switches to output the first voltage through repetition of charging and distributing the upper or lower reference voltage received from the input.

The resistance string converter has a resistance string and a decoder.

In the resistor string, a plurality of resistors are arranged in a line to form reference voltages. The decoder outputs a reference voltage corresponding to consecutive N bits of the digital data among the reference voltages as the second voltage.

The difference between the reference voltages of the capacitor converter is equal to the difference with the adjacent reference voltages of the resistance string converter. The first capacitor and the second capacitor have the same capacitance.

The resistor string has 2 ^N resistors.

The analog voltage output unit is a buffer. The buffer has an OP amplifier and a switch. The OP amplifier outputs the analog voltage through an output terminal connected to one end of the second capacitor and the second voltage as an input of an inverting terminal and a non-inverting terminal, respectively, and the other end of the second capacitor.

The switch is connected to the output of the OP amplifier and the inverting terminal.

When M + N is 10, M is 7 and N is 3. When M + N is 12, M is 8 and N is 4.

The digital-analog converting driver further includes a data distributor which divides the digital data into the M bits and the N bits and distributes the digital data to the first converter and the second converter, respectively.

According to another aspect of the present invention, there is provided a digital-analog converting method in a digital-analog converting driver combining a resistance string converter and a capacitor converter. Inputting data, separating the digital data into a predetermined number, performing digital-analog conversion on the bit values of the separated digital data, respectively, and generating a voltage corresponding to each bit value; Adding the resulting voltages and outputting the added voltages as analog voltages.

The generating of the voltage corresponding to each bit value is performed by converting each bit value in a different converting manner. Separating the digital data into a predetermined number divides the M + N bits of digital data into upper M bits and lower N bits.

The converting method is a converting method using a capacitor converter and a converting method using a resistance string for the upper M bit value and the upper lower N bit value, respectively.

Generating a voltage corresponding to each bit value differs in the output range of voltages corresponding to each bit value. Separating the digital data into a predetermined number divides the M + N bits of digital data into upper M bits and lower N bits.

The outputting of the voltage corresponding to each bit value may include an output range of the voltage for the upper M bit value smaller than an output range of the voltage for the lower N bit value.

The step of generating a voltage corresponding to each bit value includes converting the upper M bit value using a capacitor converter and converting the upper lower N bit value using a resistance string converter.

M is 7 and N is 3. M is 8 and N is 4.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a diagram schematically illustrating a digital-analog converting driver according to an embodiment of the present invention.

Referring to FIG. 3, the digital-analog converting driver 100, which receives digital data of M + N bits and converts the digital data into an analog voltage according to an embodiment of the present invention, includes a first converter ( 120, a second converter 140, and an analog voltage output unit 160.

The first converter 120 converts consecutive M bit values of the digital data DTA into the first voltage V1. The second converter 140 converts the consecutive N bit values of the digital data DTA into the second voltage V2.

Preferably, the digital-analog converting driver 100 divides the digital data DTA into the M bits and the N bits and distributes the digital data DTA to the first converter 120 and the second converter 140, respectively. ) Is further provided.

4 is a diagram conceptually illustrating the digital data of FIG. 3.

Referring to FIG. 4, the digital data DTA is divided into two parts. The consecutive M bit value is the lower M bit value DTA [M-1: 0] of the digital data DTA, and the consecutive N bit value is the upper N bit value DTA [M of the digital data DTA. + N-1: M-1]).

That is, the first converter 120 of FIG. 3 converts the lower M bit values DTA [M-1: 0] of the digital data DTA and the second converter 140 of FIG. 3. Performs conversion for the upper N bit values DTA [M + N-1: M-1] of the digital data DTA.

Referring back to FIG. 3, the first converter 120 and the second converter 140 may be different types of digital-analog converters. The analog voltage output unit 160 adds the first voltage V1 and the second voltage V2 and outputs the analog voltage VANL.

FIG. 5 is a circuit diagram illustrating in detail the first converter and the analog voltage output unit of FIG. 3.

4 and 5, the first converter 120 is a capacitor converter. The capacitor converter 120 has an input means 122 and a conversion means 124.

The input means 122 comprises switches S1221 and S1222 to provide the logic level ("0" or "1") of each bit of the lower M bit value DTA [M-1: 0] of the digital data DTA. And outputs an upper reference voltage Vup or a lower reference voltage Vdown corresponding to.

6 is a circuit diagram illustrating in detail the input means of FIG. 5.

Referring to FIG. 6, reference voltages Vup and Vdown are applied to both ends of the input unit 122. The two switches S1221 and S1222 of the input means 122 are NMOS transistor S1221 and PMOS transistor S1222, respectively.

When the input bit value is logic "1", the NMOS transistor S1221 is turned on. Therefore, the upper reference voltage Vup is transmitted to the conversion means 124 of FIG. 5. However, when the input bit value is logic "0", the PMOS transistor S1222 is turned on and the lower reference voltage Vdown is transmitted.

Referring again to FIG. 5, the conversion means 124 includes a first capacitor C1, a second capacitor C2, and a switch S1241. The conversion means 124 outputs the first voltage V1 through repetition of charging and distributing the upper or lower reference voltage Vup or Vdown transmitted from the input means 122.

Dispensing means 124 specifically operates as follows. When the upper or lower reference voltage Vup or Vdown is transmitted from the input means 122, the first capacitor C1 is charged to the upper or lower reference voltage Vup or Vdown.

That is, when the input bit value is logic "0", the first capacitor C1 is charged to the lower reference voltage Vdown. In contrast, when the input bit value is logic “1”, the first capacitor C1 is charged to the upper reference voltage Vup.

The second capacitor C2 is connected to the first capacitor C1 charged to the upper or lower reference voltage Vup or Vdown by a predetermined control signal. The control signal is generated by inputting the lower M bit value DTA [M-1: 0] of the digital data DTA to the input means 122.

At this time, distribution of charge occurs between the first capacitor C1 and the second capacitor C2. If the capacitances of the first capacitor C1 and the second capacitor C2 are the same, the first capacitor C1 and the second capacitor C2 are charged with the same amount of charge.

When the above process is repeatedly performed, the amount of charge charged in the second capacitor C2 is added or subtracted according to the logic level of each bit of the sequentially lower M bit values DTA [M-1: 0]. do. When M repetitions of execution are completed, the second capacitor C2 is finally charged to a voltage corresponding to the lower M bit value DTA [M-1: 0].

As a result, the first voltage V1 is output as a voltage according to the amount of charge charged in the second capacitor C2.

The capacitor converter 120 may further include a switch S1242 connected in parallel with the second capacitor C2 to discharge and initialize the first capacitor C1 and the second capacitor C2.

5, the analog voltage output unit 160 is a buffer. The buffer 160 includes an OP amplifier 162 and a switch S164. The OP amplifier 162 uses one end of the second capacitor C2 and the second voltage V2 as inputs of an inverting terminal and a non-inverting terminal, respectively, and outputs the analog voltage through an output terminal connected to the other end of the second capacitor. Output

The switch S164 connected to the output of the OP amplifier 162 and the inverting terminal is turned on to initialize the inverting terminal voltage of the OP amplifier 162 to a non-inverting terminal voltage, that is, the second voltage V2. Thereafter, when the switch S164 is turned off in response to the control signal, the first voltage V1 is applied to the inverting terminal initialized to the second voltage V2.

Therefore, the analog voltage output unit 160 outputs the analog voltage VANL to which the first voltage V1 and the second voltage V2 are added.

FIG. 7 is a diagram illustrating a second converter of FIG. 3.

Referring to FIG. 7, the second converter 140 is a resistance string converter. The resistor string converter 140 includes a resistor string 142 and a decoder 144.

As described above, the resistance string converter 140 converts the upper N bit values DTA [M + N-1: M-1] of the digital data DTA. The resistor string 142 has 2 ^N resistors, and the maximum voltage Vmax and the minimum voltage Vmin of the output range of the second voltage V2 are applied to both ends.

The resistor string 142 has 2 ^N resistors R1, R2,..., R2 ^N −1 arranged in a line to form the reference voltages Vr1, Vr2,..., And Vr2 ^N. The decoder 144 selects one reference voltage among the reference voltages Vr1, Vr2,..., Vr2 ^N.

In this case, since 2 ^N voltage levels are required to convert the upper N bits, the reference voltages of the resistor string converter 140 are obtained by dividing the difference (Vmax-Vmin) between the maximum voltage (Vmax) and the minimum voltage (Vmin) by ^2N . Is a multiple of.

That is, according to the resistance string converter 140, when the upper N bit values DTA [M + N-1: M-1] of the digital data DTA are input, the decoder 144 may input the upper N bit values DTA [. M + N-1: M-1]) is switched to a reference voltage corresponding to the second voltage V2.

5 and 7, the difference between the upper and lower reference voltages of the capacitor converter 120 (Vup-Vdown) is determined by the difference between adjacent reference voltages of the resistor string converter 142 (eg, Vr1 -Vr2). Same as).

Therefore, the output range of the first voltage V1 and the output range of the second voltage V2 are different. In particular, the output range of the first voltage V1 may be smaller than the output range of the second voltage V2. For example, the first voltage V1 may have a voltage level within the output range of 5 kW, while the second voltage V2 may have a voltage level within the output range of 5V.

Referring again to FIG. 3, in the digital-analog converting driver 100 according to the present invention, the M + N indicates the number of bits of the digital data DTA. In this case, the ratio of M and N may be set to an appropriate value according to the error rate required by the system or the area of the driver.

As a preferred example, when M + N, that is, the number of bits of the digital data DTA is 10, M is 7 and N is 3. When M + N is 12, M is 8 and N is 4.

Assume a capacitor converter error rate of 1 in a 10-bit or 12-bit system. The above examples show an error rate of about 10% (1/2 ^(10-M) , 1/2 ^(12-M) ) in converting 10-bit or 12-bit digital data by the digital-analog converting driver of the present invention. Are examples selected to lower.

Therefore, when M + N is 10, M may be less than 7, and when M + N is 12, M may be less than 8. However, when the M value becomes smaller than an appropriate number, the number of upper N bits to be processed in the resistance string converter increases relatively.

Therefore, in determining the M and N values, it should be considered that as the M value becomes smaller, the area of the digital-analog converting driver of the present invention increases.

With the same M and N values as the above examples, the present invention requires only about half the area compared to a resistive string converter in an 8-bit system. In addition, the stability string of the system is greatly improved by having the resistance string converter transmit the most significant bit causing the largest error in the capacitor converter.

8 is a flowchart illustrating a digital-analog converting method according to an embodiment of the present invention.

 Referring to FIG. 8, in the digital-analog converting method according to the embodiment of the present invention for achieving the another technical problem, in step 810 of inputting digital data of M + N bits into the digital-analog converting driver, the digital data Dividing a number into a predetermined number; performing digital-analog conversion on the separated bit values of the digital data, and outputting a voltage corresponding to each bit value by 830; adding voltages output as a result of the converting Step 840 and step 850 of outputting the added voltage as an analog voltage.

The digital-analog converting method according to an embodiment of the present invention has the same technical idea as the digital-analog converting driver described above and corresponds to the operation of the digital-analog converting driver. Therefore, those skilled in the art can easily understand the digital-analog converting method according to the present invention from the foregoing description, and a description thereof will be omitted.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, these terms are only used for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the digital-analog converting driver and the digital-analog converting method, which combine the resistor string converter and the capacitor converter according to the present invention, the digital structure of the novel structure combining the stable resistor string converter and the capacitor converter with excellent area efficiency By converting by the analog converting driver, there is an advantage of maximizing the stability and area efficiency of the digital-analog converting driver and the digital-analog converting method.

Claims (24)

In a digital-analog converting driver that receives digital data of M + N bits (M and N are natural numbers) and converts them into analog voltages A first converter converting consecutive M bit values of the digital data into a first voltage; A second converter converting consecutive N bit values of the digital data into a second voltage; And An analog voltage output unit configured to add the first voltage and the second voltage to output the analog voltage; And a resistor string converter and a capacitor converter, wherein the output range of the first voltage is different from the output range of the second voltage. The method of claim 1, And the M bit value is a lower M bit value of the digital data and the N bit value is an upper N bit value of the digital data. The method of claim 1, And the output range of the first voltage is smaller than the output range of the second voltage. The method of claim 1, wherein the first converter and the second converter, Digital-to-analog converting driver that combines a resistor string converter and a capacitor converter, characterized by different types of digital-to-analog converters. The method of claim 1, And the first converter is a capacitor converter and the second converter is a resistor string converter. The method of claim 5, wherein the capacitor converter, Input means having switches for outputting an upper or lower reference voltage corresponding to a logic level of each bit of consecutive M bits of said digital data; And A capacitor converter having a first capacitor, a second capacitor, and switches, and converting means for outputting said first voltage through repetition of charging and distributing said upper or lower reference voltage delivered from said input means, The resistance string converter, A resistor string in which a plurality of resistors are arranged in a line to form reference voltages; And And a resistor string converter for outputting, as the second voltage, a reference voltage corresponding to consecutive N bits of the digital data among the reference voltages. The digital-analog converting driver coupling the resistor string converter and the capacitor converter. . The method of claim 6, And a difference between said reference voltage of said capacitor converter is equal to a difference between said adjacent reference voltage of said resistor string converter. The method of claim 6, wherein the first capacitor and the second capacitor, A digital-analog converting driver combining resistor string converters and capacitor converters having the same capacitance. The method of claim 6, wherein the resistance string, A digital-analog converting driver combining a resistor string converter and a capacitor converter, characterized by having 2 ^N resistors. The method of claim 5, wherein the analog voltage output unit, A digital-analog converting driver combining a resistor string converter and a capacitor converter, characterized in that it is a buffer. The method of claim 10, wherein the buffer, An op amp configured to input one end of the second capacitor and the second voltage to an inverting terminal and a non-inverting terminal, respectively, and output the analog voltage through an output terminal connected to the other end of the second capacitor; And And a switch connected to the output of said op amp and said inverting terminal. The method of claim 1, And wherein M is 7 and N is 3 when M + N is 10. The digital-analog converting driver coupling a resistor string converter and a capacitor converter. The method of claim 1, And wherein M is 8 and N is 4 when M + N is 12. The digital-analog converting driver coupling a resistor string converter and a capacitor converter. The method of claim 1, wherein the digital-analog converting driver, And a digital divider for receiving the digital data and dividing the digital data into the M bits and the N bits and distributing the digital data to the first and second converters, respectively. Converting driver. In the digital-analog converting method, Inputting M + N bits of digital data into the digital-analog converting driver; Separating the digital data into M bit values and N bit values, respectively; Performing digital-analog converting on the M bit value and the N bit value to generate voltages corresponding to the respective bit values; Adding voltages resulting from the converting; And Outputting the added voltage as an analog voltage. The method of claim 15, wherein generating a voltage corresponding to each bit value comprises: A digital-to-analog converting method for converting each bit value in a different converting method. The method of claim 16, Wherein the M bit value is a lower M bit value of the digital data and the N bit value is an upper N bit value of the digital data. The method of claim 17, wherein the converting method, And a converting method using a capacitor converter and a converting method using a resistance string for the upper M bit value and the upper lower N bit value, respectively. The method of claim 15, wherein generating a voltage corresponding to each bit value comprises: And an output range of voltages corresponding to the respective bit values is different. The method of claim 19, wherein the separating of the digital data into a predetermined number comprises: And separating the M + N bits of digital data into upper M bits and lower N bits. The method of claim 20, wherein generating a voltage corresponding to each bit value comprises: And the output range of the voltage for the upper M bit value is smaller than the output range of the voltage for the lower N bit value. The method of claim 20, wherein generating a voltage corresponding to each bit value comprises: Converting the upper M bit value using a capacitor converter and converting the upper M bit value using a resistance string converter. The method of claim 15, And wherein M is 7 and N is 3. 3. The method of claim 15, And wherein M is 8 and N is 4. 3.

Images