JPH0824265B2 - D / A converter - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter used as a MOS integrated circuit.

2. Description of the Related Art In recent years, D / A converters are becoming digital processing of all electronic devices, and play an important role as a contact point between analog processing and digital processing.

The conventional MOS segment type D / A converter will be described below. FIG. 3 is a diagram of a conventional 6-bit D / A converter.

φ _C is a two-phase clock pulse, D _{0 to} D ₅ are 6-bit data, 3 is an X decoder, 4 is a Y decoder, 301, 302, 406, 40
7 is a NAND gate, 303, 305, 403, 405 are compound gates, 306, 30
7,401,402,422,424,426,428,430,432,434,436 are NOR gates, 304,308 to 315,348,332,334,336,338,340,342,344,3
46,404,408 to 414,423,425,427,429,431,433,435,437 are inverters (hereinafter referred to as INV), 333,335,337,339,341,3
43,345,347 are buffers, 349,350 are AND gates 316 to 331,4
15 to 421 are transfer gates, X _{0 to} X ₇ , ₀ to ₇ are positive phase and negative phase X decoder outputs, Y _{P0 to} Y _P7 , Y _{S0 to} Y, respectively.
_S7 is a Y decoder output.

(0,0) to (7,7) are constant current source basic circuits arranged in a matrix. 10 is a resistor, which is a constant current source basic circuit (0,
0) to (7,7). Further, the positive-phase X decoder outputs X _{0 to} X ₇ are connected to the constant-current source basic circuits of even columns such as (7,0), (7,2), (7,4), The X decoder outputs ₀ to ₇ are connected to the constant current source basic circuits of odd columns such as (7,1), (7,3), (7,5).

Next, FIG. 4 shows the circuit configuration of the constant current source basic circuit. 30 indicates a basic circuit block of constant current source, 31 indicates 2 inputs
An AND gate, 32 is a 2-input NOR gate, 33 is a transfer gate, and 35 to 38 and 391 to 396 are n-channel MOS transistors. X _j is the output of the j-th X decoder, (Y _Pi , Y _Si ) is the output of the i-th Y decoder, _C is the two-phase clock pulse, I _OUT is the output current, and CV is the bias that controls the output current I _OUT. The voltage, I _BIAS, is the bias current that determines the current value of the constant current source.

The operation of the D / A conversion device configured as described above will be described below. First, of the bit data D _{0 to} D ₅ , the data D _{0 to} D ₃ are input to the X decoder. Among them, D ₃ is used for switching between a case where a high level (hereinafter referred to as “H” level) is generated and a low level (hereinafter referred to as “L” level) is generated in the X decoder output X _n ,
Is latched by the clock pulse phi _C X decoder output (X _n,
n ) (n = 0 to 7) is generated. This relationship is shown in Table 1. In this configuration, the signals X _n and _n having opposite phases are used as the outputs of the X decoder to prevent noise generated when a plurality of bits of the digital signal change at the same time. That is, as shown in Table 1, the input data D ₀
When ~ D ₃ changes by 1 bit (in Table 1, for example, when the input data D ₀ ~ D ₃ changes to the data of the next lower row such as "0000" to "0001", or X when changing from "1111" to "0000" on the top line)
The output value of the decoder does not change in many bits, but changes in one bit.

If signals of opposite phases are not used, unlike the output values as shown in Table 1, when the input data changes by 1 bit, a plurality of bits of the output of the X decoder changes at the same time (for example, X _{0 to} X). Data may change from “0” to “1” for all ₇ bits at the same time), which causes a large current to flow in the circuit, causing digital noise.

As described above, by using the two decoder output signals of the positive phase and the negative phase, it is possible to reduce the occurrence of digital noise.

The data D _{3 to} D ₅ are input to the Y decoder 4, latched by the clock pulse φ _C , and output from the Y decoder (Y _P0 ,
Y _S0 ) to (Y _P7 , Y _S7 ) are generated. This relationship is shown in Table 2.

[ _Xn , _n ], [ _Ypm , _Ysm ] (n, m in Tables 1 and 2)
= 0 to 7), the constant current source basic circuit (0,0) to
(7,7) is latched by the clock pulse _C , and the output voltage I _OUT flows. By counting up the data one bit at a time, the constant current source basic circuit shown in FIG. 3 becomes (0,
0) → (1,0) → (2,0) → …… (7,0) → (0,1) → (1,
Conduction in the order of 1) → …… (7,1) → (0,2) → …… (6,7).

For example, if the data is (D ₅ ,, D ₄ ,, D ₃ ,, D ₂ ,, D ₁ , D ₀ ) = (0,0,0,
0,0,0), (X ₀ , X ₁ , X ₂ , X ₃ , X ₄ , X ₅ , X ₆ , X ₇ ) ＝ (1,1,
1,1,1,1,1,1), (Y _P0 , Y _S0 , Y _P1 , Y _S1 , Y _P2 , R _S2 , Y _P3 , Y _S3 , Y
_P4 , Y _S4 , Y _P5 , Y _S5 , Y _P6 , Y _S6 , Y _P7 , Y _S7 ) ＝ (0,1,1,1,1,1,1,1,
1,1,1,1,1,1,1,1,1,1). Constant current source basic circuit (0,0)
According to Fig. 4, Y _P0 = 0, Y _S0 = 1, X ₀ = 1 and NOR
The output of the gate 32 becomes "L" level and clock pulse
_{When C} is at "H" level, the transfer gate 33 becomes conductive and a signal passes through INV34 to make the transistor 35 conductive.
Then, it forms a current mirror structure with the external transistor 38, and takes the current flowing from the transistor 35, which flows through the transistor 36, which functions as a constant current source. When the transistor 35 is non-conducting, current is taken from the transistor 37. That is,
In this series of operations, the output data I _OUT flows through the corresponding number of constant current source basic circuits due to the binary data input from the data D _{0 to} D _5, and the current flowing through all constant current source basic circuits is added. And converted into an analog current amount. In addition, it will be described below that a current flows through the output transistor 37 of the constant current source basic circuit.

The invention challenges the attempts to solve the conventional configuration, to the constant current source basic circuit consists of blocks consisting of a single matrix as shown in FIG. 3, X _n, 2 kinds of _n from X decoder 3 Signal was distributed and the decode signal was supplied to all constant current source basic circuits. Therefore, at the level of each constant current basic circuit, it suffices that either one of the signals X _n and _n be supplied, but due to the configuration, the two signal lines are almost all constant. The wiring had passed over (or near) the basic current circuit.

As a result, the wiring length of the two signal lines of X _n and _n inevitably becomes long, so that an extra wiring area is required when integrated into an integrated circuit, and there is a drawback that the chip size is increased.

Further, there is a drawback that the operation speed becomes slow because the wiring resistance becomes large as the wiring length becomes long.

Furthermore, since two signal lines (X _n and _n ) pass over each constant current basic circuit block 30 shown in FIG. 4, when the outputs passing through these signal lines change at the same time, Analog signal wiring that has capacitive coupling with these signal lines (for example, bias current I _BIAS , bias voltage VC, output voltage I
_It has the drawback of adding extra digital noise to ( _OUT flows) and eventually causing pulse noise (glitch) in the D / A conversion output.

The present invention solves the above-mentioned conventional problems, and when integrated into an IC, a D / A of a segment type matrix structure that reduces the chip area, speeds up the operation speed, and reduces digital noise as compared with the conventional case. The purpose is to submit a conversion device.

Means for Solving the Problems In order to achieve this object, the D / A conversion device of the present invention,
The constant current source basic circuits are arranged in a matrix structure in the X-axis and Y-axis directions, and an X-decoder circuit and a Y-decoder circuit which are decoder circuits in the X-axis and Y-axis directions for selecting each of the constant current source basic circuits.
By dividing at least one of the decoder circuits into the same column or the same row of the matrix of the constant current source basic circuit, the matrix is divided, and the positive phase output of the inserted decoder circuit is divided. The matrix block is supplied to one matrix block, and the output of the opposite phase of the inserted decoder circuit is supplied to the other divided matrix block.

Function This configuration reduces the wiring length of X or Y decode signal
It can be reduced to 1/2, the propagation time of a signal can be shortened, the chip area can be reduced when it is integrated into an IC, and the generation of digital noise that is multiplied by an analog signal can be suppressed.

Embodiment One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a 6-bit D / A in the constant current source addition method of matrix configuration in one embodiment of the present invention.
It shows a conversion device.

In FIG. 1, power supply voltage V _DD , ground voltage V _SS , data D ₀
~ D ₅ , output current I _OUT , and constant current source basic circuit (0,0) ~
The configuration of (7,7) itself is the same as the configuration of the conventional example. Next, 1 is an X decoder, 2 is a Y decoder, 101, 102,
204,207 are NAND gates, 103,105,202,203 are compound gates,
106,107,201,205,222,224,226,228,230,232,234,236 is N
OR gates, 120,122,124,126,128,130,132,134 are buffer gates, 104,108,111 to 119,121,123,125,127,129,13
1,133,208 to 214,223,225,227,229,231,233,235,237 is IN
V, 109 and 110 are AND gates, 135 to 150 and 215 to 221 are transfer gates, and 10 is a resistor. X _{0 to} X ₇ , ₀ to ₇ are X
At the output of the decoder, the signal polarities of X _n and _n (n = 0 ... 7) are opposite. (Y _P0 , Y _P0 ), (Y _P1 , Y _S1 ), (Y _P2 ,
Y _S2 ), (Y _P3 , Y _S3 ), (Y _P4 , Y _S4 ), (Y _P5 , Y _S5 ), (Y
_P6 , Y _S6 ) and (Y _P7 , Y _S7 ) are the outputs of the Y decoder. Matrix array constant current source basic circuit (X, Y) = (0,0) ~
Among (7,7), y = 0,2,4,6 uses the X decoder output X _n as the input of X _j in the constant current source basic circuit of FIG.
= 1,3,5,7 uses the X decoder output _n as the input of X _j . FIG. 2 shows the above connection relationship. This is a matrix constant current source basic circuit, X decode signal output X _n , _n , Y decode signal output (Y _pm , Y _sm ), bias voltage CV, bias current I _BIAS , clock pulse _C ,
5 is a schematic diagram showing a connection relationship of output current I _OUT .

The operation of the matrix-structured D / A conversion apparatus of the present embodiment configured as described above will be described below.

First, according to FIG. 1, of the 6-bit data D _{0 to} D ₅ , the data D _{0 to} D ₃ are input to the X decoder 1. Of which D ₃ is
The clock φ _C causes the X decoder output X _n to be at the “H” level,
It is used for switching when the "L" level is generated, latched by the clock pulse φ _C , and X decoder X _n , _n (n
= 0-7) is generated. And 2 in the X decoder circuit
Decode outputs X _n , _n are supplied to each of the divided constant current basic circuit blocks having a matrix configuration. Further, the data D _{3 to} D ₅ are input to the Y decoder 2, latched by the clock pulse φ _C , and output from the Y decoder (Y _P0 , Y _P0
S0 ) to (Y _P7 , Y _S7 ) are generated. This relationship is shown in Table 3.

Therefore, from data D _{5 to} D ₀ = (0,0,0,1,1,1), data D
₅ ~ D ₀ = (0,0,1,0,0,0) and D ₅ ~ D ₀ = (0,0,1,0,0,
The operation of each part will be described by using the operation 1) as an example. First, when the data D _{0 to} D ₅ are in the state of (0,0,0,1,1,1), the X decoder from Table 1 is used. The output signal of 1 is X ₇ = and X _{0 to} X ₆ =
0, which is the opposite phase of ₇ = 0, ₀ to ₆ = 1. The output signal of the Y decoder 2 is (Y _P0 ,
Y _S0 ) = (0,1), (Y _P1 , Y _S1 )-(Y _P7 , Y _S7 ) = (1,1)
Then, it is latched by φ _C and supplied to the constant current source basic circuit, the constant current source basic circuits from (0,0) to (6,0) become conductive, and the other (0,2) to (7, Up to 7) is cut off. Next, when the data D _{5 to} D ₀ = (0,0,1,0,0,0),
Among the outputs of the X decoder, X _{0 to} X ₆ , ₀ to ₆ do not change, X _{0 to} X ₆ = 0, ₀ to ₆ = 1 remain, and X ₇ = 0, X ₇
= 1 and X ₇ = 0 changes to ₇ = 1. The Y decoder output Y _P0 = 0, Y _{S1 to} Y _S7 = 1 remains unchanged, the Y decoder output Y _S0 is Y _S0 = 1 and Y _S0 = 0, Y _P1 is Y _P1 = 1 to Y
_P1 = 0. As a result, (7,
0) changes from the cutoff state to the conduction state, and therefore the constant current source basic circuits (0,0) to (7,0) turn on and (0,1) to (0,1)
Up to (7,7) is cut off. Then, the data D _{5 to} D ₀
= (0,0,1,0,0,1), among the outputs of the X decoder, X _{1 to} X ₇ , ₁ to ₇ do not change, and X _{1 to} X ₇ = 0, ₁ to
_{With 7} = 1 still, X ₀ = 0 becomes X ₀ = 1 and ₀ = 1 becomes ₀
= 0, the output of the Y decoder remains unchanged (Y _P0 ,
Y _S0 ) = (0,0), (Y _P1 , Y _S1 ) = (0,1), (Y _P2 , Y _S2 ).
~ (Y _P7 , Y _S7 ) = (1,1), the constant current source basic circuit is
(0,0) to (7,0) and (0,1) are conducted, and (1,1) to (7,0)
Up to 7) is cut off.

As described above, according to the present embodiment, by supplying X _n and _n to the constant current source basic circuit block of the matrix configuration divided by the X decoder, the conventional constant current source basic circuit ( X decoded signals that have passed through (or in the vicinity) can be changed from two to one.
The wiring length supplied from the decoder to the constant current source basic circuit is also X
By placing the decoder in the center of the matrix,
Can be halved. Therefore, the buffer of the X decoder and INV can also be designed with a half capacity, and the chip size can be reduced in the case of an IC. Also, the decode signal that causes digital noise is halved for the X decoder.
Further, noise can be reduced by reducing the capacity of the output buffer and INV of the X decoder.

In this embodiment, a 6-bit matrix structure is used.
Although the D / A converter is taken as an example, the present invention is also applicable to all matrix D / A converters.

Further, the matrix structure is divided into two in the Y-axis direction, but it is also possible to form it in the X-axis direction by a Y decoder.

Further, the X decoder 1 for decoding the lower bit group of the input signal is composed of a gate circuit and a transfer gate switch for simplification of description, but it has three inputs of data D ₂ to D ₀ for decoding the lower bit group. , The gate circuit may be configured and decoded only by inputting the least significant bit data D ₃ of the upper bit group. Although this description is based on N-channel MOS transistors, the circuit configuration is P
Obviously, it may be a channel MOS transistor circuit or a CMOS circuit.

EFFECTS OF THE INVENTION According to the present invention, the decode signal wiring is provided by separately supplying two positive-phase and negative-phase output X decode signals generated from the X decoder to the constant current source basic circuit of the matrix configuration divided by the X decoder. Since the length can be shortened, the chip size can be reduced in the case of an IC, and the wiring resistance can be reduced, so that the operation can be performed at high speed. Further, it is possible to realize an excellent D / A conversion device capable of suppressing digital noise to an analog signal caused by a decoded signal.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a 6-bit D / A converter using a constant current source addition method of a matrix configuration in one embodiment of the present invention, and FIG. 2 is a constant current source basic circuit of the D / A converter of the same embodiment. Fig. 3 is a circuit diagram showing the connection relationship between the decode signal and analog signal. Fig. 3 is a circuit diagram of a conventional 6-bit D / A converter.
FIG. 4 is a circuit diagram of the constant current source basic circuit. 1 ... X decoder, 2 ... Y decoder, 3 ... X decoder, 4 ... Y decoder, 10 ... resistor, 31,109,110,349,3
50 …… AND gate, 32,106,107,201,205,222,224,226,22
8,230,232,234,236,306,307,401,402,422,424,426,428,
430,432,434,436 …… NOR gate, 33,135 ~ 150,215,221,
316-331 …… Transfer gate, 35-38,391-396…
... MOS transistors, 34,104,108,111 to 118,121,123,12
5,127,129,131,133,208 to 214,223,225,227,229,231,23
3,235,237,304,308 to 315,332,334,336,338,340,342,34
4,346,348,408 to 414,423,425,427,429,431,433,435,437
...... INV, 103,105,202,203,303,305,403,405 …… Composite gate, 120-134,333,335,337,339,341,343,345,347 ……
Buffer gate, D _{0 to} D ₅ …… 6-bit data, φ _C ……
Clock pulse, _C ... φ _C anti-phase clock pulse, X _{0 to} X ₇ ... X decode output, ₀ to ₇ ... X _n anti-phase X decode output, (Y _P0 , Y _S0 ) ~ ( Y _P7 , Y _S7 ) …… Y
Decode output, I _OUT ... output current, I _BIAS ... bias current, CV ... bias voltage.

Claims (1)

[Claims] 1. An X-decoder circuit, which is a decoder circuit unit in the X-axis and Y-axis directions in which constant current source basic circuits are arranged in a matrix structure in the X-axis and Y-axis directions and which selects each constant current source basic circuit. And at least one of the Y decoder circuits are inserted in the same column or the same row of the matrix of the constant current source basic circuit to divide the matrix, and the positive phase output of the inserted decoder circuit is divided. One of the divided matrix blocks is supplied to the other divided matrix block, and the opposite phase output of the inserted decoder circuit is supplied to the other divided matrix block.
Conversion device.