JPH0787373B2 - Digital-to-analog conversion circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital circuit used as a MOS integrated circuit.
The present invention relates to an analog (D / A) conversion circuit.

2. Description of the Related Art In recent years, digitization of ICs and LSIs used in various electronic devices has advanced. Along with that, digitalization has progressed even in systems that used to be only analog processing, and the number of systems that perform digital processing has increased, excluding the input and output sections, and the importance of digital-analog conversion and analog-digital conversion, which are the contact points, has been increasing. It's getting higher.

A conventional matrix structure D / A conversion circuit will be described below. FIG. 3 is a 6-bit D / A conversion circuit diagram by a conventional constant current source addition method of matrix structure.

φ _C is a 2-phase clock pulse, D _{0 to} D ₅ are 6-bit data, 3
Is an X decoder, 4 is a Y decoder, and 301 and 407 are 3-input NANDs.
Gates, 302,406 are 2-input NAND gates, 303,305,403,405
Is a reconstruction gate, 304,308 to 321,404,408 to 414,416,418,42
0,422,424,426,428,430 is an inverter (hereinafter referred to as INV), 306,402,415,417,419,421,423,425,427,429 is 2
Input NOR gates, 307 and 401 are 3-input NOR gates, 322-32
8,431～437 is transfer gates, X ₀ to X ₇ The output of the X _{decoder, [Y P0, Y S0]} ~ [Y P7, Y S7] is the output of the Y decoder. (0,0) to (7,7) are constant current source basic circuits arranged in a matrix. A resistor 20 is connected to the constant current source basic circuits (0,0) to (7,7). Next, FIG. 4 shows a circuit configuration of the constant current basic circuit. 30 is a basic circuit block of constant current source, 31 is a 2-input AND gate, 32 is 2
Input NOR gate, 33 is transfer gate, 35, 36, 37, 3
Reference numerals 8,391 to 396 are n-channel MOS transistors. X _j is the output of the j-th X decoder, and [Y _Pi , Y _Si ] is the i-th Y decoder.
Decoder output, _C is a reverse phase clock pulse of the two-phase clock pulse φ _C , I _OUT is an output current, CV is an output current I _OUT
I _{BIAS, which} is the bias voltage that controls the current, is the bias current that determines the current value of the constant current source.

The operation of the D / A conversion circuit configured as above will be described below. First, of the bit data D ₀ to D _5, the data D ₀ to D ₂ are input to the X decoder, to generate an X decoder output X ₀ to X ₇ is latched by Kurokuparusu phi _C.
The relationship is shown in Table 1.

The decoders D _{3 to} D ₅ are input to the Y decoder and generate Y decoder outputs [Y _P0 , Y _S0 ] to [Y _P7 , Y _S7 ]. The relationship is shown in Table 2.

For example, if the data is (D ₅ ,, D ₄ ,, D ₃ ,, D ₂ ,, D ₁ D ₀ ) = (0,0,0,0,0,
When 0), (X ₀ , X ₁ , X ₂ , X ₃ , X ₄ , X ₅ , X ₆ , X ₇ ) ＝ (1,1,1,1,
1,1,1,1), (Y _P0 , Y _S0 , Y _P1 , Y _S1 , Y _P2 , Y _S2 , Y _P3 , Y _S3 , Y _P4 , Y
_S4 , Y _P5 , Y _S5 , Y _P6 , Y _S6 , Y _P7 , Y _S7 ) ＝ (0,1,1,1,1,1,1,1,1,1,
It becomes 1,1,1,1,1,1,1,1). The constant current source basic circuit (0,0) is Y _P0 = 0, Y _S0 = 1, X ₀ = 1 from FIG. 4, and the output of the NOR gate 32 is at a low level (hereinafter referred to as “L” level). When the clock pulse _C is at a high level (hereinafter referred to as “H” level), the transfer gate 33 becomes conductive and the signal becomes IN.
Conduct transistor 35 through V34. Then, the external transistor 38 draws from the transistor 35 the current that flows in the transistor 36 that functions as a constant current source. In addition,
When the transistor 35 is non-conductive, it is taken from the transistor 37. That is, in this series of operations, the output data I _OUT flows through the corresponding number of constant current source basic circuits due to the binary data input from the data D _{0 to} D _5, and the current flowing through all constant current source basic circuits is It is added and converted into an analog current amount. In addition, it will be described below that the current flows to the output of the constant current source basic circuit.

When the data D _{0 to} D ₅ are up-counted bit by bit as in the above operation, the constant current source basic circuit (n, m) (n, m
= 0, ..., 7) conducts in the order of (0,0) → (1,0) → (2,0) → ... (7,0), and when all the first columns conduct, next (0,1) becomes conductive, (1,1) → (1,2) →… (7,
1) is conducting. Thus, the data (D ₅ , D ₄ ,, D ₃ ,, D ₂ ,, D ₁ ,
When D ₀ ) = (1,1,1,1,1,1,1), the constant current source basic circuit (7,7) is left and all others are in the conductive state. FIG. 5 shows the order in which the constant current source basic circuit is turned on by the 1-bit up-counting of the above data. The numbers in the circles indicate the order of continuity.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the above-described conventional configuration, since only the positive phase signal is output from the X decoder, and the data D _3- .
When D ₀ = (0,1,1,1) changes to the state of data D _{3 to} D ₀ = (1,0,0,0), or vice versa, X decode output X ₀ ~
An analog signal line having capacitive coupling with the output signal line of the X decoder for changing X ₆ to “H” level “L” level or from “L” level to “H” level at the same time (for example,
There is a problem that digital noise is superimposed on the bias current I _BIAS , the bias voltage CV, and the signal line through which the output current I _OUT flows, and pulse noise (glitch) is generated in the output.

The present invention solves the above-mentioned conventional problems, and provides a D / A conversion circuit having a matrix structure capable of minimizing changes in the X decoder outputs X _{0 to} X ₇ and eliminating output glitches. That is the purpose.

Means for Solving the Problems A plurality of current source basic circuits arranged in a matrix structure, and an X decoder circuit and a Y decoder circuit for outputting a signal for switching ON / OFF of the plurality of current source basic circuits are provided. , The Y decoder circuit decodes the data of the upper bit group of the input data and outputs it for each column of the current source basic circuit of the matrix structure, and the X decoder circuit decodes the data of the lower bit group of the input data to form the matrix structure. The data is output for each row and the least significant bit data of the upper bit group is input to the X decoder circuit. When the least significant bit data is inverted, the X decoder circuit inverts the output, and among all the columns of the matrix structure. The positive phase of the output of the X decoder circuit is input to half of the columns of and the opposite phase of the output of the X decoder circuit is input to the other half of columns. , Y decoder circuit and X decoder circuit have input data of "1"
If the current source basic circuit in the same column is turned on,
When all the current source basic circuits in one column are switched on and off by switching them off sequentially, the upper bits are set so that the current source basic circuit for the column to which the phase of the inversion relation is input is switched on and off. It is characterized in that switching to the next column is performed at the timing when the data of the least significant bit of the group is inverted, and when the input data changes by "1", only the output for one row of the X decoder circuit is inverted. .

Action With this circuit configuration, in all cases where the data changes by 1 bit, the change in the output signal line of the X decoder becomes only one row, and at the same time, the positive phase of X _n and _n is output on the output signal line of the X decoder. By outputting a signal having a phase opposite to that of the signal, it is possible to cancel fluctuations in the digital signal and to minimize noise on the analog signal due to the digital signal. As described above, the occurrence of glitches due to this type of cause can be eliminated.

Embodiment One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a 6-bit D / A conversion circuit according to a constant current source addition method having a matrix configuration according to an embodiment of the present invention.

In FIG. 1, power supply voltage V _DD , ground voltage V _SS , Y decoder
2, data D ₀ ~ D ₅ , output current I _OUT , constant current source basic circuit (0,
0) to (7, 7) are the same as the configuration of the conventional example. Next, 1 is an X decoder, 101 and 207 are 3-input NAND gates, 10
2,206 is a 2-input NAND gate, 103,205,105,203 is a decompression gate, 107,201 is a 3-input NOR gate, 149,150 is an AND gate,
104,108 ~ 115,132,134,136,138,140,142,144,146,148,2
08〜214,223,225,227,229,231,233,235,237 is INV, 133,
135,137,139,141,143,145,147 are buffer circuits, 106,20
2, 222, 224, 226, 228, 230, 232, 234, 236 are 2-input NOR gates, 116 to 131, 215 to 221 are transfer gates, and 10 is a resistor. [X ₀ , ₀ ], [X ₁ , ₁ ], [X ₂ , ₂ ],
_{[X 3, 3], [} X 4, 4], [X 5, 5], [X 6,
₆ ] and [X ₇ , ₇ ] are outputs of the X decoder, and X _n and _n
(N = 0 ... 7) has the opposite signal polarity. [Y _S0 , Y _P0 ],
[Y _S1,, Y _P1 ], [Y _S2 , Y _P2 ], [Y _S3 , Y _P3 ], [Y _S4 ,
Y _P4 ], [Y _S5 , Y _P5 ], [Y _S6 , Y _P6 ], [Y _S7 , Y _P7 ] are the matrix decoder constant current source basic circuit (x, y) = ( 0.0)-(7,7 of y = 0,2,4,6 is the fourth
As inputs x _j in the constant current source basic circuit of FIG, with X decoder output X _n, y = 1, 3, 5, 7 are used X decoder output _n as inputs x _j. The above connection is shown in FIG. 2, which is a matrix constant current source basic circuit, X decoder signal output [X _n , _n ], Y decode signal output [Y _Pm , Y _Sm ], bias. Voltage CV, bias current I _BIAS ,
6 is a schematic diagram showing a connection relationship between a clock pulse _C and an output current I _OUT .

The matrix configuration of the present embodiment configured as described above
The operation of the D / A conversion circuit will be described below.

First, from FIG. 1, data out of 6-bit data D _{0 to} D ₅
D _{0 to} D ₃ are input to the X decoder 1. Data D ₃
Is used for switching between generation of the X decoder output X _n n “H” level and generation of the “L” level, latched by the clock pulse φ _C , and X decoder output [X _n , _n ] (n = 0-7) is generated. This relationship is shown in Table 3.

Further, the data D _{3 to} D ₅ are input to the Y decoder 2, latched by the clock pulse φ _C , and output from the Y decoder [Y _S0 ,
_YP0 ] to [ _YP7 , _YS7 ] are generated. This relationship is shown in Table 2 above.
Shown in. [X _n , _n ], [Y _Sm , Y _Pm ] in Tables 2 and 3
Due to the relationship (n, m = 0 to 7), the constant current source basic circuit (0,
0) to (7,7) are latched by the clock pulse _C , and the output current I _OUT flows. The order in which the constant current source basic circuit is turned on by the up count of each bit of data is
Similar to the conventional example, it becomes the one shown in FIG.

Therefore, from data D _{5 to} D ₀ = (0,0,0,1,1,1), data D ₅
~ D ₀ = (0,0,1,0,0,0) When the operation is described as an example, data D ₅ ~ D ₀ = (0,0,0,1,1,1) At this time, the output signal of the X decoder 1 is X ₇ = 1 and X _{0 to} X ₆ = 0.
₇ = _{0, 0-6} = 1, the signal of the Y decoder 2 [Y
_{P0 = 0, Y S0 = 1} ], [Y P1, Y S1] ~ are latched by _{[Y P7, Y S7] =} 1 next clock pulse phi _C, is input to the constant current source basic circuit, the constant current source basic circuit Is latched by clock pulse _C and the constant current source basic circuits (0,0) to (6,0) are conducting, and the other constant current source basic circuits (7,0) to (7,7) are in the cutoff state. Become. Next, the data D _{5 to} D ₀ = (0,0,1,0,0,
0) and 1-bit data is up, X decoder output X
₀ to X ₆ and _0-6 is not _{changed, X 0 ~X 6 = 0,} 0 ~
₆ = 1, the X decoder output X ₇ is X ₇ = to X ₇ = 0
And vice versa, the X decoder output ₇ is ₇ = 0 to ₇
Changes to = 1. Also, the output of the Y decoder Y _P0 = 0, Y _S1 ~
Y _S7 = 1 remains unchanged, Y decoder output _S0 changes from Y _S0 = 1
When Y _S0 = 0, the Y decoder Y _P1 changes from Y _P1 = 1 to Y _P1 = 0. As a result, the latching operation of the clock pulse _C causes (7,0) of the constant current source basic circuit to change from the cut-off state to the conductive state, so that the constant current source basic circuit (0,0) to
Conducting up to (7,0), constant current source basic circuit (0,1) to (7,0)
It is cut off until 7).

Next, the difference between the prior art and the present invention will be described in more detail with reference to FIGS. 6 and 7. FIG. 6 shows the relationship between the output of the X, Y decoder circuit and the ON / OFF state of the current source basic circuit in the conventional example, and FIG. 7 shows the X, Y decoder in one embodiment of the present invention. The relationship between the output of the circuit and the ON / OFF state of the current source basic circuit is shown. In addition, in these figures, in order to simplify the explanation,
It shows a matrix of 4 rows, and the input bit data is 5 bits of D _{0 to} D ₄ , and the upper 2 bits of D ₄
And D ₃ are input to the Y decoder circuit, and the lower 3 bits D ₀
It is assumed that ~ D ₂ is input to the X decoder circuit. In the embodiment of the present invention (FIG. 7), the least significant bit D ₃ of the upper bit group is also input to the X decoder circuit.

First, the points common to FIGS. 6 and 7 will be described. In these figures, (a) to (c) are
8 shows a matrix of 8 current rows × 4 columns = 32 current source basic circuits. Further, (a) is the case where the input bit data is (D ₄ , D ₃ , D ₂ , D ₁ , D ₀ ) = ( ₀ , ₀ , ₁ , ₁ , ₁ ), and (b) is the (D ₄ , D ₃ , D ₂ , D ₁ , D ₀ ) = (0, 1,
0, 0, 0), and (c) is (D ₄ , D ₃ , D ₂ , D ₁ ,
The matrix of the current source basic circuit in the case of D ₀ ) = ( _{0, 1, 0, 0, 1} ) is shown, and the bit data changes by “1” in the order of (a), (b) and (c). ing. Also, X ₀ ~
X ₇ is the output of the X decoder circuit, Y _{P0 to} Y _P3 and Y _S0 to Y _S3 are the outputs of the Y decoder circuit, all of which are shown in Table 1 above.
~ It has the relation of Table 3. The three-digit number shown in each current source basic circuit corresponds to one output of the X decoder circuit and two outputs of the Y decoder circuit (X _i , Y
_Pj , Y _Sj ) in that order. Also, as shown in the drawing, this current source basic circuit is (X _i , Y _Pj ,
Y _Sj ) = (0, 0, 1) or (1, 0, 0) or (0, 0, 0) turns on, and otherwise sets off. With this setting,
When (Y _Pj , Y _Sj ) = (0, 0), the current source basic circuit is always turned on regardless of the value of X _i , and (Y _Pj , Y _Sj ) =
When (1, 1), the current source basic circuit is always turned off regardless of the value of X _i , and when (Y _Pj , Y _Sj ) = (0, 1), the value of X _i is 0 or 1. Depending on, it can be switched on and off. Further, in both FIG. 6 and FIG. 7, the relationship between the input bit data and the ON / OFF state of the current source basic circuit is the same, and when the bit data changes by “1”, one current source basic circuit is changed. The on / off state of changes.

In the case of the conventional example, as shown in FIG. 6 (a), when the bit data (D ₄ , D ₃ , D ₂ , D ₁ , D ₀ ) is ( ₀ , ₀ , ₁ , ₁ , ₁ ), the table From the relationship of 1, the output of the X decoder circuit is (X ₇ , X ₆ , X ₅ , X ₄ , X ₃ , X ₂ , X ₁ , X ₀ ) = (1, 0, 0,
0, 0, 0, 0, 0), and from the relationship of Table 2, the output of the Y decoder circuit is Y _P0 = 0, and 1 otherwise. Therefore, the output to each current source basic circuit becomes as shown in the figure, and the seven current source basic circuits in the leftmost column in the figure turn on,
Other current source basic circuits are turned off.

Next, as shown in FIG. 7B, bit data (D ₄ , D ₃ ,
D ₂ , D ₁ , D ₀ ) changes by "1" ( ₀ , ₁ , ₀ , ₀ ,
0), the output of the X decoder circuit is (X ₇ , X ₆ , X ₅ , X ₄ , X ₃ , X ₂ , X ₁ , X ₀ ) = (1, 1, 1,
1,1,1,1,1,1), and changes greatly. The output of the Y decoder circuit is Y _P0 , Y _S0 and Y _{P1 according} to the relationship in Table 2.
= 0 and 1 for all other cases. Therefore, the output to each current source basic circuit becomes as shown in the figure, and all the eight current source basic circuits in the leftmost column in the figure turn on and the other current source basic circuits turn off.

Further, as shown in (c) of the figure, bit data (D ₄ , D ₃ ,
D ₂ , D ₁ , D ₀ ) is further changed by “1” (0, 1,
When it becomes 0, 0, 1), the output of the X decoder circuit is (X ₇ ,
X ₆ , X ₅ , X ₄ , X ₃ , X ₂ , X ₁ , X ₀ ) = ( ₁ , ₁ , ₁ , ₁ ,
, 1, 1, 1, 0), and only one line changes. Further, the output of the Y decoder circuit does not change. For this reason, the output to each current source basic circuit becomes as shown in the figure, and a total of nine current source basic circuits, eight in the left end column and one in the adjacent column, are turned on, and other current source basic circuits are turned on. The current source basic circuit is turned off. Also in this case, if only the bit data “1” changes, the ON / OFF state of the current source basic circuit also changes by one.

That is, when the bit data changes by "1", the ON / OFF state of the current source basic circuit changes by one,
As shown in the above example, at the timing when the lower bit group of the bit data input to the X decoder circuit is carried (the timing at which (a) changes to (b)), the output of the X decoder circuit greatly changes, It was a cause of noise.

The reason for this is that the matrix of the current source basic circuit has 8 rows, but the output of the X decoder circuit is 8 types as shown in Table 1, and therefore the output of the X decoder circuit is (1, From the state of 1, 1, 1, 1, 1, 1, 1, 1), the state is changed one by one, and at the seventh change, (1, 0, 0, 0,
This is because most of the outputs must be inverted to return to the original state at the next change.

Next, an embodiment of the present invention is shown in FIG. The configuration of the X decoder circuit in the present embodiment is the same as that shown in FIG. 1, and a positive phase output and a negative phase output which are in an inverse relationship with each other are output for each row. Further, in the example of FIG. 7, the positive-phase output X is input to the current source basic circuits in the first and third columns from the left, and the negative-phase output is in the second and fourth columns from the left. Input to the current source basic circuit. As described above, the present invention can be configured so that the positive phase of the output of the X decoder circuit is input to half the columns of the current source matrix and the opposite phase of the output of the X decoder circuit is input to the other half column. Is one of the features of. Further, as can be seen from the circuit configuration shown in FIG. 1, the X decoder circuit has the least significant bit of the upper bit group.
When D ₃ is input and the logic of this D ₃ is inverted, all the outputs of the X decoder circuit are inverted.

As shown in FIG. 7A, bit data (D ₄ , D ₃ ,
When D ₂ , D ₁ , D ₀ ) is ( ₀ , ₀ , ₁ , ₁ , ₁ ), the positive phase output of the X decoder circuit is (X ₇ , X ₆ ,
X ₅ , X ₄ , X ₃ , X ₂ , X ₁ , X ₀ ) = ( ₁ , ₀ , ₀ , ₀ , ₀ ,
0, 0, 0), and the negative phase outputs ₇ to ₀ become the inverted logic signals. Also, the output of the Y decoder circuit is Y _P0 = 0 and 1 otherwise except from the relationship of Table 2 as in the conventional case. Therefore, the output to each current source basic circuit becomes as shown in the figure, and the seven current source basic circuits in the leftmost column in the figure turn on and the other current source basic circuits turn off. That is,
Compared with FIG. 6A showing a conventional example, the same input data (bit data) is subjected to the same ON / OFF control.

Next, as shown in FIG. 7B, bit data (D ₄ , D ₃ ,
D ₂ , D ₁ , D ₀ ) changes by "1" ( ₀ , ₁ , ₀ , ₀ ,
At 0), since the logic of D ₃ is inverted from “0” to “1”, all the outputs of the X decoder circuit are inverted. That is, the output of the X decoder circuit is, as shown in Table 3, positive phase outputs (X ₇ , X ₆ , X ₅ , X ₄ , X ₃ , X ₂ , X ₁ , X ₀ ) = (0,
0, 0, 0, 0, 0, 0, 0), negative phase output ( ₇ ,
₆ , ₅ , ₄ , ₃ , ₃ , ₂ , ₁ , ₀ ) = (1,
1, 1, 1, 1, 1, 1, 1, 1). That is, unlike the conventional example, in the present embodiment, the output of the X decoder circuit changes only in one row. Further, the output of the Y decoder circuit is 0 for Y _P0 , Y _S0 and Y _{P1 according} to the relationship in Table 2 as in the conventional example, and is 1 for the other outputs. Therefore, the output to each current source basic circuit becomes as shown in the figure, and all the eight current source basic circuits in the leftmost column in the figure turn on and the other current source basic circuits turn off. That is, the on / off state of the current source basic circuit is the same as the conventional one. In this embodiment, the lower bit group of the bit data that is the input data carries (or, conversely, carries down) as in the case of this figure (b), and the least significant bit D _{3 of the} upper bit group. At the timing at which the logic of is reversed, (Y _P0 , Y _S0 ) = (0, 0) and (Y _P1 , Y _S1 ) = (0, 1). That is,
The Y decoder circuit switches the ON / OFF switching target column from the column for inputting the positive phase output to the column for inputting the negative phase output at the timing when the logic of D ₃ is inverted. As described above, in the present embodiment, the current source basic circuits are switched on and off for each column, and when the on / off switching of all the current source basic circuits of one column is completed, the column having the inversion relation is next. It is controlled to switch on and off.

Further, as shown in (c) of the figure, bit data (D ₄ , D ₃ ,
D ₂ , D ₁ , D ₀ ) is further changed by “1” (0, 1,
0, 0, 1), the positive phase output of the X decoder circuit is (X ₇ , X ₆ , X ₅ , X ₄ , X ₃ , X ₂ , X ₁ , X ₀ ) = (0, 0, 0,
0, 0, 0, 0, 1), and only one line changes. The output of the Y decoder circuit does not change as in the conventional example. For this reason, the output to each current source basic circuit is as shown in the figure, and there are a total of 9 currents, 8 in the leftmost column in the figure and 1 in the adjacent column (column to which the reverse phase output is input). The source basic circuit is turned on and the other current source basic circuits are turned off. Also in this case, since the bit data has changed by "1", only one ON / OFF state of the current source basic circuit has changed.

As described above, in the present embodiment, the least significant bit D ₃ of the upper bit group is input to the X decoder circuit, and 4 bits of this D ₃ and the lower bit group (D ₂ , D ₁ , D ₀ ) are used. Since the output of the X decoder circuit is determined by X, only (D ₂ , D ₁ , D ₀ )
Compared with the conventional case where the output of the decoder circuit is determined, the type of output of the X decoder circuit is doubled (see Table 3). Therefore, the output (for example, the positive phase output) of the X decoder circuit becomes 1 in order from the state of (1, 1, 1, 1, 1, 1, 1, 1, 1).
Each time, the 7th change (1, 0, 0, 0,
It becomes 0, 0, 0, 0), and it is not necessary to return to the original state (1, 1, 1, 1, 1, 1, 1, 1, 1) at the next change, and only one line is changed. (0, 0, 0, 0, 0, 0,
It becomes possible to set it to 0, 0). Then, the output of each line is changed in order, and the original output state (1,
1, 1, 1, 1, 1, 1, 1, 1) (see Table 3). Therefore, the output of the X decoder circuit does not suddenly change greatly.

In addition, the output of the X decoder circuit is inverted in response to the change in the output of D ₃ , and Y is controlled to control the column to which the phase in the inversion relationship is input at the timing when the output of D ₃ changes. Since the decoder circuit operates, the ON / OFF switching control of the current source basic circuit can be controlled in the same manner as in the conventional case.

As described above, according to the present embodiment, in all cases in which the data change to the X decoder changes by 1 bit by the main decoding method of the X decoder 1, the outputs X _{0 to} X ₆ of the X decoder are generated.
Can prevent the output signals from changing from "H" level to "L" level or from "L" level to "H" level at the same time. Therefore, the digital noise on the bias current I _BIAS , the bias voltage CV and the output current I _OUT that the analog signal in the constant current source basic circuit flows can be minimized, and the digital noise can be reduced by about 6bB compared to the conventional example. Can be reduced. Therefore, it is possible to largely eliminate the occurrence of glitches due to the variation of this kind of analog reference signal.

It should be noted that in the present embodiment, the D /
A conversion circuit is taken as an example, but D of all matrix structures
It is also applicable to the / A conversion circuit.

Further, the X decoder 1 which decodes the lower bit group of the input signal is composed of a gate circuit and a transfer gate switch for simplifying the description. However, the data D ₂ to D ₀ 3 input for decoding the lower bit group, The gate circuit may be configured and decoded only by inputting the least significant bit data D ₃ of the upper bit group. And this description is all N channel MO
Although it is based on the S-transistor, it is obvious that the circuit configuration may be a P-channel MOS transistor circuit or a CMOS circuit.

The present invention uses the least significant bit (LSB) input data of the upper side data of the Y decoder for the X decoder that uses the lower side data in the input data, and outputs the two outputs of the positive phase and the negative phase. X
A decoder circuit that can minimize the simultaneous change of the X decode output signal in all cases where the data changes by 1 bit when a decoder signal is generated and the constant current source basic circuit of matrix structure is turned on or off. By providing the section, the digital noise can be significantly reduced, and the effect of canceling the switching noise can be obtained by using the two-phase X-decode output signal of the reverse phase in which the positive phase and the polarity are inverted. It is possible to realize a D / A conversion circuit.

[Brief description of drawings]

FIG. 1 is a 6-bit D / A conversion circuit diagram by a matrix-structured constant current source addition method in an embodiment of the present invention, and FIG. 2 is a constant current source basic circuit and a decode signal of the D / A conversion circuit of the present invention, A schematic diagram showing the connection relationship between the analog signal and the latch clock signal, FIG. 3 is a conventional 6-bit D / A conversion circuit diagram, FIG. 4 is a circuit diagram of a constant current source basic circuit, and FIG. FIG. 6 is a diagram showing the order in which the constant current source basic circuit of the A / A conversion circuit sequentially conducts from the complete cutoff state according to data.
FIG. 7 is a diagram showing the relationship between the output of the X, Y decoder circuit and the current source basic circuit in the conventional example, and FIG. 7 is a diagram showing the relationship between the output of the X, Y decoder circuit and the current source basic circuit in the embodiment of the present invention. Is. 1 ... X decoder, 2 ... Y decoder, 10 ... resistor, 11
6〜131,215〜221 …… Transfer gate, 101,207 ……
3-input NAND gate, 102,206 ... 2-input NAND gate, 10
3,105,203,205 …… Reconstruction gate, 104,108 to 115,132,134,
136,138,140,142,144,146,148,208〜214,223,225,227,2
29,231,233,235,237 …… INV, 106,202,222,224,226,22
8,230,232,234,236 …… 2-input NOR gate, 107,201 ……
3-input NOR gate, 149,150 ... 2-input AND gate, 133,1
35,137,139,141,143,145,147 …… Buffer gate, D ₀ ~
D ₅ ... 6-bit data, φ _C ... clock pulse, _C
... φ _C anti-phase clock pulse, X _{0 to} X ₇ ... decoder output, ₀ to ₇ ... X _{0 to} X ₇ anti-phase X decoder output, [Y
_P0 , Y _S0 ]-[Y _P7 , Y _S7 ] …… Y decoder output, I _OUT ……
Output current, I _BIAS ... bias current, CV ... bias voltage.

Claims (1)

[Claims] 1. A plurality of current source basic circuits arranged in a matrix structure, and an X decoder circuit and a Y decoder circuit for outputting a signal for switching ON / OFF of the plurality of current source basic circuits. The Y decoder circuit decodes the data of the upper bit group of the input data and outputs the decoded data for each column of the current source basic circuit of the matrix structure.
The decoder circuit decodes the data of the lower bit group of the input data and outputs it for each row of the current source basic circuit of the matrix structure, and inputs the data of the least significant bit of the upper bit group to the X decoder circuit, When the data of the least significant bit is inverted, the X decoder circuit inverts the output, and the positive phase of the output of the X decoder circuit is input to half of all the columns of the matrix structure and the other half of the columns are input. The configuration is such that the opposite phase of the output of the X decoder circuit is input to the column, and the Y decoder circuit and the X decoder circuit turn on the current source basic circuit of the same column when the input data changes by "1". -When the current source basic circuits in one column are switched on and off, the current source basic circuit is turned on and off for the column to which the phase in the inverting relationship is input next. Is switched to the next column at the timing at which the data of the least significant bit of the upper bit group is inverted, and when the input data changes by "1", only the output for one row of the X decoder circuit is inverted. A digital-to-analog conversion circuit characterized by: