JPS63236414A - Digital-analog converting circuit - Google Patents

Abstract

PURPOSE:To prevent pulse noise from being generated, by providing a decoder circuit which suppresses the change of an X decode output at the minimum level, in all cases where data change by one bit. CONSTITUTION:In an X decoder 1 which uses the data D0-D2 on low-order sides out of input data D0-D5, an X decode signal having two outputs of two phases, a positive phase and a negative phase, is generated by using the input data of the least significant bit D3 on the high-order side of a Y decoder 2. Thereby, at the time of energizing/de-energizing constant current source fundamental circuits 0.0-7.7 with matrix structure, it is possible to prevent the output signals of the outputs X0-X7 of the decoder 1 from being changed simultaneously from H levels to L levels, or from the L levels to the H levels in all cases where the data to the X decoder 1 change. Therefore, it is possible to suppress noise on an analog signal due to a digital signal at the minimum level.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital-to-analog (D/A) conversion circuit used as an MO8 integrated circuit.

BACKGROUND ART In recent years, the digitalization of ICs and LSIs used in all kinds of electronic devices has progressed. As a result, systems that previously only performed analog processing have become digitalized, and with the exception of input/output sections, the number of systems that perform digital processing has increased, and this is the point of contact.

Digital-to-analog conversion and analog-to-digital conversion have become increasingly important.

A conventional matrix-structured D/A conversion circuit will be described below. FIG. 3 is a diagram of a 6-bit D/A conversion circuit using a conventional matrix structure constant current source addition method.

φC is a two-phase clock pulse, Do=Ds is 6-bit data, 3 is an X decoder, 4 is a Y decoder, 301°407
is a 3-man power NAND gate, 302.406 is a 2-man power NA
ND gate, 303, 305, 403 ° 405 is a composite gate, 304, 308 ~ 321 ° 404. 408 ~ 41
4,416,418,420°422.424,426
, 428.430 is Inverk (hereinafter referred to as INV),
306,402°415,417,419,421,4
23,425°427.429 is a two-person NOR gate,
307°401 is a 3-person NOR gate, 322~32
8゜431~437 are transfer gates, XO~X
7 is the output of the X decoder, [Ypo, Yso] ~ [YF
3°YS7] is the output of the X decoder. (0,O)～
(7, 7) is a constant current source basic circuit arranged in a matrix. 20 is a resistor and is a constant current source basic circuit (0,0)
~(7,7). Next, the circuit configuration of the constant current basic circuit is shown in FIG. 30 shows a constant current source basic circuit block, 31 shows a two-man power AND gate, and 32 shows a two-man power AND gate.
Human powered NOR gate, 33 is transfer gate, 35,
36°37.38.391-396 are n-channel MOS
It is a transistor. Xi is the output of the i-th X-decoder, [Yp+, Yst] is the output of the i-th The bias voltage IBIAS is a bias current that determines the current value of the constant current source.

The operation of the D/A conversion circuit configured as described above will be explained below. First, bit data D o
= D Of s, data DO to D2 are input to the X decoder and latched by the clock pulse φC to generate the X decoder output xo-X7. The relationship is shown in Table 1.

Table 1 Also, data D3 to D5 are input to the X decoder,
Decoder output [Ypo, Yso] to [Yp7. Y.S.
7] is generated. The relationship is shown in Table 2.

For example, if the data is <Ds, D4. Ds, D2.
When DIDo) = (0, O, O, O, 0, 0), (
Xo, XI, X21 X3. X4.
xs, xe, X7) = (1, 1+ 1
．． 1.1+ 1.1), (Ypo, Yso.

YpHYSII YP2I Yst1 YP3I YS
S1 YP41YS4. YPS, YSS, YPS, YS
8. YF3. YS7) = (0, 1, 1, 1, 1, 1, 1
,1,1,1,1゜1.1.1,1.1). From Figure 4, the constant current source basic circuit (0,0) is as follows: Ypo=O,
Yso=1.

Xo=1, and the output of the NOR gate 32 is at a low level (
(hereinafter referred to as "L" level), and the clock pulse t
When fic is at a high level (hereinafter referred to as "H" level), the transfer gate 33 is conductive and the signal is INV3.
4 and makes the transistor 35 conductive. Then, an external transistor 38 takes the current flowing through the transistor 36 which acts as a constant current source from the transistor 35.

Note that when the transistor 35 is non-conductive, the signal is taken from the transistor 37. In other words, with this series of operations, the data D o
=D Depending on the binary data coming from s,
Output current 10 to the corresponding number of constant current source basic circuits
The currents flowing through the UT and all constant current source basic circuits are added and converted into an analog current amount. Note that the fact that a current flows through the output of the constant current source basic circuit is hereinafter referred to as conduction.

As described above, when the data D o = D s is counted up bit by bit, the constant current source basic circuit (n, m) (n, m = o, =, 7) becomes (0° O)→(
1,0)→(2,O) Pass...Conductivity progresses in the order of (7,0), and when all the first rows become conductive, then (0,1)
becomes conductive, and (1, 1) → (1, 2) →...(
7,1) is conductive. In this way, the data (D5. D
tl D31 D2. DI, Do) = (1, 1, 1
, 1, 1, 1), the constant current source basic circuit (7, 7>
All but 1 are in a conductive state. 1 of the above data
By counting up bit by bit, the constant current source basic circuit becomes conductive (the order is shown in FIG. 5).The numbers in the circles indicate the order in which the constant current source becomes conductive.

Problems to be Solved by the Invention However, in the above conventional configuration, the data D3 to D
From O=(0,1,1,1), data D3~Do=(1
, 0, O, O) or vice versa, the X decode outputs XO to X6 simultaneously change from "H" level to "L" level or from "L" level to "H" level. In order to
B1^S, the bias voltage Cv, and the signal line through which the output current IOUT flows), digital noise is added to the signal line through which the output current IOUT flows, resulting in the problem of generating pulse noise (glitch) in the output.

The present invention solves the above-mentioned conventional problems, and is a D/A with a matrix configuration that can minimize the change in the X decoder output Xo-X7 and eliminate the occurrence of glitches in the output.
The purpose is to submit a conversion circuit.

Means for Solving the Problems In the digital-to-analog conversion circuit of the present invention, constant current source basic circuits are arranged in a matrix structure in the X-axis and Y-axis directions, and the X-axis selects each of the constant current source basic circuits. and the X decoder circuit and the Y decoder circuit, which are the decoding circuit sections in the Y-axis direction (one output outputs two outputs of positive phase and reverse phase, and the same positive phase output and the negative phase output are determined as described above). Inputs are alternately input to each column of the basic current source circuit, and this decoder circuit, which has positive and negative phase outputs, decodes all inputs corresponding to the lower bit group and the least significant bit input of the upper bit group. be.

Effect: With this circuit configuration, in all cases where the data changes by one bit, the output signal line of the X decoder changes by only one line, and at the same time, the positive phase of Xn and Xn appears on the output signal line of the X decoder. By outputting signals of opposite phase, fluctuations in the digital signal can be canceled out, and noise caused by the digital signal on the analog signal can be minimized. As described above, it is possible to prevent the occurrence of glitches due to this type of cause.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a 6-bit D/A using a matrix-configured constant current source addition method in an embodiment of the present invention.
It shows a conversion circuit diagram.

In FIG. 1, the power supply voltage V DD and the ground voltage V s
s, X decoder 2. Data Do-Da, output current 1
0U, constant current source basic circuit (0, O) ~ (7, 7),
This is the same configuration as the conventional example. Next, 1 is an X decoder, 101.207 is a three-man NAND gate, and 102.2
06 is a two-person NAND gate, 103.205,105
, 203 is a composite gate, 107.201 is a 3-person NOR
Gate, 149°150 is AND gate, 104,10
8~115°132.134,136,138,140
, 142°144.146, 148.208~214,
223°225.227,229,231,233,2
35°237 is INV, 133,135,137,13
9゜141.143, 145, 147 are buffer circuits,
106,202,222,224,226°228.2
30, 232, 234, 236 are two-person NOR gates,
116 to 131, 215 to 221 are transfer gates, and 10 is a resistor. [Xo.

Xol, [XI, Xtl・[X2・X2]・[Xs・
X3]・[X41X4]1 [XS, XS1. [Xa
, Xal, [X7. Xtl is the output of the X decoder,
n and Xn (n -0...7) have opposite signal polarities o
[Yso, Ypol, [ysl, Yp+].

[YS21 YP2], [YS3. YP3],
[YS4. YP4].

[Yss, Ypsl, [Yse, Ypsl,
[YS71 YP7] is the output of the Y decoder, a constant current source basic circuit (x, y) = (0
, 0) to (7, 7), y=o, 2, 4.6 uses the X decoder output Xn as the input of Xj in the constant current source basic circuit of FIG. .7 uses the X decoder output Yn as the input of Xj. Figure 2 shows the above connection relationship, which shows the basic constant current source circuit in matrix configuration, the X decode signal output [Xn, Xn1-
Y decode signal output [Yp-, Ys-].

It is a schematic diagram showing the connection relationship of bias voltage Cv, bias current IBIASp clock pulse φC2 output current 10LIT.

The operation of the matrix-configured D/A conversion circuit of this embodiment configured as described above will be described below.

First, as shown in FIG. 1, among the 6-bit data Do-DS, data DO-D3 is input to the X decoder 1.

Among them, data D3 is used to switch between generating an "H" level and 'L' level at the X decoder output Xn, and is latched by the clock pulse φC and outputs the X decoder output [Xfl, XI, ]( n=0~7
) occurs. This relationship is shown in Table 3.

(Margin below) Data D3 to D5 are also input to the X decoder 2, latched by the clock pulse φC, and output from the Y decoder [Ys
o, Ypol ~ [YF71 YS7] is generated. This relationship is shown in Table 2 above. [X
n, Xnl, [YslYpsl (n, m=
0~7), the constant current source basic circuit (0°O)~
(7, 7) is latched by the clock pulse tlyc, and an output current of 10UT flows. As the data is counted up one bit at a time, the constant current source basic circuit becomes conductive in the same order as shown in FIG. 5, as in the prior art example.

Therefore, data Ds~Do= (0, O, 0, 1°1.
1>, data Ds~Do=(0,0,1,0°0.0
) to explain the operation as an example, the data Ds~Do
= (0,0,0,1,1,1), the output signal of X decoder 1 is X7=1 and XO~X6=0, and its opposite phase is X7=O and Xo-Xe=1. , the signal of the X decoder 2 is [Ypo=O, Yso=1].

[Yp+, Ys+] ~ [YF3. YS7] =
1, which is latched by clock pulse φC and input to the constant current source basic circuit, which is latched by clock pulse φC and input from constant current source basic circuit (0, O) to (6,
0), and other constant current source basic circuits (7,0
) to (7, 7) are in the cutoff state. Next, when the 1-bit data increases as data D5 to Do=(0,0,1,0°0.0), the outputs X0-X6 and Xo-xs of the X decoder do not change, and Xo=Xs=O, Xo−X5=
1, the X decoder output X7 changes from X7=1 to X7=
0, and vice versa, the X decoder output X7 changes from X7=0 to
Changes to 7=1. Also, the output YPO=O of the Y decoder
I YSI ~ Ys7 = 1 remains as before, Y decoder output YSO changes from Yso = 1 to Yso = O Y decoder YPI
Since YPI = 1, YPI = O. As a result, due to the latching operation of the clock pulse φC, (7,0) of the constant current source basic circuit changes from the cut-off state to the conductive state, and therefore the constant current source basic circuit (0,0) to (7°O)
The constant current source basic circuit (0,1) to (7,7
) will be cut off.

As described above, according to this embodiment, due to the present decoding method of the X decoder 1, in all cases where the data to the X decoder changes by 1 bit, the output of the X decoder X o
= X s output signal goes from “H” level to “L” at the same time
It is possible to eliminate the change from the "L" level to the "H" level. Therefore, the bias current IBI^S through which the analog signal in the constant current source basic circuit flows, the bias voltage Cv and the output current 10UT
It is possible to minimize the digital noise caused by the noise, and it is possible to reduce the digital noise by about 6 bB compared to the conventional example. Therefore, the occurrence of glitches due to variations in this type of analog reference signal can be largely eliminated.

In addition, in this embodiment, D with a 6-bit matrix structure
Although the /A conversion circuit is taken as an example, the present invention is also applicable to all matrix-structured D/A conversion circuits.

In addition, the X decoder 1 that decodes the lower bit group of the input signal is configured with a gate circuit and a transfer gate switch to simplify the explanation, but the A gate circuit may be configured and decoded only by inputting the least significant bit data D3 of the bit group. Although this description is based on an N-channel MOS transistor, it is clear that the circuit configuration may be a P-channel MO8) transistor circuit or a CMO8 circuit.

Effects of the Invention The present invention uses the least significant bit (LSB) input data of the upper data of the Y decoder for the X decoder that uses the lower data of the input data, and provides two outputs of positive phase and reverse phase. When generating the X-decode signal and turning on or cutting off the basic circuit of the constant current source with a matrix structure, simultaneous changes in the X-decode output signal can be minimized in all cases where the data changes by one bit. By providing a decoding circuit section, digital noise can be significantly reduced, and by using two output X-decode output signals, one in positive phase and one in reverse phase with reversed polarity, it is possible to obtain the effect of canceling out switching noise. This makes it possible to realize an excellent D/A conversion circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram of a 6-bit D/A conversion circuit using a constant current source addition method with a matrix structure in an embodiment of the present invention, and FIG. 2 shows a basic constant current source circuit and decoded signal of the D/A conversion circuit of the present invention A schematic diagram showing the connection relationship between analog signals and latch clock signals. Figure 3 is a conventional 6-bit D/A conversion circuit diagram. Figure 4 is a circuit diagram of a basic constant current source circuit. Figure 5 is a 6-bit D/A conversion circuit diagram. The constant current source basic circuit of the /A conversion circuit is turned on in order from a completely cut-off state according to data (this is a diagram showing the order. 1...X decoder, 2...Y decoder , 10...Resistance, 116-131, 215-2
21...Transfer gate, 101,207
...3-person NAND gate, 102,206・
...2-person NAND gate, 103, 105, 2
03,205...Compound gate, 104,108
~115,132°134.136,138,140,
142,144°146.148,208~214,2
23,225°227,229,231,233,23
5,237...--I NV, 106,202,22
2,224°226.228,230,232,234
．． 236...2-person NOR gate, 107.2
01...3-man power NOR gate, 149,150
・・・・・・2-person AND gate, 133, 135, 1
37,139°141.143,145,147...
...Buffer gate, D o -D s...
6-bit data, φC...Clock pulse, φ
C・・・・・・φC anti-phase clock pulse, X O””
X7... Decoder output, xo-X7...
... Xo to X7 negative phase X decoder output, [Ypo,
Yso] ~ [Yp7. YS7]...Y decoder output, I OUT...Output current, I B
IAS...Bias current, Cv...Bias voltage. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1 Figure 2 Figure 3 Figure 4 Procedural amendment (Mutsu) 1985 5 Swords/20

Claims (1)

[Claims] Constant current source basic circuits are arranged in a matrix structure in the X-axis and Y-axis directions, and an
Two outputs of positive phase and negative phase are output from at least one output of the decoder circuit, and the same positive phase output and the negative phase output are alternately inputted to each column of the constant current source basic circuit, and 1. A digital-to-analog conversion circuit, wherein a decoding circuit that generates positive-phase and negative-phase output signals decodes all inputs corresponding to a lower bit group and the least significant bit input of an upper bit group.