CN104052490B - A kind of adjustable Segmented electrical flow pattern DAC-circuit - Google Patents
A kind of adjustable Segmented electrical flow pattern DAC-circuit Download PDFInfo
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Abstract
The invention discloses a kind of adjustable Segmented electrical flow pattern DAC-circuit, including input register, the first decoding circuit, the second decoding circuit, delay circuit, the first latch cicuit, the second latch cicuit, the 3rd latch cicuit, adjustable bias circuit and current source circuit；The output end d1 d3 of input register and the input of delay circuit are connected, and inputs of output end d4 d6 and the d7 d10 respectively with the second decoding circuit and the first decoding circuit is connected；The output end of first decoding circuit, the second decoding circuit and delay circuit is connected with the input of corresponding first latch cicuit, the second latch cicuit and the 3rd latch cicuit respectively；The input of the highest order current source circuit of current source circuit, interposition current source circuit and lowest order current source circuit is connected with the output end of adjustable bias circuit, its input is connected with the output end of corresponding first latch cicuit, the second latch cicuit and the 3rd latch cicuit respectively, and the present invention can reduce circuit complexity and power consumption.
Description
Technical field
The present invention relates to digital-to-analog circuit, more particularly to a kind of adjustable Segmented electrical flow pattern DAC-circuit.
Background technology
With various Audiotechnicas, computer technology, multimedia technology extensive use, promoted in Digital Signal Processing
Digital analog converter (DAC) develop rapidly.In following a very long time, high speed, broadband technology are by as communication system
Development trend.Due to leading position of the digital communication in Modern Communication System, DAC also turn into Modern Communication System in one not
The important module that can or lack.The quality of digital analog converter directly affects the performance of whole system, due to Digital Signal Processing
Develop rapidly, it is desirable to DAC has sufficiently high data processing speed and sufficiently high precision.
Current mode structure DAC is made up of analog portion and numerical portion.It is divided into binary type, temperature code type and sectional type
Structure.The advantage of binary code is to be conserved area without decoding logic, has the disadvantage there is big DNL errors, monotonicity
It cannot be guaranteed that and having a big conversion burr；Comparatively speaking, the advantage of thermometer-code is then that DNL errors are small, monotonicity is protected
Card, burr are small, have the disadvantage complexity, area and the power consumption of increased thermometer decoded circuit.
Existing biasing circuit power vd D, p-type MOS as shown in figure 4, p-type metal-oxide-semiconductor MP1_1 substrate is connected with source electrode
Pipe MP1_1 grid and drain electrode are connected with N-type metal-oxide-semiconductor MN6 drain electrode；N-type metal-oxide-semiconductor MN6_1 grid connects the defeated of amplifier OP_1
Go out, N-type metal-oxide-semiconductor MN6_1 source electrode is connected with the reverse input end of resistance Rc_1 one end and amplifier OP_1；Resistance Rc_1's is another
One end is connected with N-type metal-oxide-semiconductor MN1_1 drain electrode and resistance R1_1 one end；The output end of second reference voltage source and amplifier OP
Positive input be connected；N-type metal-oxide-semiconductor MN1_1 grid meets external control signal K1_1, for controlling whether MN1_1 turns on
(0 represents cut-off, and 1 represents conducting)；The resistance R1_1 other end and N-type metal-oxide-semiconductor MN2_1 drain electrode, N-type metal-oxide-semiconductor MN1_1 source
Pole is connected with resistance R2_1 one end, and N-type metal-oxide-semiconductor MN2_1 grid meets external control signal K2_1, for controlling MN2_1 to be
No conducting (0 represents cut-off, and 1 represents conducting)；The resistance R2_1 other end and N-type metal-oxide-semiconductor MN3_1 drain electrode, N-type metal-oxide-semiconductor
MN2_1 source electrode, resistance R3_1 one end are connected, and N-type metal-oxide-semiconductor MN3_1 grid meets external control signal K3_1, for controlling
Whether MN3_1 turns on (0 represents cut-off, and 1 represents conducting)；The resistance R3_1 other end and N-type metal-oxide-semiconductor MN4_1 drain electrode, N-type
Metal-oxide-semiconductor MN3_1 source electrode, resistance R4_1 one end are connected, and N-type metal-oxide-semiconductor MN4_1 grid meets external control signal K4_1, use
Whether turned on (0 represents cut-off, and 1 represents conducting) in control MN4_1；The resistance R4_1 other end and N-type metal-oxide-semiconductor MN5_1 leakage
Pole, N-type metal-oxide-semiconductor MN4_1 source electrode, resistance R5_1 one end are connected, and N-type metal-oxide-semiconductor MN5_1 grid connects external control signal
K5_1, for controlling whether MN5_1 turns on (0 represents cut-off, and 1 represents conducting)；The resistance R5_1 other end, N-type metal-oxide-semiconductor MN1_
1st, MN2_1, MN3_1, MN4_1, MN5_1, MN6_1 substrate, which are connected, is grounded GND.
The operation principle of circuit shown in Fig. 4 is：When MN1_1 is turned on, resistance R1_1 short circuits；When MN2_1 is turned on, resistance R2_1
Short circuit；When MN3_1 is turned on, resistance R3_1 short circuits；When MN4_1 is turned on, resistance R4_1 short circuits；When MN5_1 is turned on, resistance R5_1
Short circuit；Due in N trap CMOS technologies, the substrate of NMOS tube must be connected to ground potential, thus MN1_1, MN2_1, MN3_1,
MN4_1, MN5_1 substrate are grounded, and are introduced into body bias effect, the accuracy of load resistance is affected, are influenceed it to export
Bias current precision.
The content of the invention
In order to solve the above problems, it is an object of the invention to provide a kind of segmentation structure, it combines binary current
The characteristics of source type DAC and temperature code type DAC.Therefore using the combination of rational thermometer decoded and binary decoding, both may be used
To ensure the requirement of DNL errors and burr, less area and power consumption can be realized again.
The present invention is adopted the following technical scheme that：
A kind of adjustable Segmented electrical flow pattern DAC-circuit, including input register, the first decoding circuit, the second decoding circuit,
Delay circuit, the first latch cicuit, the second latch cicuit, the 3rd latch cicuit and current source circuit, in addition to adjustable bias electricity
Road；The adjustable Segmented electrical flow pattern DAC-circuit uses " 4+3+3 " segmental structure, wherein minimum 3 use binary coding,
Centre 3 and highest 4 use thermometer code coded system；The minimum three output end d1-d3 and delay circuit of input register
Input connection, the three output end d4-d6 in centre are connected with the input of the second decoding circuit, four output end d7- of highest
D10 is connected with the input of the first decoding circuit；The output end difference of first decoding circuit, the second decoding circuit and delay circuit
Connected with the input of corresponding first latch cicuit, the second latch cicuit and the 3rd latch cicuit；Current source circuit is included most
High side current source circuit, interposition current source circuit and lowest order current source circuit, and respectively with corresponding first latch cicuit,
The output end connection of second latch cicuit and the 3rd latch cicuit；The output end of adjustable bias circuit respectively with highest order current source
The input connection of circuit, interposition current source circuit and lowest order current source circuit；Highest order current source circuit, interposition electricity
Current source circuit is connected I with the output end of lowest order current source circuitOUT。
A kind of described adjustable Segmented electrical flow pattern DAC-circuit, in addition to the first clock circuit and second clock circuit, the
The output end of one clock circuit and the input of input register are connected, and the output end of second clock circuit is latched with first respectively
Circuit, the second latch cicuit, the input connection of the 3rd latch cicuit.
First decoding circuit is 4-15 decoding circuits, and the second decoding circuit is 3-7 decoding circuits.
The output signal of first latch cicuit is B11-B25 and B11_-B25_；The output of second latch cicuit
Signal is B4-B10 and B4_-B10_；The output signal of 3rd latch cicuit is B1-B3 and B1_-B3_.
The adjustable bias circuit includes p-type metal-oxide-semiconductor MP1, the first reference voltage source, operational amplifier OP, N-type metal-oxide-semiconductor
MN1, MN2, MN3, MN4, MN5, MN6, resistance Rc, R1, R2, R3, R4, R5；P-type metal-oxide-semiconductor MP1 substrate and source electrode is connected to
Power vd D, p-type metal-oxide-semiconductor MP1 grid and drain electrode and N-type metal-oxide-semiconductor MN6 drain electrode are connected in the output end of adjustable bias circuit
A1 nodes；N-type metal-oxide-semiconductor MN6 grid connects operational amplifier OP output, N-type metal-oxide-semiconductor MN6 source electrode and resistance Rc one end,
Amplifier OP reverse input end is connected, N-type metal-oxide-semiconductor MN6 Substrate ground GND；The resistance Rc other end respectively with resistance R1 mono-
End is connected with N type metal-oxide-semiconductors MN1 drain electrode；The output end of first reference voltage source is connected with amplifier OP positive input；N-type
Metal-oxide-semiconductor MN1 grid meets external control signal K1, for controlling whether MN1 turns on, N-type metal-oxide-semiconductor MN1 source electrode and substrate phase
Connection ground GND；The resistance R1 other end is connected with N-type metal-oxide-semiconductor MN2 drain electrode and resistance R2 one end, N-type metal-oxide-semiconductor MN2 grid
Pole outer signal K2, for controlling whether MN2 turns on, N-type metal-oxide-semiconductor MN2 source electrode is connected with substrate is grounded GND；Resistance R2's
The other end is connected with N-type metal-oxide-semiconductor MN3 drain electrode and resistance R3 one end, and N-type metal-oxide-semiconductor MN3 grid connects external control signal
K3, for controlling whether MN3 turns on, N-type metal-oxide-semiconductor MN3 source electrode is connected with substrate is grounded GND；The resistance R3 other end and N-type
Metal-oxide-semiconductor MN4 drain electrode and resistance R4 one end connection, N-type metal-oxide-semiconductor MN4 grid meets external control signal K4, for controlling
Whether MN4 turns on, and N-type metal-oxide-semiconductor MN4 source electrode is connected with substrate is grounded GND；The resistance R4 other end is with N-type metal-oxide-semiconductor MN5's
Drain electrode and resistance R5 forward end are connected, and N-type metal-oxide-semiconductor MN5 grid meets external control signal K5, for controlling whether MN5 leads
Logical, N-type metal-oxide-semiconductor MN5 source electrode is connected with substrate is grounded GND；Resistance R5 other end ground connection GND.
The highest order current source circuit is made up of 15 equal current sources of breadth length ratio, including p-type metal-oxide-semiconductor P11-
P25 and T21-T50；Interposition current source circuit is made up of seven equal current sources of breadth length ratio, including p-type metal-oxide-semiconductor P4-P10
And T7-T20；The current source that lowest order current source circuit is constantly doubled by three breadth length ratios is constituted, including p-type metal-oxide-semiconductor P1, P2,
P3、T1、T2、T3、T4、T5、T6；
P-type metal-oxide-semiconductor P11-P25, P4-P10, P1, P2, P3 source electrode and substrate are connected meets power vd D, p-type MOS together
Pipe P11-P25, P4-P10, P1, P2, P3 grid are connected connects the node of output terminals A 1 of adjustable bias circuit, p-type metal-oxide-semiconductor together
P25 drain electrode is connected together with p-type metal-oxide-semiconductor T49, T50 source electrode and T49, T50 substrate；P-type metal-oxide-semiconductor T50 grid connects
First latch cicuit corresponding output end B25, p-type metal-oxide-semiconductor T50 drain electrode meet the positive output end IOUTN of electric current；P-type metal-oxide-semiconductor
The drain electrode that T49 grid meets the first latch cicuit corresponding output end B25_, p-type metal-oxide-semiconductor T49 connects electric current negative sense output end
IOUTP；P-type metal-oxide-semiconductor P11 drain electrode and p-type metal-oxide-semiconductor T21, T22 source electrode and T21, T22 substrate are connected together；P-type
The drain electrode that metal-oxide-semiconductor T22 grid meets the first latch cicuit corresponding output end B11, p-type metal-oxide-semiconductor T22 connects the positive output end of electric current
IOUTN；P-type metal-oxide-semiconductor T21 grid meets the corresponding output end B11_ of the first latch cicuit, and p-type metal-oxide-semiconductor T21 drain electrode connects electric current
Negative sense output end IOUTP；Similarly connect P12~P25 and T23~T48；
P-type metal-oxide-semiconductor P10 drain electrode and p-type metal-oxide-semiconductor T19, T20 source electrode and T19, T20 substrate are connected together；P-type
The drain electrode that metal-oxide-semiconductor T20 grid meets the second latch cicuit corresponding output end B10, p-type metal-oxide-semiconductor T20 connects the positive output end of electric current
IOUTN；P-type metal-oxide-semiconductor T19 grid meets the corresponding output end B10_ of the second latch cicuit, and p-type metal-oxide-semiconductor T19 drain electrode connects electric current
Negative sense output end IOUTP；P-type metal-oxide-semiconductor P4 drain electrode and p-type metal-oxide-semiconductor T7, T8 source electrode and substrate are connected together；P-type
The drain electrode that metal-oxide-semiconductor T8 grid meets the second latch cicuit corresponding output end B4, p-type metal-oxide-semiconductor T8 connects the positive output end of electric current
IOUTN；P-type metal-oxide-semiconductor T7 grid connect the second latch cicuit corresponding output end B4_, p-type metal-oxide-semiconductor T7 drain electrode connect electric current bear
To output end IOUTP；Similarly connect P5-P9 and T9-T18；
P-type metal-oxide-semiconductor P3 drain electrode and p-type metal-oxide-semiconductor T5, T6 source electrode and substrate are connected together；P-type metal-oxide-semiconductor T6's
Grid meets the corresponding output end B3 of the 3rd latch cicuit, and p-type metal-oxide-semiconductor T6 drain electrode meets the positive output end IOUTN of electric current；P-type MOS
Pipe T5 grid meets the corresponding output end B3_ of the 3rd latch cicuit, and p-type metal-oxide-semiconductor T5 drain electrode connects electric current negative sense output end
IOUTP；P-type metal-oxide-semiconductor P2 drain electrode and p-type metal-oxide-semiconductor T3, T4 source electrode and substrate are connected together；P-type metal-oxide-semiconductor T4 grid
Pole meets the corresponding output end B2 of the 3rd latch cicuit, and p-type metal-oxide-semiconductor T4 drain electrode meets the positive output end IOUTN of electric current；P-type metal-oxide-semiconductor
T3 grid meets the corresponding output end B2_ of the 3rd latch cicuit, and p-type metal-oxide-semiconductor T3 drain electrode meets electric current negative sense output end IOUTP；P
Type metal-oxide-semiconductor P21 drain electrode and p-type metal-oxide-semiconductor T1, T2 source electrode and substrate are connected together；P-type metal-oxide-semiconductor T2 grid connects
Three latch cicuits corresponding output end B1, p-type metal-oxide-semiconductor T2 drain electrode meet the positive output end IOUTN of electric current；P-type metal-oxide-semiconductor T1 grid
Pole meets the corresponding output end B1_ of the 3rd latch cicuit, and p-type metal-oxide-semiconductor T1 drain electrode meets electric current negative sense output end IOUTP.
The highest order current source circuit is made up of breadth length ratio for M=64 current source；Interposition current source circuit is by width
The long current source composition than for M=8；Lowest order current source circuit is by current source that breadth length ratio is respectively M=1, M=2 and M=4
Composition.
Beneficial effects of the present invention：
(1) 4+3+3 segmental structures are used, reduce circuit complexity, reduce chip area and power consumption, while improving DAC
Performance.
(2) present invention using adjustable bias circuit switch control mode, by by the substrate of switching tube in circuit and source
Pole is connected, and eliminates influence of the body bias effect to reference current, can adjust DAC output current sizes.
Brief description of the drawings
Fig. 1 is a kind of Segmented electrical flow pattern DAC-circuit block diagram of embodiment of the present invention；
Fig. 2 is a kind of current source circuit figure of embodiment of the present invention；
Fig. 3 is a kind of adjustable bias circuit diagram of embodiment of the present invention；
Fig. 4 is a kind of existing adjustable bias circuit diagram.
Embodiment
The present invention is described in detail with specific embodiment below in conjunction with the accompanying drawings.
Embodiment one
As shown in figure 1, the present invention includes input register 1, decoding and delay circuit 2, latch cicuit 3, current source circuit
4th, adjustable bias circuit 5, the first clock circuit and second clock circuit；The decoding and delay circuit 2 include the first decoding electricity
Road, the second decoding circuit, delay circuit, the first decoding circuit use 4-15 decoding circuits, and the second decoding circuit is decoded using 3-7
Circuit.The latch cicuit 3 includes the first latch cicuit, the second latch cicuit and the 3rd latch cicuit；The current source circuit,
Including highest order current source circuit 4-1, interposition current source circuit 4-2 and lowest order current source circuit 4-3；10 adjustable point
Section current mode DAC-circuit uses " 4+3+3 " segmental structure, wherein minimum 3 use binary coding, middle 3 and highest 4
Using thermometer code coded system；External data D1-D10 is input to input register 1, minimum three output of input register 1
The input of d1-d3 and delay circuit is held to connect, the three output end d4-d6 in centre are connected with the input of the second decoding circuit,
Four output end d7-d10 of highest are connected with the input of the first decoding circuit；First decoding circuit, the second decoding circuit and prolong
When circuit output end connect respectively with the input of corresponding first latch cicuit, the second latch cicuit and the 3rd latch cicuit
Connect；Highest order current source circuit 4-1, interposition current source circuit 4-2 and lowest order current source circuit 4-3 are respectively with corresponding
The output end connection of one latch cicuit, the second latch cicuit and the 3rd latch cicuit；The output end of adjustable bias circuit 5 respectively with
Highest order current source circuit 4-1, interposition current source circuit 4-2 and lowest order current source circuit 4-3 input connection；First
The output end of clock circuit and the input of input register are connected, and the output end of second clock circuit latches electricity with first respectively
Road, the second latch cicuit, the input connection of the 3rd latch cicuit, for causing in 10 signal Synchronization Control current source circuits
Switching tube；Highest order current source circuit 4-1, interposition current source circuit 4-2 and lowest order current source circuit 4-3 output end
Be connected current output terminal IOUT。
The operation principle of circuit diagram shown in Fig. 1 is：Minimum 3 data-signal D1-D3 are latched by delay circuit, the 3rd
Circuit output switch controlling signal B1-B3 and B1_-B3_ gives lowest order current source circuit 4-3, for controlling lowest order current source
The conducting and shut-off of circuit 4-3 switching tubes.The 3 data-signal D4-D6 in centre are 3-7 decoding circuits by the second decoding circuit
Output end is transferred to the second latch cicuit, exports seven way switch control signal B4-B10 and B4_-B10_ and gives interposition current source electricity
Road 4-2, for controlling the conducting and shut-off of interposition current source circuit 4-2 switching tubes；4 data-signal D7-D10 of highest pass through
Input register is 4-15 decoding circuits into the first decoding circuit, passes through the first decoding circuit and the first latch cicuit output ten
Five way switch control signals B11-B25, B11_-B25_ give highest order current source circuit 4-1, for controlling highest order current source electricity
The conducting and shut-off of road 4-1 switching tubes.The corresponding electric current in Zhong Ge roads of switch controlled current source circuit 4 be output to IOUTN or
Person IOUTP, according to principle of stacking, the electric current for switching closure branch road is added and is output to IOUTN or IOUTP.Adjustable bias electricity
Road 5 provides reference voltage for whole adjustable Segmented electrical flow pattern DAC-circuit, passes through a series of switch controlled adjustable bias circuits
5 load resistance size, can adjust Segmented electrical flow pattern DAC bias current, so as to control the electric current of each segmented current
Size.
As shown in Fig. 2 highest order current source circuit 4-1 is made up of 15 breadth length ratios for M=64 current source, including P
Type metal-oxide-semiconductor P11-P25 and T21-T50；Interposition current source circuit 4-2 is made up of seven breadth length ratios for M=8 current source, is wrapped
Include p-type metal-oxide-semiconductor P4-P10 and T7-T20；Lowest order current source circuit 4-3 is respectively M=1, M=2 and M=4 by three breadth length ratios
Current source composition, including p-type metal-oxide-semiconductor P1, P2, P3, T1, T2, T3, T4, T5, T6；
P-type metal-oxide-semiconductor P11-P25, P4-P10, P1, P2, P3 source electrode and substrate are connected meets power vd D, p-type MOS together
Pipe P11-P25, P4-P10, P1, P2, P3 grid are connected connects the node of output terminals A 1 of adjustable bias circuit, p-type metal-oxide-semiconductor together
P25 drain electrode is connected together with p-type metal-oxide-semiconductor T49, T50 source electrode and T49, T50 substrate；P-type metal-oxide-semiconductor T50 grid connects
B25, p-type metal-oxide-semiconductor T50 drain electrode meet the positive output end IOUTN of electric current；P-type metal-oxide-semiconductor T49 grid meets B25_, p-type metal-oxide-semiconductor
T49 drain electrode meets electric current negative sense output end IOUTP；P-type metal-oxide-semiconductor P11 drain electrode and p-type metal-oxide-semiconductor T21, T22 source electrode and
T21, T22 substrate are connected together；P-type metal-oxide-semiconductor T22 grid meets B11, and p-type metal-oxide-semiconductor T22 drain electrode connects electric current forward direction output
Hold IOUTN；P-type metal-oxide-semiconductor T21 grid meets B11_, and p-type metal-oxide-semiconductor T21 drain electrode meets electric current negative sense output end IOUTP；Similarly connect
Meet P12~P25 and T23~T48；
P-type metal-oxide-semiconductor P10 drain electrode and p-type metal-oxide-semiconductor T19, T20 source electrode and T19, T20 substrate are connected together；P-type
Metal-oxide-semiconductor T20 grid meets B10, and p-type metal-oxide-semiconductor T20 drain electrode meets the positive output end IOUTN of electric current；P-type metal-oxide-semiconductor T19 grid
B10_ is met, p-type metal-oxide-semiconductor T19 drain electrode meets electric current negative sense output end IOUTP；P-type metal-oxide-semiconductor P4 drain electrode and p-type metal-oxide-semiconductor T7, T8
Source electrode and substrate be connected together；P-type metal-oxide-semiconductor T8 grid meets B4, and p-type metal-oxide-semiconductor T8 drain electrode connects electric current forward direction output
Hold IOUTN；P-type metal-oxide-semiconductor T7 grid meets B4_, and p-type metal-oxide-semiconductor T7 drain electrode meets electric current negative sense output end IOUTP；Similarly connect
P5-P9 and T9-T18；
P-type metal-oxide-semiconductor P3 drain electrode and p-type metal-oxide-semiconductor T5, T6 source electrode and substrate are connected together；P-type metal-oxide-semiconductor T6's
Grid meets B3, and p-type metal-oxide-semiconductor T6 drain electrode meets the positive output end IOUTN of electric current；P-type metal-oxide-semiconductor T5 grid meets B3_, p-type metal-oxide-semiconductor
T5 drain electrode meets electric current negative sense output end IOUTP；P-type metal-oxide-semiconductor P2 drain electrode and p-type metal-oxide-semiconductor T3, T4 source electrode and substrate phase
Connect together；P-type metal-oxide-semiconductor T4 grid meets B2, and p-type metal-oxide-semiconductor T4 drain electrode meets the positive output end IOUTN of electric current；P-type metal-oxide-semiconductor
T3 grid meets B2_, and p-type metal-oxide-semiconductor T3 drain electrode meets electric current negative sense output end IOUTP；P-type metal-oxide-semiconductor P21 drain electrode and p-type MOS
Pipe T1, T2 source electrode and substrate are connected together；P-type metal-oxide-semiconductor T2 grid meets B1, and p-type metal-oxide-semiconductor T2 drain electrode is connecing electric current just
To output end IOUTN；P-type metal-oxide-semiconductor T1 grid meets B1_, and p-type metal-oxide-semiconductor T1 drain electrode meets electric current negative sense output end IOUTP.
As shown in figure 3, adjustable bias circuit 5 includes p-type metal-oxide-semiconductor MP1, the first reference voltage source, operational amplifier OP, N
Type metal-oxide-semiconductor MN1, MN2, MN3, MN4, MN5, MN6, resistance Rc, R1, R2, R3, R4, R5；P-type metal-oxide-semiconductor MP1 substrate and source electrode
Power vd D is connected to, p-type metal-oxide-semiconductor MP1 grid and drain electrode and N-type metal-oxide-semiconductor MN6 drain electrode are connected in adjustable bias circuit
The node of output terminals A 1；N-type metal-oxide-semiconductor MN6 grid connects operational amplifier OP output, N-type metal-oxide-semiconductor MN6 source electrode and resistance
Rc one end, amplifier OP reverse input end are connected, N-type metal-oxide-semiconductor MN6 Substrate ground GND；The resistance Rc other end respectively with
The drain electrode of resistance R1 one end and N-type metal-oxide-semiconductor MN1 is connected；The output end of first reference voltage source and amplifier OP positive input
It is connected；N-type metal-oxide-semiconductor MN1 grid meets external control signal K1, for controlling whether MN1 turns on, N-type metal-oxide-semiconductor MN1 source electrode
Be connected ground connection GND with substrate；The resistance R1 other end is connected with N-type metal-oxide-semiconductor MN2 drain electrode and resistance R2 one end, N-type MOS
Pipe MN2 grid meets external control signal K2, for controlling whether MN2 turns on, and N-type metal-oxide-semiconductor MN2 source electrode is connected with substrate
Ground GND；The resistance R2 other end is connected with N-type metal-oxide-semiconductor MN3 drain electrode and resistance R3 one end, and N-type metal-oxide-semiconductor MN3 grid connects
External control signal K3, for controlling whether MN3 turns on, N-type metal-oxide-semiconductor MN3 source electrode is connected with substrate is grounded GND；Resistance R3
The other end be connected with N-type metal-oxide-semiconductor MN4 drain electrode and resistance R4 one end, N-type metal-oxide-semiconductor MN4 grid connects external control signal
K4, for controlling whether MN4 turns on, N-type metal-oxide-semiconductor MN4 source electrode is connected with substrate is grounded GND；The resistance R4 other end and N-type
Metal-oxide-semiconductor MN5 drain electrode and resistance R5 forward end connection, N-type metal-oxide-semiconductor MN5 grid meets external control signal K5, for controlling
Whether MN5 turns on, and N-type metal-oxide-semiconductor MN5 source electrode is connected with substrate is grounded GND；Resistance R5 other end ground connection GND.Adjustable bias
Circuit 5 can eliminate influence of the body bias effect to adjustable bias circuit reference electric current, so as to accurate control Segmented electrical flow pattern
DAC output current scope sizes.
The course of work of circuit shown in Fig. 3 is as follows：
Amplifier OP and N-type metal-oxide-semiconductor MN6 and resistance Rc, R1-R5 constitute backfeed loop, N-type metal-oxide-semiconductor MN6 source voltages etc.
In the output voltage Vref of the first reference voltage source, so as to be to flow through resistance branch the voltage conversion of the first reference voltage source
Electric current.By controlling switch pipe MN1-MN5 turn-on and turn-off, different output reference electric current Iref can be obtained, wherein：
When only MN1 is turned on, load resistance R sizes are Rc；When only MN2 is turned on, load resistance R sizes are Rc+
R1；When only MN3 is turned on, load resistance R sizes are Rc+R1+R2；When only MN4 is turned on, load resistance R sizes are Rc+
R1+R2+R3；When only MN5 is turned on, load resistance R sizes are Rc+R1+R2+R3+R4；When MN1-MN5 is fully closed disconnected, load
Resistance R sizes are Rc+R1+R2+R3+R4+R5.
Adjustable bias circuit shown in Fig. 3 is compared with existing adjustable bias circuit in Fig. 4, switching tube MN1_1-MN5_1 in Fig. 4
Substrate connect with ground so that lining bias-voltage VBS≤ 0, thus body bias effect can be produced.In Fig. 3 switching tube MN1-MN5 substrates with
Source electrode connects, therefore VBS=0, body bias effect will not be produced.Wherein metal-oxide-semiconductor threshold voltage expression formula is：VTH0(i.e. threshold voltage) is represented when the electron concentration at interface is equal to many of substrate
Grid voltage during sub- concentration, φFFermi potential is represented, γ represents body-effect coefficient, and metal-oxide-semiconductor will be equivalent to a resistance when turning on, its
Expression formula is：In formula：μnIt is electron mobility, Cox is the gate oxide capacitance of unit area,
VGSIt is gate source voltage, due to VBS≠ 0, it will change the value of threshold voltage, so as to influence its equivalent resistance.Such as work as MN1-
When MN5, MN1_1-MN5_1 are turned on entirely, ideally, its equivalent resistance is 0, therefore Fig. 3 and Fig. 4 effective resistance is RC
And RC_ 1, but due to the influence of body bias effect so that MN1_1-MN5_1 threshold voltage can all be significantly greater than MN1, then be less than
Resistance when MN1_1 is turned on can be significantly greater than resistance during MN1 conductings, therefore larger to actually active resistance value influences, from
And influence reference current Iref value.So the adjustable bias circuit I ref of the present invention existing adjustable bias circuit of ratio of precision
Iref precision will height.
The present invention is not limited to the above-described embodiments, every a kind of using above-mentioned no matter its way of realization makees any change
Switch the adjustable bias current of control mode or (binary system is compiled using 4bit (temperature code)+3bit (temperature code)+3bit
Code) 10bitDAC structures, all should fall within the scope of the present application.
Claims (6)
1. a kind of adjustable Segmented electrical flow pattern DAC-circuit, including input register, the first decoding circuit, the second decoding circuit, prolong
When circuit, the first latch cicuit, the second latch cicuit, the 3rd latch cicuit and current source circuit, it is characterized in that：Also include adjustable
Biasing circuit；The adjustable Segmented electrical flow pattern DAC-circuit uses " 4+3+3 " segmental structure, wherein minimum 3 use binary system
Coding, centre 3 and highest 4 use thermometer code coded system；Minimum three output end d1-d3 of input register and delay
The input connection of circuit, the three output end d4-d6 in centre are connected with the input of the second decoding circuit, four output ends of highest
D7-d10 is connected with the input of the first decoding circuit；The output end of first decoding circuit, the second decoding circuit and delay circuit
Connected respectively with the input of corresponding first latch cicuit, the second latch cicuit and the 3rd latch cicuit；Current source circuit bag
Highest order current source circuit, interposition current source circuit and lowest order current source circuit are included, and is latched respectively with corresponding first
The output end connection of circuit, the second latch cicuit and the 3rd latch cicuit；The output end of adjustable bias circuit respectively with highest order
The input connection of current source circuit, interposition current source circuit and lowest order current source circuit；Highest order current source circuit, in
Meta current source circuit is connected current output terminal I with the output end of lowest order current source circuitOUT；The adjustable bias circuit
Including p-type metal-oxide-semiconductor MP1, the first reference voltage source, operational amplifier OP, N-type metal-oxide-semiconductor MN1, MN2, MN3, MN4, MN5, MN6,
Resistance Rc, R1, R2, R3, R4, R5；P-type metal-oxide-semiconductor MP1 substrate and source electrode is connected to power vd D, p-type metal-oxide-semiconductor MP1 grid
Pole and drain electrode and N-type metal-oxide-semiconductor MN6 drain electrode are connected in the node of output terminals A 1 of adjustable bias circuit；N-type metal-oxide-semiconductor MN6 grid
Operational amplifier OP output is connect, N-type metal-oxide-semiconductor MN6 source electrode is connected with resistance Rc one end, amplifier OP reverse input end, N
Type metal-oxide-semiconductor MN6 Substrate ground GND；The resistance Rc other end respectively with resistance R1 one end and N-type metal-oxide-semiconductor MN1 drain electrode phase
Even；The output end of first reference voltage source is connected with amplifier OP positive input；N-type metal-oxide-semiconductor MN1 grid connects outside control
Signal K1, for controlling whether MN1 turns on, N-type metal-oxide-semiconductor MN1 source electrode is connected with substrate is grounded GND；The resistance R1 other end
One end of drain electrode and resistance R2 with N-type metal-oxide-semiconductor MN2 is connected, N-type metal-oxide-semiconductor MN2 grid outer signal K2, for controlling MN2
Whether turn on, N-type metal-oxide-semiconductor MN2 source electrode is connected with substrate is grounded GND；The resistance R2 other end and N-type metal-oxide-semiconductor MN3 drain electrode
Connected with resistance R3 one end, N-type metal-oxide-semiconductor MN3 grid meets external control signal K3, for controlling whether MN3 turns on, N-type
Metal-oxide-semiconductor MN3 source electrode is connected with substrate is grounded GND；The resistance R3 other end and N-type metal-oxide-semiconductor MN4 drain electrode and the one of resistance R4
End connection, N-type metal-oxide-semiconductor MN4 grid meets external control signal K4, for controlling whether MN4 turns on, N-type metal-oxide-semiconductor MN4 source
Pole is connected with substrate is grounded GND；The resistance R4 other end is connected with N-type metal-oxide-semiconductor MN5 drain electrode and resistance R5 forward end, N-type
Metal-oxide-semiconductor MN5 grid meets external control signal K5, for controlling whether MN5 turns on, N-type metal-oxide-semiconductor MN5 source electrode and substrate phase
Connection ground GND；Resistance R5 other end ground connection GND.
2. a kind of adjustable Segmented electrical flow pattern DAC-circuit according to claim 1, it is characterized in that：Also include the first clock
Circuit and second clock circuit, the output end of the first clock circuit and the input of input register are connected, second clock circuit
Input of the output end respectively with the first latch cicuit, the second latch cicuit, the 3rd latch cicuit be connected.
3. a kind of adjustable Segmented electrical flow pattern DAC-circuit according to claim 1, it is characterized in that：The first decoding electricity
Road is 4-15 decoding circuits, and the second decoding circuit is 3-7 decoding circuits.
4. a kind of adjustable Segmented electrical flow pattern DAC-circuit according to claim 1, it is characterized in that：Described first latches electricity
The output signal on road is B11-B25 and B11_-B25_；The output signal of second latch cicuit is B4-B10 and B4_-
B10_；The output signal of 3rd latch cicuit is B1-B3 and B1_-B3_.
5. a kind of adjustable Segmented electrical flow pattern DAC-circuit according to claim 3, it is characterized in that：The highest order electric current
Source circuit is made up of 15 equal current sources of breadth length ratio, including p-type metal-oxide-semiconductor P11-P25 and T21-T50；Interposition electric current
Source circuit is made up of seven equal current sources of breadth length ratio, including p-type metal-oxide-semiconductor P4-P10 and T7-T20；Lowest order current source electricity
The current source composition that three breadth length ratios of route constantly double, including p-type metal-oxide-semiconductor P1, P2, P3, T1, T2, T3, T4, T5, T6；
P-type metal-oxide-semiconductor P11-P25, P4-P10, P1, P2, P3 source electrode and substrate are connected meets power vd D, p-type metal-oxide-semiconductor together
P11-P25, P4-P10, P1, P2, P3 grid are connected connects the node of output terminals A 1 of adjustable bias circuit, p-type metal-oxide-semiconductor P25 together
Drain electrode be connected together with p-type metal-oxide-semiconductor T49, T50 source electrode and T49, T50 substrate；P-type metal-oxide-semiconductor T50 grid connects
One latch cicuit corresponding output end B25, p-type metal-oxide-semiconductor T50 drain electrode meet the positive output end IOUTN of electric current；P-type metal-oxide-semiconductor T49
Grid connect the first latch cicuit corresponding output end B25_, p-type metal-oxide-semiconductor T49 drain electrode and meet electric current negative sense output end IOUTP；P
Type metal-oxide-semiconductor P11 drain electrode and p-type metal-oxide-semiconductor T21, T22 source electrode and T21, T22 substrate are connected together；P-type metal-oxide-semiconductor T22
Grid connect the first latch cicuit corresponding output end B11, p-type metal-oxide-semiconductor T22 drain electrode and meet the positive output end IOUTN of electric current；P
Type metal-oxide-semiconductor T21 grid connects the first latch cicuit corresponding output end B11_, p-type metal-oxide-semiconductor T21 drain electrode, and to connect electric current negative sense defeated
Go out to hold IOUTP；Similarly connect P12~P24 and T23~T48；
P-type metal-oxide-semiconductor P10 drain electrode and p-type metal-oxide-semiconductor T19, T20 source electrode and T19, T20 substrate are connected together；P-type MOS
The drain electrode that pipe T20 grid meets the second latch cicuit corresponding output end B10, p-type metal-oxide-semiconductor T20 connects the positive output end of electric current
IOUTN；P-type metal-oxide-semiconductor T19 grid meets the corresponding output end B10_ of the second latch cicuit, and p-type metal-oxide-semiconductor T19 drain electrode connects electric current
Negative sense output end IOUTP；P-type metal-oxide-semiconductor P4 drain electrode and p-type metal-oxide-semiconductor T7, T8 source electrode and substrate are connected together；P-type
The drain electrode that metal-oxide-semiconductor T8 grid meets the second latch cicuit corresponding output end B4, p-type metal-oxide-semiconductor T8 connects the positive output end of electric current
IOUTN；P-type metal-oxide-semiconductor T7 grid connect the second latch cicuit corresponding output end B4_, p-type metal-oxide-semiconductor T7 drain electrode connect electric current bear
To output end IOUTP；Similarly connect P5-P9 and T9-T18；
P-type metal-oxide-semiconductor P3 drain electrode and p-type metal-oxide-semiconductor T5, T6 source electrode and substrate are connected together；P-type metal-oxide-semiconductor T6 grid
The corresponding output end B3 of the 3rd latch cicuit is met, p-type metal-oxide-semiconductor T6 drain electrode meets the positive output end IOUTN of electric current；P-type metal-oxide-semiconductor T5
Grid meet the corresponding output end B3_ of the 3rd latch cicuit, p-type metal-oxide-semiconductor T5 drain electrode meets electric current negative sense output end IOUTP；P-type
Metal-oxide-semiconductor P2 drain electrode and p-type metal-oxide-semiconductor T3, T4 source electrode and substrate are connected together；P-type metal-oxide-semiconductor T4 grid connects the 3rd lock
The drain electrode for depositing circuit corresponding output end B2, p-type metal-oxide-semiconductor T4 meets the positive output end IOUTN of electric current；P-type metal-oxide-semiconductor T3 grid connects
The corresponding output end B2_ of 3rd latch cicuit, p-type metal-oxide-semiconductor T3 drain electrode meet electric current negative sense output end IOUTP；P-type metal-oxide-semiconductor P21
Drain electrode and p-type metal-oxide-semiconductor T1, T2 source electrode and substrate be connected together；P-type metal-oxide-semiconductor T2 grid connects the 3rd latch cicuit
Corresponding output end B1, p-type metal-oxide-semiconductor T2 drain electrode meet the positive output end IOUTN of electric current；P-type metal-oxide-semiconductor T1 grid connects the 3rd lock
The drain electrode for depositing circuit corresponding output end B1_, p-type metal-oxide-semiconductor T1 meets electric current negative sense output end IOUTP.
6. a kind of adjustable Segmented electrical flow pattern DAC-circuit according to claim 5, it is characterized in that：The highest order electric current
Source circuit is made up of breadth length ratio for M=64 current source；Interposition current source circuit is made up of breadth length ratio for M=8 current source；
Lowest order current source circuit is made up of the current source that breadth length ratio is respectively M=1, M=2 and M=4.
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