CN118041367A - Ternary decoder - Google Patents
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- CN118041367A CN118041367A CN202410436758.3A CN202410436758A CN118041367A CN 118041367 A CN118041367 A CN 118041367A CN 202410436758 A CN202410436758 A CN 202410436758A CN 118041367 A CN118041367 A CN 118041367A
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Abstract
The invention relates to a ternary decoder, and belongs to the technical field of semiconductors. The ternary decoder comprises N decoder input ends and N 3 decoder output ends, wherein the decoder input ends are used for inputting ternary input signals, and the ternary decoder comprises three states of high, low and suspension; each decoder input end is connected with a corresponding input end logic circuit, each input end logic circuit is provided with three paths of high-low level signal output ends, each path of high-low level signal output end is connected with three paths of corresponding decoder output ends, and the corresponding decoder output end signals are generated according to different ternary input signals, so that more output signals can be obtained under the condition of reducing the input ends.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to the technical field of logic circuits, and specifically relates to a ternary decoder.
Background
A logic circuit with a decoding function is called a decoder, which is capable of converting an input signal (code) with a specific meaning into a corresponding output signal.
The most common decoder in the market at present is a binary decoder, and the principle is shown in fig. 1, where each binary code corresponds to one output terminal, that is, only one output terminal is an active level, and the other outputs are inactive levels. The n-bit binary code is translated into 2 n high-low level signals, called an n-line-2 n line decoder. If n=3, 2 n =8 high and low level signals can be interpreted, and the decoder is called a 3-line-8-line decoder.
However, the binary decoder has the problem of fewer output terminals, and if the output terminals need to be increased, the input terminals need to be correspondingly increased, which increases the bit number of the input signals of the binary decoder, so that the binary decoder is not easy to apply.
How to provide a decoder that can obtain more output signals without increasing or even decreasing input terminals is a problem to be solved in the art.
Disclosure of Invention
It is an object of the present invention to overcome the above-mentioned drawbacks of the prior art and to provide a ternary decoder which allows to obtain more output signals with reduced input.
In order to achieve the above object, a ternary decoder of the present invention has the following constitution:
The ternary decoder comprises N decoder input ends, N 3 decoder output ends, an enabling end E, a positive power supply VDD and a negative power supply GND, wherein N is a natural number which is more than or equal to 1; the input end of the decoder inputs a ternary input signal, and the ternary input signal comprises three states of high, low and suspended;
Each decoder input end is connected with a corresponding input end logic circuit, each input end logic circuit is connected with a positive power supply VDD and a negative power supply GND, each input end logic circuit is provided with three paths of high-low level signal output ends, each path of high-low level signal output end is connected with three paths of corresponding decoder output ends, and each decoder output end is connected with an enabling end E for generating corresponding decoder output end signals according to different ternary input signals.
In the ternary decoder, an input end of the input end logic circuit is connected with a positive power supply VDD, a negative power supply GND or suspended according to different input signals, an input voltage V 0 of which the input end is connected with positive input ends of two comparators OP1 and OP2 through an input resistor R 0, an input voltage V 0 is also connected with the positive power supply VDD through a voltage dividing resistor R 2, an input voltage V 0 is also connected with a negative power supply GND through a voltage dividing resistor R 3, the positive power supply VDD and the negative power supply GND are also sequentially connected with a voltage dividing resistor R 4、R5、R6、R7, a reverse input end of the comparator OP1 is connected between the voltage dividing resistors R 4、R5, a reverse input end of the comparator OP2 is connected between the voltage dividing resistors R 6、R7, the resistance values of the voltage dividing resistors R 2~R7 are the same, one path of output ends of the comparator OP1 is connected with input ends of a first AND gate and a third AND gate through a NOT gate, the other path of the output ends of the comparator OP1 is connected with the input ends of the second AND gate through the first path of the comparator and the other input ends of the AND gate 2; the output ends of the first, second and third AND gates are the three high-low level signal output ends B 0、B1、B2.
In the ternary decoder, the resistance of the input resistor R 0 is 50Ω, and the resistance of the voltage dividing resistor R 2~R7 is 500kΩ.
The ternary decoder further comprises N 3 output end AND gates, the output end of each output end AND gate is the decoder output end Y, each high-low level signal output end is respectively connected with the input ends of the output end AND gates, and the enabling end E is connected with the input end of each output end AND gate.
The ternary decoder comprises N decoder input ends and N 3 decoder output ends, wherein the decoder input ends are used for inputting ternary input signals, and the ternary decoder comprises three states of high, low and suspension; the input end of each decoder is connected with a corresponding input end logic circuit, each input end logic circuit is provided with three paths of high-low level signal output ends, each path of high-low level signal output ends is connected with the corresponding three paths of decoder output ends, and the corresponding decoder output end signals are generated according to different ternary input signals, so that more output signals can be obtained under the condition of reducing the input ends.
Drawings
FIG. 1 is a schematic diagram of a prior art binary decoder;
FIG. 2 is a schematic diagram of a 2-line-9-line ternary decoder according to the present invention;
FIG. 3 is a schematic diagram of a portion of the input logic circuit of the ternary decoder of the present invention;
Fig. 4 is a schematic diagram of a 2-wire-9-wire ternary decoder logic circuit according to the present invention.
Detailed Description
In order to make the technical contents of the present invention more clearly understood, the following examples are specifically described.
In one embodiment, the ternary decoder of the present invention includes N decoder input terminals, N 3 decoder output terminals, N being a natural number greater than or equal to 1, and an enable terminal E, and a positive power supply VDD, a negative power supply GND; the input end of the decoder inputs a ternary input signal which comprises three states of high, low and suspended.
Taking a 2-line-9-line ternary decoder with 2 decoder input ends as an example, as shown in fig. 2, each decoder input end is connected with a corresponding input end logic circuit, each input end logic circuit is connected with the positive power supply VDD and the negative power supply GND, each input end logic circuit is provided with three paths of high-low level signal output ends, each path of high-low level signal output ends is connected with three paths of corresponding decoder output ends, and each decoder output end is connected with the enabling end E, so as to generate corresponding decoder output end signals according to different ternary input signals.
In a preferred embodiment, as shown in fig. 3, in the input logic circuit, an input end is connected to a positive power supply VDD, a negative power supply GND or suspended according to different input signals, an input voltage V 0 of an input end passing through an input resistor R 0 is connected to positive input ends of two comparators OP1 and OP2, a resistance value of the input resistor R 0 is 50Ω, an input voltage V 0 is also connected to the positive power supply VDD through a voltage dividing resistor R 2, an input voltage V 0 is also connected to a negative power supply GND through a voltage dividing resistor R 3, the positive power supply VDD and the negative power supply GND are also sequentially connected with a voltage dividing resistor R 4、R5、R6、R7, a reverse input end of the comparator OP1 is connected between the voltage dividing resistors R 4、R5, a reverse input end of the comparator OP2 is connected between the voltage dividing resistors R 6、R7, resistance values of the voltage dividing resistors R 2~R7 are the same, one output end of the comparator OP1 is connected to input ends of a first and a third and gate through a non-gate, and the other output end of the comparator OP1 is connected to the first output end of the second and the third gate 2; the output ends of the first, second and third AND gates are the three high-low level signal output ends B 0、B1、B2.
In a more preferred embodiment, as shown in fig. 4, the circuit includes N 3 output and gates, the output end of each output and gate is the decoder output end Y, each of the high-low level signal output ends is connected to the input end of each output and gate, and the enable end E is connected to the input end of each output and gate.
In practical applications, if the input signal is a ternary code, that is, only one output terminal is an active level and the other outputs are inactive levels corresponding to each ternary code. The n-bit ternary code is translated into 3 n high-low level signals, and if n=2, 3 n =9 high-low level signals can be translated, compared with the binary decoder, the ternary decoder of the invention can use fewer input ends to correspond to more output ends, and realize the 2-line-9-line ternary decoder.
Compared with the 2-line-4-line binary decoder, the ternary decoder of the invention, taking the 2-line-9-line ternary decoder shown in fig. 2 as an example, can have more combination states under the same bit number of input, and can translate more output signals. The first diagram is a block diagram of a 2-line-9-line ternary decoder of the present invention, which has two inputs a 0、A1 (not only high and low states, but also floating states), 9 outputs Y 0~Y8 (active high), an enable E, and a positive power supply VDD and a negative power supply GND.
Fig. 3 is a logic circuit diagram (part of two inputs a 0、A1) of the present invention, R 0、R1 having a resistance of 50Ω and R 2、R3、R4……R13 having a resistance of 500kΩ.
Since the resistance values of R 4、R5、R6 and R 7 are equal, the voltage of VDD is equally split over these four resistors, i.e. V 2=3/4VDD,V3 =1/4 VDD. When a 0 is connected to GND, i.e. the input is low, then V 0 is close to but slightly higher than GND, V 2＞V3＞V0, and the outputs of comparators OP1 and OP2 are both low, then B 0 is high, and B 1 and B 2 are low; when a 0 is terminated by VDD, i.e., the input is high, then V 0 is close to but slightly below VDD, V 0＞V2＞V3, and the outputs of comparators OP1 and OP2 are both high, then B 1 is high, and B 0 and B 2 are low; when the terminal a 0 is not connected, i.e. the input is in a suspended state, the voltage of VDD is equally divided over the resistors R 2 and R 3, then the output terminal of V 0=1/2VDD,V2＞V0＞V3, OP1 is low, the output terminal of OP2 is high, at this time, B 2 is high, and B 0 and B 1 are low.
The resistance values of R 10、R11、R12 and R 13 are equal, V 4=3/4VDD,V5 =1/4 VDD. When a 1 is connected to GND, i.e., the input is low, the outputs of comparators OP3 and OP4 are both low, at which time C 0 is high, and C 1 and C 2 are low; when a 1 is terminated by VDD, i.e., the input is high, the outputs of comparators OP3 and OP4 are both high, at which point C 1 is high, and C 0 and C 2 are low; when the terminal a 1 is not connected, i.e. the input is in a suspended state, the output terminal of OP3 is at a low level, the output terminal of OP4 is at a high level, at this time, C 2 is at a high level, and C 0 and C 1 are at low levels.
The overall logic circuit diagram of the 2-line-9-line ternary decoder of the present invention is shown in fig. 4, the function table is shown in the following table 1, and "0" represents a low level. "1" indicates a high level, and "2" indicates a suspended state. The enable signal is active low and when e=1, the output is inactive logic level (i.e., low) regardless of the value of the input signal. When e=0, the output terminal Y x(x=3A1+A0 corresponding to the a 1A0 input code) is high, and the remaining output terminals are low.
| Input device | Input device | Input device | Output of | Output of | Output of | Output of | Output of | Output of | Output of | Output of | Output of |
| E | A1 | A0 | Y0 | Y1 | Y2 | Y3 | Y4 | Y5 | Y6 | Y7 | Y8 |
| 1 | × | × | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| 0 | 1 | 2 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 0 | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| 0 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Table 1 functional table
Further, when the input ports are increased from two to three, 27 high-low level signals can be decoded, and a 3-line-27-line ternary decoder is realized. The number of input ports and output ports is not limited in the present invention.
Compared with a binary decoder, the input signal of the ternary decoder has not only a high state and a low state, but also a floating state. Therefore, more combination states can be obtained under the same bit number input, and more output signals can be translated.
The ternary decoder adopting the invention comprises N decoder input ends and N 3 decoder output ends, wherein the decoder input ends are used for inputting ternary input signals, and the ternary decoder comprises three states of high, low and suspension; the input end of each decoder is connected with a corresponding input end logic circuit, each input end logic circuit is provided with three paths of high-low level signal output ends, each path of high-low level signal output ends is connected with the corresponding three paths of decoder output ends, and the corresponding decoder output end signals are generated according to different ternary input signals, so that more output signals can be obtained under the condition of reducing the input ends.
In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent that various modifications and variations can be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (4)
1. The ternary decoder is characterized by comprising N decoder input ends, N 3 decoder output ends, an enabling end E, a positive power supply VDD and a negative power supply GND, wherein N is a natural number greater than or equal to 1; the input end of the decoder inputs a ternary input signal, and the ternary input signal comprises three states of high, low and suspended;
Each decoder input end is connected with a corresponding input end logic circuit, each input end logic circuit is connected with a positive power supply VDD and a negative power supply GND, each input end logic circuit is provided with three paths of high-low level signal output ends, each path of high-low level signal output end is connected with three paths of corresponding decoder output ends, and each decoder output end is connected with an enabling end E for generating corresponding decoder output end signals according to different ternary input signals.
2. The ternary decoder of claim 1, wherein in the input logic circuit, an input terminal is connected to a positive power supply VDD, a negative power supply GND or floating according to different input signals, an input voltage V 0 input through an input resistor R 0 is connected to positive input terminals of two comparators OP1 and OP2, an input voltage V 0 is further connected to the positive power supply VDD through a voltage dividing resistor R 2, an input voltage V 0 is further connected to the negative power supply GND through a voltage dividing resistor R 3, the positive power supply VDD and the negative power supply GND are further sequentially connected to a voltage dividing resistor R 4、R5、R6、R7, a reverse input terminal of the comparator OP1 is connected between the voltage dividing resistors R 4、R5, a reverse input terminal of the comparator OP2 is connected between the voltage dividing resistors R 6、R7, resistance values of the voltage dividing resistors R 2~R7 are the same, an output terminal of the comparator OP1 is connected to input terminals of a first and a third and gate through a non-gate, an output terminal of the comparator OP1 is connected to an input terminal of a second and an output terminal of the comparator OP2 through a non-gate; the output ends of the first, second and third AND gates are three high-low level signal output ends B 0、B1、B2.
3. The ternary decoder of claim 2, wherein the input resistor R 0 has a resistance of 50Ω and the divider resistors R 2~R7 have a resistance of 500kΩ.
4. The ternary decoder of claim 2, comprising N 3 output and gates, wherein the output of each output and gate is the decoder output Y, each of the high and low signal outputs is connected to the input of each output and gate, and the enable E is connected to the input of each output and gate.
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| JPS5862955A (en) * | 1981-09-17 | 1983-04-14 | ジ−メンス・アクチエンゲゼルシヤフト | High frequency digital signal reproducing repeater |
| CN105471504A (en) * | 2015-12-20 | 2016-04-06 | 西北工业大学 | Communication method based on visible light and visible light emitting device |
| CN108628795A (en) * | 2017-03-17 | 2018-10-09 | 安立股份有限公司 | Ternary signal generation device and ternary signal production method |
| CN208126845U (en) * | 2018-05-08 | 2018-11-20 | 宗仁科技(平潭)有限公司 | A kind of Digitron display driver circuit and electronic watch |
| CN111755051A (en) * | 2020-06-19 | 2020-10-09 | 杭州电子科技大学 | 2-9 line three-value decoder circuit based on memristor |
| CN219227882U (en) * | 2022-12-28 | 2023-06-20 | 浙江科博达工业有限公司 | Vehicle tail lamp circuit |
| US20240119210A1 (en) * | 2022-10-11 | 2024-04-11 | Lite-On Singapore Pte. Ltd. | Method for establishing optocoupler spice model |
-
2024
- 2024-04-12 CN CN202410436758.3A patent/CN118041367B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5862955A (en) * | 1981-09-17 | 1983-04-14 | ジ−メンス・アクチエンゲゼルシヤフト | High frequency digital signal reproducing repeater |
| CN105471504A (en) * | 2015-12-20 | 2016-04-06 | 西北工业大学 | Communication method based on visible light and visible light emitting device |
| CN108628795A (en) * | 2017-03-17 | 2018-10-09 | 安立股份有限公司 | Ternary signal generation device and ternary signal production method |
| CN208126845U (en) * | 2018-05-08 | 2018-11-20 | 宗仁科技(平潭)有限公司 | A kind of Digitron display driver circuit and electronic watch |
| CN111755051A (en) * | 2020-06-19 | 2020-10-09 | 杭州电子科技大学 | 2-9 line three-value decoder circuit based on memristor |
| US20240119210A1 (en) * | 2022-10-11 | 2024-04-11 | Lite-On Singapore Pte. Ltd. | Method for establishing optocoupler spice model |
| CN219227882U (en) * | 2022-12-28 | 2023-06-20 | 浙江科博达工业有限公司 | Vehicle tail lamp circuit |
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