CN111736650B - Integrator circuit - Google Patents
Integrator circuit Download PDFInfo
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- CN111736650B CN111736650B CN202010643843.9A CN202010643843A CN111736650B CN 111736650 B CN111736650 B CN 111736650B CN 202010643843 A CN202010643843 A CN 202010643843A CN 111736650 B CN111736650 B CN 111736650B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The invention provides an integrator circuit, comprising: a voltage-current conversion unit for converting an input voltage into an input current; the current scaling unit is used for scaling the input current according to a proportion to obtain output current; a current-voltage conversion unit for converting the output current into an output voltage; the invention can effectively relieve the compromise problem between the resistance noise and the chip area.
Description
Technical Field
The invention relates to the field of circuit design, in particular to an integrator circuit.
Background
Integrator circuits are widely used in analog integrated circuits, one of which is a high speed sigma delta analog to digital converter that is primarily used to receive an input signal and a feedback signal and convert a residual current to an output voltage.
However, existing integrator circuits typically consist of a resistor and a capacitor, the output being related to the product of the resistance and the capacitance, one of which is determined and the other is determined. That is, if the introduced noise is reduced by reducing the resistance value, the capacitance value needs to be increased, which leads to a large increase in chip area, and finally leads to a compromise solution between noise and chip area during circuit design.
Disclosure of Invention
In view of the problems in the prior art, the present invention provides an integrator circuit, which mainly solves the problem that the existing circuit cannot take both noise and chip area into consideration.
In order to achieve the above and other objects, the present invention adopts the following technical solutions.
An integrator circuit, comprising:
a voltage-current conversion unit for converting an input voltage into an input current;
the current scaling unit is used for scaling the input current according to a proportion to obtain output current;
and the current-voltage conversion unit is used for converting the output current into output voltage.
Optionally, the current scaling unit includes a first constant current source, a second constant current source, a first MOS transistor, and a second MOS transistor; the drain electrode of the first MOS tube receives the input current and is connected with the negative electrode of the first constant current source; the source electrode of the first MOS tube and the source electrode of the second MOS tube are grounded; the grid electrode of the first MOS tube is connected with the grid electrode of the second MOS tube and is connected with the voltage-current conversion unit; and the drain electrode of the second MOS tube is connected with the negative electrode of the second constant current source to serve as a current output end.
Optionally, the first MOS transistor and the second MOS transistor both adopt NMOS transistors.
Optionally, the width-to-length ratio of the conduction channel of the first MOS transistor is N times the width-to-length ratio of the conduction channel of the second MOS transistor, where N is a positive number.
Optionally, the current value of the first constant current source is N times the current value of the second constant current source, where N is a positive number.
Optionally, the voltage-current conversion unit includes a resistor and a first amplifier, one end of the resistor receives the input voltage, and the other end of the resistor is connected to a non-inverting input terminal of the first amplifier to serve as an output terminal of the input current; the inverting input end of the first amplifier is grounded; the output end of the first amplifier is connected with the grid electrode of the first MOS tube.
Optionally, the resistance value of the resistor is adjusted according to a ratio of the width-to-length ratio of the conducting channel of the first MOS transistor to the width-to-length ratio of the conducting channel of the second MOS transistor.
Optionally, the current-voltage conversion unit includes a capacitor and a second amplifier, and a non-inverting input terminal of the second amplifier is grounded; the reverse input end of the second amplifier is connected with one end of the capacitor and receives the output current; and the other end of the capacitor is connected with the output end of the second amplifier and is used as an output port of the output voltage.
Optionally, the capacitance type selection is performed according to a ratio of the width-to-length ratio of the conductive channel of the first MOS transistor to the width-to-length ratio of the conductive channel of the second MOS transistor.
As described above, the integrator circuit of the present invention has the following advantageous effects.
The input current is scaled through the current scaling unit, and the value of the integral capacitor and/or the resistor can be adjusted according to the scaling, so that the value of the capacitor resistor is more free and flexible, and the problem of compromise between resistor noise and the chip area is effectively solved.
Drawings
Fig. 1 is a schematic diagram of a conventional integrator circuit.
Fig. 2 is a schematic diagram of an integrator circuit according to an embodiment of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The inventor finds that:
referring to fig. 1, a typical integrator circuit is shown. The circuit receives an input voltage Vin, converts the input voltage into a current I0 which is Vin/R0. through an amplifier A0 and a resistor R0, and generates an output voltage by flowing the current I0 through an integrating capacitor C0
The integrator is characterized in that for a fixed input signal characteristic, the output signal amplitude is only related to the product of R0 and C0. For example, assuming that the input is a 10MHz, 100mv amplitude sinusoidal signal, then the integrator outputs a 90 degree difference sinusoidal signal. Assuming that the integrator output amplitude is also required to be 100mv, the product of R0, C0 is required to be equal to 15.9 nS. In this case, R0 and C0 may be selected from a variety of options, for example, R0 ═ 1.59kohm, and C0 ═ 10 pF. The circuit has the disadvantage that only one of R0 and C0 is allowed to be any value as a variable, as long as one is determined, and the other is determined accordingly. For example, to reduce the noise introduced by the resistor, R0 can be reduced to 400ohm, and the capacitance C0 is increased to about 40pF, which greatly increases the chip area, and finally results in a compromise between noise and chip area.
Referring to fig. 1, the present invention provides an integrator circuit, comprising:
a voltage-current conversion unit for converting an input voltage into an input current;
the current scaling unit is used for scaling the input current according to a proportion to obtain output current;
and the current-voltage conversion unit is used for converting the output current into the output voltage.
In one embodiment, the current scaling unit comprises a first constant current source, a second constant current source, a first MOS (metal oxide semiconductor) transistor and a second MOS transistor; the drain electrode of the first MOS tube receives input current and is connected with the negative electrode of the first constant current source; the source electrode of the first MOS tube and the source electrode of the second MOS tube are grounded; the grid electrode of the first MOS tube is connected with the grid electrode of the second MOS tube and is connected with the voltage-current conversion unit; and the drain electrode of the second MOS tube is connected with the negative electrode of the second constant current source to be used as a current output end.
Optionally, the first MOS transistor and the second MOS transistor both adopt NMOS transistors.
In one embodiment, the voltage-current conversion unit comprises a resistor and a first amplifier, wherein one end of the resistor receives an input voltage, and the other end of the resistor is connected with a non-inverting input end of the first amplifier to serve as an output end of an input current; the inverting input end of the first amplifier is grounded; the output end of the first amplifier is connected with the grid electrode of the first MOS tube.
In one embodiment, the current-voltage conversion unit comprises a capacitor and a second amplifier, wherein the non-inverting input end of the second amplifier is grounded; the reverse input end of the second amplifier is connected with one end of the capacitor and receives the output current; the other end of the capacitor is connected with the output end of the second amplifier and used as an output port of the output voltage.
Specifically, referring to fig. 2, one end of the resistor R1 is connected to the input voltage VinThe other end of the amplifier is connected with the non-inverting input end of an amplifier A1 and the drain electrode of an NMOS tube M1, and outputs current I to M11(ii) a The cathode of the current source IB1 is connected to the drain of M1, so that the drain current is equal to the output current of IB1 and I1Summing; the inverting input end of the amplifier A1 is grounded, the output end of the amplifier A1 is connected with the grid of the NMOS transistor M1 and the grid of the NMOS transistor M2, and the sources of the NMOS transistors M1 and M2 are grounded; the drain of M2 is connected to the negative electrode of constant current source IB2, and one end of integrating capacitor C1 is connected to output current I to C12(ii) a The inverting input terminal of the amplifier A2 is connected with the drain of the M2, the non-inverting input terminal of the A2 is grounded, and the other end of the integrating capacitor C1 is connected with the output terminal of the A2 to serve as the output port of the integrating circuit.
In an embodiment, the current value of the constant current source IB1 may be set to be N times the current value of the constant current source IB2, where N is a positive number, and the specific value may be selectively adjusted according to an actual application scenario. Further, the conduction channel width-to-length ratio of M1 may be set to be N times the conduction channel width-to-length ratio of M2.
The working principle of the circuit is as follows:
the input voltage Vin is connected to the left end of the resistor R1, and because of the amplifier, the right end of the resistor is virtual ground, so there is a current I1:
since the current IB1 is N × IB2, the width/length of M1 is equal to N times the width/length of M2, therefore:
the push-out integrator output voltage Vout 1:
an integrating capacitor C1 is connected to the drain of the M2 transistor and receives the scaled current I2. Compared with the conventional integrating circuit in fig. 1, assuming that R1 is equal to R0, in order to maintain the same output amplitude, the capacitance C1 is equal to C0/N, and the chip area can be reduced by N times. Similarly, assuming that C1 is C0 and the same output voltage amplitude is maintained, R1 is R0/N and the noise introduced by the resistor is reduced by 10 log (N) dB. The resistance value of the resistor and/or the capacitance value of the capacitor can be flexibly adjusted according to the scaling.
In summary, the integrator circuit provided by the invention scales the current in proportion through the mirrored current scaling unit, so that the problem of compromise between resistance noise and capacitance area can be effectively alleviated; by adjusting the scaling, the selection of the values of the resistor and the integrating capacitor can be made more flexible and free. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (6)
1. An integrator circuit, comprising:
the voltage-current conversion unit is used for converting input voltage into input current and comprises a resistor and a first amplifier, wherein one end of the resistor receives the input voltage, and the other end of the resistor is connected with a non-inverting input end of the first amplifier to serve as an output end of the input current; the inverting input end of the first amplifier is grounded; the output end of the first amplifier is connected with the grid electrode of the first MOS tube;
the current scaling unit is used for scaling the input current according to a proportion to obtain output current; the current scaling unit comprises a first constant current source, a second constant current source, a first MOS (metal oxide semiconductor) tube and a second MOS tube; the drain electrode of the first MOS tube receives the input current and is connected with the negative electrode of the first constant current source; the source electrode of the first MOS tube and the source electrode of the second MOS tube are grounded; the grid electrode of the first MOS tube is connected with the grid electrode of the second MOS tube and is connected with the voltage-current conversion unit; the drain electrode of the second MOS tube is connected with the negative electrode of the second constant current source to serve as a current output end;
the current-voltage conversion unit is used for converting the output current into output voltage and comprises a capacitor and a second amplifier, and the non-inverting input end of the second amplifier is grounded; the reverse input end of the second amplifier is connected with one end of the capacitor and receives the output current; and the other end of the capacitor is connected with the output end of the second amplifier and is used as an output port of the output voltage.
2. The integrator circuit of claim 1, wherein the first MOS transistor and the second MOS transistor are both NMOS transistors.
3. The integrator circuit of claim 1, wherein the first MOS transistor has a conduction channel width-to-length ratio that is N times the conduction channel width-to-length ratio of the second MOS transistor, where N is a positive number.
4. The integrator circuit of claim 3, wherein the current value of the first constant current source is N times the current value of the second constant current source, where N is a positive number.
5. The integrator circuit of claim 1, wherein the resistance value is adjusted according to a ratio of the first MOS transistor conducting channel width-to-length ratio to the second MOS transistor conducting channel width-to-length ratio.
6. The integrator circuit of claim 1, wherein the capacitance selection is based on a ratio of the first MOS transistor conductive channel width-to-length ratio to the second MOS transistor conductive channel width-to-length ratio.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010643843.9A CN111736650B (en) | 2020-07-07 | 2020-07-07 | Integrator circuit |
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| CN202010643843.9A CN111736650B (en) | 2020-07-07 | 2020-07-07 | Integrator circuit |
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| CN111736650A CN111736650A (en) | 2020-10-02 |
| CN111736650B true CN111736650B (en) | 2022-03-22 |
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| JP4662698B2 (en) * | 2003-06-25 | 2011-03-30 | ルネサスエレクトロニクス株式会社 | Current source circuit and current setting method |
| US9590590B2 (en) * | 2014-11-10 | 2017-03-07 | Analog Devices Global | Delta-sigma modulator having transconductor network for dynamically tuning loop filter coefficients |
| ITUA20163475A1 (en) * | 2016-05-16 | 2017-11-16 | St Microelectronics Srl | VOLTAGE REGULATOR CIRCUIT, ELECTRONIC DEVICE AND CORRESPONDENT PROCEDURE |
| CN105954624A (en) * | 2016-06-17 | 2016-09-21 | 丰郅(上海)新能源科技有限公司 | Detection device |
| US10103744B1 (en) * | 2017-04-12 | 2018-10-16 | Analog Devices Global | Power scaling a continuous-time delta sigma modulator |
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