KR20090001356A

KR20090001356A - The method and apparatus for improving the voltage margin of pam

Info

Publication number: KR20090001356A
Application number: KR1020070065656A
Authority: KR
Inventors: 신성철; 최훈대
Original assignee: 삼성전자주식회사
Priority date: 2007-06-29
Filing date: 2007-06-29
Publication date: 2009-01-08

Abstract

The pulse amplitude modulation transmit driver according to the present invention comprises: a first load connected in series between a voltage source and a first output node; A second rod connected in series between the voltage source and a second output node; A first current source and a second current source electrically connected to a ground voltage, and electrically connected to the first output node and the second output node, a differential input pair of a zero bit signal and a differential input of a first bit signal An input data driver for distributing currents of the first current source and the second current source to the first rod and the second rod in response to a pair to determine voltages of the first output node and the second output node; And a common mode changer electrically connected to the first output node and the second output node and supplying a common mode current to the first rod and the second rod.

The present invention has the effect of increasing the voltage margin when comparing the reference voltage and the transmitted signal by changing the common mode level when the exclusive logical sum of the first bit signal and the zero bit signal of the input data is true. In addition, the process of determining the transmission data in the reception driver using only one reference voltage is simpler and faster, and there is an advantage of reducing the number of signals transmitted by transmitting only one reference voltage.

Description

Method and Apparatus for improving the voltage margin of PAM in pulse amplitude modulation

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating a transmitter, a channel, and a receiver for transmitting a 2-bit signal.

2 is a view showing the shape of the signal according to the symbol of the pulse amplitude modulation according to the present invention.

3 is a diagram illustrating a pulse amplitude modulation transmission driver according to the present invention.

4A to 4B are diagrams showing a pulse amplitude modulation transmission driver according to a first embodiment of the present invention.

5 is a diagram showing a pulse amplitude modulation transmission driver according to a second embodiment of the present invention.

6 is a flowchart illustrating a pulse amplitude modulation method according to the present invention.

7 shows a pulse amplitude modulation transmission apparatus according to the present invention.

8 is a diagram illustrating a pulse amplitude modulation reception driver according to a third embodiment of the present invention.

9A through 9B are detailed views and timing diagrams of the integrator and the storage unit of FIG. 8.

10 is a diagram illustrating a pulse amplitude modulation reception driver according to a fourth embodiment of the present invention.

11A-11B are detailed views of the transducer of FIG. 10.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse amplitude modulation method and apparatus, and more particularly to increasing voltage margin in four-level pulse amplitude modulation (PAM).

Efforts have been made to improve speed and signal to noise ratio (SNR) in transmitting digital signals. Since the speed of the channel is fixed when transmitting a signal, a signal must be processed so that a larger amount of signal can be transmitted at one time in the process of transmitting a signal. In general, however, it is important to improve both speed and SNR at the same time as the speed increases.

Pulse amplitude modulation is a method of representing a symbol to be transmitted by varying the amplitude of the pulse. For example, when transmitting a signal of 1 bit, high may represent 1 and low may represent 0, which is called 2PAM. In this case, the larger the difference between the amplitudes representing the different symbols, the higher the SNR and the better the performance. If two bits are sent at once to increase the transmission speed, the signal can be transmitted at twice the speed than one bit at a time. This is called 4PAM. Although 4PAM is twice as fast as 2PAM, since 4 symbols must be represented, there is a problem that SNR is reduced due to a small voltage margin.

In general, 4PAM has a larger voltage source than 2PAM, and can increase the voltage size of the voltage source in order to increase the voltage margin. However, in this case, the power consumption is increased, so the method of increasing the voltage source alone increases the SNR.

Therefore, there is a need for a method and apparatus for increasing the SNR by increasing the voltage margin while maintaining the size of the voltage source at 4 PAM.

SUMMARY OF THE INVENTION The present invention provides a pulse amplitude modulation method for changing a common mode level according to an input signal in order to increase voltage margin in a four-level pulse amplitude modulation scheme. An amplitude modulated receive driver is provided.

According to an aspect of the present invention, there is provided a pulse amplitude modulation transmission driver comprising: a first rod connected in series between a voltage source and a first output node; A second rod connected in series between the voltage source and a second output node; A first current source and a second current source electrically connected to a ground voltage, and electrically connected to the first output node and the second output node, a differential input pair of a zero bit signal and a differential input of a first bit signal An input data driver for distributing currents of the first current source and the second current source to the first rod and the second rod in response to a pair to determine voltages of the first output node and the second output node; And a common mode changer electrically connected to the first output node and the second output node and supplying a common mode current to the first rod and the second rod. The common mode changing unit may change the common mode current in response to a differential input pair of an exclusive logical sum (XOR) of the 0th bit signal and the first bit signal.

The common mode changer may include: a third load connected in series between the voltage source and a third node; A fourth rod connected in series between the voltage source and a fourth node; A third current source electrically connected to the ground voltage; And receiving a differential input pair of an exclusive logical sum (XOR) of the zeroth bit signal and the first bit signal, wherein the first output node, the second output node, the third node, the fourth node, and the fourth node. A third electrical source electrically connected to a third current source to supply the current of the third current source to the first rod and the second rod or to the third rod and the fourth rod according to the differential input pair of the exclusive OR; It may include a mode control unit.

The common mode control unit is electrically connected to the first output node, the third node, and the third current source, and the third current source is connected to the first rod or the third load according to the exclusive-OR differential input pair. A first output common mode controller configured to supply at least a portion of the current supplied from the second output common mode; And among the currents electrically connected to the second output node, the fourth node, and the third current source and supplied to the second rod or the fourth rod from the third current source according to the exclusive-OR differential input pair. It may include a second output common mode control unit for supplying at least a portion.

The first current source and the second current source may supply currents of different magnitudes.

The input data driver may be electrically connected to the first output node, the second output node, and the first current source to supply current supplied from the first current source according to a differential input pair of the zero bit signal. A zero bit processor configured to supply one load or the second load; And a current electrically connected to the first output node, the second output node, and the second current source to supply a current supplied from the second current source according to a differential input pair of the first bit signal. It may include a first bit processing unit for supplying the two loads.

In the pulse amplitude modulation method according to the present invention, a voltage drop of any one of a first output node for determining a first output signal and a second output node for determining a second output signal according to a zero bit signal is determined. Bit processing step; A first bit processing step of determining a voltage drop of any one of the first output node and the second output node according to a first bit signal; And a common mode changing step of changing a common mode level of the first output node and the second output node according to a combination of the 0th bit signal and the first bit signal.

The zero bit processing step may include bringing a voltage drop of a first output node when the zero bit signal is a first logic level, bringing a voltage drop of a second output node when the second bit level is a second logic level,

The first bit processing step may result in a voltage drop of the first output node when the first bit signal is at the first logic level, and a voltage drop of the second output node when the first bit signal is at the second logic level. Can be.

The magnitude of the voltage drop caused by the zero bit signal and the magnitude of the voltage drop caused by the first bit signal may be different from each other. The changing of the common mode may change the common mode of the first output node and the second output node according to an exclusive logical sum (XOR) of the 0th bit signal and the first bit signal. The common mode changing step lowers the common mode level of the first output node and the second output node when the exclusive OR is true, and reduces the common mode level of the first output node and the second output node when the exclusive OR is false. You can not change the common mode level.

The transmitter according to the present invention is a transmitter for transmitting a signal of n (even number greater than zero) bits, and includes an exclusive logical sum of the k-th bit signal and the k + 1th bit signal for each k (even number less than n). N / 2 exclusive logic gates generating XOR); A first multiplexer for receiving the n / 2 exclusive ORs and outputting one of the exclusive ORs according to the value of k; A second multiplexer for receiving the k-th bit signals for each k and outputting one of the k-th bit signals in accordance with the k value; A third multiplexer for receiving the k + 1th bit signals for each k and outputting one of the k + 1th bit signals according to the k value; A predriver for modulating the outputs of the first to third multiplexers with respective differential input pairs; And a pulse amplitude for receiving the respective differential input pairs and outputting a first output signal and a second output signal according to each of the differential input pairs of the kth bit signal, the k + 1th bit signal, and the exclusive logical sum. And a modulation transmission driver, wherein the first output signal and the second output signal change in common mode level in accordance with the exclusive logical sum.

According to another aspect of the present invention, there is provided a pulse amplitude modulation reception driver comprising: a first bit signal discrimination unit configured to discriminate a first bit signal according to a polarity of a first differential amplification output differentially amplifying a first input signal and a second input signal; And a second differential amplification output obtained by differentially amplifying the first input signal and the reference voltage, and a third differential amplification output obtained by differentially amplifying the second input signal and the reference voltage, and according to the polarity of the first differential amplified output. And a zero bit signal discrimination unit configured to select one of the second differential amplifier output and the third differential amplifier output to determine a zero bit signal.

The zero bit signal determination unit may include: a second differential amplifier configured to differentially amplify the first input signal and a reference voltage to obtain the second differential amplifier output; A third differential amplifier for differentially amplifying the second input signal and the reference voltage to obtain the third differential amplifier output; And a multiplexer configured to receive the second differential amplifier output and the third differential amplifier output and output one of the second differential amplifier output and the third differential amplifier output according to the polarity of the first differential amplifier output. have.

According to another aspect of the present invention, there is provided a pulsed pulse modulation modulation driver comprising: a first bit signal discrimination unit configured to discriminate a first bit signal according to a polarity of a first differential amplification output differentially amplifying a first input signal and a second input signal; And a zero bit signal discrimination unit configured to compare the first input signal and the second input signal with a reference voltage, output a third output voltage and a fourth output voltage according thereto, and determine a zero bit signal according to the first bit signal. The zero bit signal discrimination unit,

Receiving the first to second input signals and the reference voltage, and according to the relationship between the first input signal and the reference voltage, and the relationship between the second input signal and the reference voltage and the third output voltage and the fourth output voltage. A converter to generate; An integrator configured to output one of a second output voltage pair at a high level according to the third output voltage and the fourth output voltage; A storage unit to receive and store the second output voltage pair; An amplifier for receiving and amplifying the output of the storage unit; And a latch for receiving and storing the output of the amplifier.

When the first input signal and the second input signal are both lower than the reference voltage, the fourth output voltage has a higher voltage level than the third output voltage, and the first input signal is lower than the reference voltage and the first input signal. 2 when the input signal is higher than the reference voltage or when the first input signal is higher than the reference voltage and the second input signal is lower than the reference voltage, the third output voltage is higher than the fourth output voltage. It can have

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

The system for transmitting a signal includes a transmitting end Tx, a channel, and a receiving end Rx. The transmitter Tx converts a digitally input signal into an analog signal corresponding to each symbol and transmits the signal to a channel. The channel transfers the signal output from the transmitter Tx to the receiver Rx in a predetermined frequency range. The receiver Rx reads the received signal by converting the analog signal transmitted through the channel into a digital signal. In this case, since the present invention transmits two bits at a time, the transmitter Tx receives the two-bit inputs d0 and d1, converts the signals into analog signals, and transmits the analog signals to the two-bit digital signals d0 and d1. Convert to and print it out.

Since the pulse amplitude modulation method distinguishes the symbols by the magnitude of the pulse, it is determined by comparing the magnitude with the reference voltage Vref when the signal transmitted from the receiving end Rx is read. In this case, the voltage level of the transmitted signal may change due to noise. Thus, the voltage margin between the signal and the reference voltage Vref should be increased to prevent the transmitted signal from being read incorrectly in the process of comparing with the reference voltage Vref. do. The conventional 4PAM system represented four symbols using four voltage levels. Therefore, the interval between the four voltage levels is narrowed, thereby reducing the voltage margin, there was a problem that the SNR increases. To solve this problem, the present invention represents four symbols with three voltage levels by changing the common mode level according to a combination of two bit signals.

Referring to FIG. 2, in the analog signal according to the present invention, the first output signal V− and the second output signal V + may be simultaneously transmitted, and each waveform may have three levels. The first output signal when the exclusive OR (XOR) of the zero bit signal d0 representing the Least significant bit (LSB) and the first bit signal d1 representing the Most significant bit (MSB) is true. The common mode level of the (V−) and the second output signal V + is lowered, and if it is false, there is no change in the common mode level. As a result, the common mode level is lowered when 10 or 01 is transmitted, so that both the first output signal V- and the second output signal V + are lower than the reference voltage Vref, and when 00 or 11 is transmitted, the reference voltage is reduced. Vref is between the first output signal V− and the second output signal V +.

When reading the transmitted signal as shown in FIG. 2, the polarity of the difference signal between the first output signal V- and the second output signal V + and the relationship between these and the reference voltage Vref are used. When the first bit signal d1 is 1, the second output signal V + is higher than the first output signal V−, and when the first bit signal d1 is 0, the first output signal ( V− is a level higher than the second output signal V +. Therefore, the first bit signal d1 can be known from the polarity of the difference signal between the first output signal V− and the second output signal V +. When the first bit signal d1 is 1 after the difference between the first output signal V- and the second output signal V- and the reference voltage Vref is obtained, The zeroth bit signal d0 is obtained from the difference signal between the second output signal V + and the reference voltage Vref. When the first bit signal d1 is 0, the first output signal V- and the reference voltage are obtained. The 0th bit signal d0 is obtained from the difference signal of (Vref). When the first bit signal d1 is 1, when the second output signal V + is smaller than the reference voltage Vref, the 0th bit signal d0 is 0, and when the first bit signal d1 is large, the 0th bit signal d0 Is 1. When the first bit signal d1 is 0, when the first output signal V- is smaller than the reference voltage Vref, the 0th bit signal d0 is 1, and when the first bit signal d1 is large, the 0th bit signal d0 ) Is 0.

By changing the common mode level of the first output signal V− and the second output signal V + according to the exclusive logical sum XOR of the zeroth bit signal d0 and the first bit signal d1 as in the present invention. Since the symbols are represented by three voltage levels, the difference between the reference voltages Vref and the output signals V + and V- increases as compared with the conventional technology using four voltage levels, thereby increasing the voltage margin. In addition, the conventional 4PAM system requires judging about four levels, so two reference voltages (Vref) are required. However, the present invention can reduce the number of reference voltages because only one reference voltage Vref needs to be used.

The pulse amplitude modulation transmission driver 100 according to the present invention includes a first rod R1, a second rod R2, an input data driver 110, and a common mode changer 120.

In the present invention, data is transmitted by the first output signal V− and the second output signal V +, which are voltages of the first output node N1 and the second output node N2, respectively. The voltages of the first output node N1 and the second output node N2 are determined by the voltage drop by the first load R1 and the second load R2 from the voltage source VDD, respectively. To this end, the input data driver 110 may include a zero bit positive input V0 + representing a zero bit signal d0, a zero bit negative input V0, a first bit positive input V1 +, and The voltage drop is determined by distributing current to the first rod R1 and the second rod R2 by receiving the first bit negative input V1-. Each negative input is an inverted signal of each positive input.

The resistances of the first rod R1 and the second rod R2 are preferably equal to each other, and may vary according to various embodiments.

According to the present invention, the common mode level of the first output signal V− and the second output signal V + is changed by an exclusive logical sum XOR of the zeroth bit signal d0 and the first bit signal d1. To this end, the common board changing unit 120 receives the exclusive OR signal of the zero bit signal d0 and the first bit signal d1 and the exclusive OR signal XOR−. Only when true, the current is supplied to the first rod R1 and the second rod R2 in common to lower the common mode level of the first output node N1 and the second output node N2. In this case, the exclusive OR sum signal XOR + is high when the exclusive OR is true and low when it is false. The exclusive OR negative signal XOR− is the inversion of the exclusive OR positive signal XOR +.

4A shows a detailed circuit diagram of the first embodiment of the pulse amplitude modulation transmission driver of FIG. The input data driver 110 includes a 0 th bit processor MN1 and MN2, a first bit processor MN3 and MN4, a first current source MN5, and a second current source MN6. Preferably, currents of different magnitudes may flow in the first current source MN5 and the second current source MN6, and more preferably, the current of the second current source MN6 is the magnitude of the current of the first current source MN5. 2 times The current flowing in the first current source MN5 is supplied to the first rod R1 or the second rod R2 by the 0-bit processing units MN1 and MN2, and the current flowing in the second current source MN6 It is supplied to the 1st rod R1 or the 2nd rod R2 by the 1-bit process part MN3 and MN4. In this embodiment, it is assumed that the current flowing through the first current source MN5 is i and the current flowing through the second current source MN6 is 2i. This is exemplary and may have a combination of various sizes. The first current source MN5 and the second current source MN6 may be configured as current mirrors (not shown), and the size of the current may be adjusted by the area ratio of the transistors.

The 0th bit processing units MN1 and MN2 and the first bit processing units MN3 and MN4 are each composed of transistor pairs. In the present embodiment, MN1 to MN4 are n-type metal oxide semiconductor field effect transistors (NMOS), which are turned on when the gate input is high level, and current flows, and is turned off when the gate input is low level. (turn-off) and no current flows. Thus current flows all the way to the turned-on transistor. This assumption is illustrative and it is also possible to change the design by distributing current at a constant rate between the pair of transistors.

The common mode changing unit 120 includes a third rod R3, a fourth rod R4, a third current source MN11, and a common mode controller 120. The common mode controller 120 receives the differential input pairs XOR + and XOR- of the exclusive OR and receives the third current source MN11 at the first load R1 and the second load R2 only when the exclusive OR is true. Supply current flowing to At this time, if the resistance of the first rod (R1) and the second rod (R2) is the same, the current flowing through the third current source (MN11) is divided in half and is supplied to the first rod (R1) and the second rod (R2), thereby The same voltage drop is generated at the first output node N1 and the second output node N2.

The common mode controller 120 includes first output common mode controllers MN7 and MN8 and second output common mode controllers MN9 and MN10. The first output common mode controllers MN7 and MN8 and the second output common mode controllers MN9 and MN10 are configured as transistor pairs, respectively. MN7 of the first output common mode controllers MN7 and MN8 is connected to the first node N1, and MN8 is connected to the third node N3. MN9 of the second output common mode controllers MN9 and MN10 is connected to the fourth node N4 and MN10 is connected to the second node N2. If the exclusive OR is true, the exclusive OR positive signal (XOR +) and negative signal (XOR-) are high and low, respectively, so that MN7 and MN10 are turned on and MN8 and MN9 are turned off to The current of the third current source MN11 is supplied to the first rod R1 and the second rod R2, whereby the first output node N1 and the second output node N2 are commonly dropped in voltage. If the exclusive OR (XOR) is false, the exclusive OR positive signal (XOR +) and negative signal (XOR-) are low and high levels, respectively, so that MN8 and MN9 are turned on and MN7 and MN10 are turned off. The current of the third current source flows to the third rod R3 and the fourth rod R4 without supplying the current of the third current source MN11 to the first rod R1 and the second rod R2. As a result, the voltage drop due to the common mode changing unit 120 does not occur in the first output node N1 and the second output node N2.

4B is a table showing a current Io flowing in the first rod R1 and a current Iob flowing in the second rod R2 according to the 0th bit signal d0 and the first bit signal d1. 4A and 4B, values of the first output signal V− and the second output signal V + according to the zeroth bit signal d0 and the first bit signal d1 will be described in detail. For convenience, the first bit signal d1 and the zeroth bit signal d0 are denoted in order to represent this. For example, in the case where the input data '10' is shown, the first bit signal d1 is 1 and the 0th bit signal d0 is 0. It is assumed that the currents supplied from the first current source MN5, the second current source MN6, and the third current source third current source MN11 are i, 2i, and 2i, respectively, and the first to fourth loads R1, R2, It is assumed that the resistances of R3 and R4) are all the same.

When the input data is 00, the zero bit positive input V0 + and the first bit positive input V1 + are low level, the zero bit negative input V0- and the first bit negative input V1-. ) Is high level. As a result, MN1 and MN3 are turned off, MN2 and MN4 are turned on, and the currents of the first current source MN5 and the second current source MN6 flow through the second rod R2. In addition, since the exclusive AND (XOR) of 00 is 0, and the exclusive OR is positive and exclusive signals XOR + are low level and high level, respectively, MN7 and MN10 are turned off to turn off the third current source. The current of the MN11 flows by i into the third rod R3 and the fourth rod. Accordingly, Io and Iob become 0 and 3i, respectively, so that the first output signal V− and the second output signal V + become VDD and GND levels, respectively.

When the input data is 01, since MN1 and MN4 are turned on and MN2 and MN3 are turned off, currents i and 2i are supplied to the first rod R1 and the second rod R2, respectively. In addition, since the exclusive OR is true, MN7 and MN10 are turned on so that the current of the third current source MN11 is supplied to the first rod R1 and the second load by i, respectively, to cause a voltage drop at the common mode level. . As a result, the currents flowing through the first rod R1 and the second rod R2 become 2i and 3i, respectively, and the first output signal V− and the second output signal V + are respectively (1/3) VDD and The GND level is reached.

When 10 is input as the input data based on the same principle as described above, the exclusive logic sum (XOR) becomes true and a common mode voltage drop occurs so that the current flowing through the first load R1 and the second load R2 is 3i and 2i, respectively. The first output signal V− and the second output signal V + become GND and (1/3) VDD levels, respectively. When 11 is input as the input data, the exclusive OR is false and the common mode voltage drop does not occur, and the currents flowing through the first and second loads R1 and R2 become 3i and 0, respectively. The first output signal V− and the second output signal V + are at the GND and VDD levels, respectively.

As a result, the current is additionally supplied from the common mode changing unit 120 to the first rod R1 and the second rod R2 by i only when the exclusive OR is true, so that the first output signal V− and The common mode level of the second output signal V + is lowered.

The present invention preferably makes the magnitude of the current supplied from the first current source MN5 and the second current source MN6 different. When the first current source MN5 and the second current source MN6 are configured as current mirrors, each channel width must be configured differently in order to change the magnitude of each current. In the second embodiment, in order to improve the symmetry of the circuit in such a circuit, the same circuits are repeatedly used in the second current source MN6 and the first bit processing units MN3 and MN4 to adjust the channel width of the transistors used in the present circuit. All are provided with the same width, and the symmetry of a circuit is improved. In addition, in order to improve the symmetry of the circuit in the common mode changing unit 220, the third current source MN11 is divided into two and used. The first rod R1, the second rod R2, the first current source MN27, and the zero bit processing units MN21 and MN22 of the second embodiment are the same as the first embodiment. The configuration of the first bit processing units MN23 to 26 and MN28 to MN29 and the common mode changing unit 220 will be described in detail.

Since the second current source MN6 preferably supplies twice the current supplied from the first current source MN5, the second current source MN6 is configured of two transistors to improve the symmetry of the circuit. To this end, the second current source is composed of two transistors, MN28 and MN29, and the channel widths of MN27 to MN29 are designed to be the same. MN28 and MN29 are each connected with separate transistor pairs. As illustrated in FIG. 5, the MN28 includes a first bit processing unit including MN23 and MN24, and the MN29 includes a first bit processing unit consisting of MN25 and MN26, and all channel widths of MN21 to MN26 are the same. Therefore, the symmetry of the circuit is achieved in the 0th bit processing units MN21, MN22, and MN27, the first bit processing units MN23 to MN26, and MN28 to MN29, the first current source MN5, and the second current source MN6.

Since the third current source MN11 preferably supplies twice the current supplied from the first current source MN5, the third current source MN11 may be divided into two and configured as two transistors MN34 and MN35. In addition, separate transistor pairs MN30 and MN31 and MN32 and MN33 are respectively connected to MN34 and MN35. MN30 to MN33 all have the same channel width. This improves the symmetry of the common mode changing unit 120.

In the pulse amplitude modulation method according to the present invention, the first output node N1 and the second output node N2 according to the zeroth bit signal d0, the first bit signal d1, and their exclusive logical sum XOR. Determine the voltage drop of. This includes a zero bit processing step, a first bit processing step, and a common mode changing step.

When the zeroth bit signal d0, the first bit signal d1, and the exclusive logical sum XOR are input, the process proceeds. The order of processing of the 0th bit signal d0, the first bit signal d1, and the exclusive logical sum XOR may be in any order, and may proceed sequentially or simultaneously.

The zeroth bit processing step will be described. The value of the 0 th bit signal d0 is determined (S602). When the 0th bit signal d0 is 0, the second output node N2 is voltage-dropped by supplying a current of the first current source MN5 to the second load R2 (S604). When the 0th bit signal d0 is 1, the first output node N1 is voltage-dropped by supplying a current of the first current source MN5 to the first load R1 (S606).

Next, the first bit processing step will be described. The value of the first bit signal d1 is determined (S608). When the first bit signal d1 is 0, the second output node N2 is voltage-dropped by supplying a current of the second current source MN6 to the second load R2 (S610). When the first bit signal d1 is 1, the current of the second current source MN6 is supplied to the first load R1 to drop the first output node N1 in step S612. Preferably, since the current of the second current source MN6 is twice the current of the first current source MN5, the voltage drop caused by the first bit signal d1 is twice the voltage drop caused by the zero bit signal d0. to be.

Finally, the common mode change step will be described. The exclusive logical sum XOR of the 0 th bit signal d0 and the first bit signal d1 is determined (S614). When the exclusive OR is zero, the voltage of the first output node N1 and the voltage of the second output node N2 are determined without changing the common mode. When the exclusive OR is 1, the current of the third current source MN11 is supplied to the first rod R1 and the second rod R2 so that the first output node N1 and the second output node N2 are supplied. The common mode voltage of is lowered (S616).

Since the pulse amplitude modulation transmission driver according to the present invention processes two bits at a time, when sending a plurality of bits, the pulse amplitude modulation transmission driver needs to bundle them two by one in succession, which is called a serial link. The present invention provides a transmitter 300 for this purpose.

The transmitter 300 according to the present invention transmits n / 2 exclusive logic gates 310, first to third multiplexers MUX1, MUX2, and MUX3 when n (n is an even number) of signals, and pulse amplitude. It includes a modulation transmission driver. The pulse amplitude modulation transmission driver is in accordance with the first or second embodiment described above. Hereinafter, the transmission apparatus 300 will be described in detail on the assumption that an 8-bit input, that is, n is 8.

The zeroth to seventh bit signals d0 to d7 are input to four exclusive logic gates 310 each having two bits. The four exclusive logic gates obtain respective exclusive ORs (XOR) and output XOR0, XOR2, XOR4, and XOR6. These are all input to the first multiplexer MUX1. Each of the zeroth bit signals d0, d2, d4, and d6 is input to the second multiplexer MUX2, and each of the first bit signals d1, d3, d5, and d7 is a third multiplexer MUX3. ) Is entered. The first to third multiplexers MUX1, MUX2, and MUX3 select and output inputs according to k values. k is an even number less than n, ie 0, 2, 4, or 6 in this example. Increasing this from 0 to 6 by 2, 8-bit signals can be sequentially processed and transmitted. The exclusive OR (XOR) selected by k, the 0th bit signal d0, and the first bit signal d1 are converted into small differential input pair signals through the pre-drivers 1 through 3, respectively. Therefore, the exclusive OR sum differential input pair XOR, the zero bit signal differential input pair V0, and the first bit signal differential input pair V1 from the pre-drivers Pre-driver 1 to 3 are pulse amplitude modulation drivers. Is output. The pulse amplitude modulation driver Driver modulates it and outputs the first output signal V− and the second output signal V + and outputs a reference voltage Vref. The first output signal V−, the second output signal V +, and the reference voltage Vref are transmitted to the receiving terminal Rx through the channel.

The first output signal V−, the second output signal V +, and the reference voltage Vref transmitted by the transmitting terminal Tx may include the first input signal Vin− and the second input signal of the receiving terminal Rx. (Vin +) and the reference voltage Vref. According to the present invention, the first bit signal d1 is determined as the polarity of the first input signal Vin− and the second input signal Vin +, and the zeroth bit signal d0 is determined as the first input signal Vin− and After comparing the second input signal Vin + with the reference voltage Vref, the zeroth bit signal d0 is determined according to the first bit signal d1. To this end, the pulse amplitude modulation reception driver according to the third embodiment of the present invention includes a first bit signal discrimination unit 410 and a zero bit signal discrimination unit 420, 430, and 440.

The first bit signal determination unit 410 includes an integrator 450, a storage unit 460, an amplifier 470, and a latch 480. When the first input signal Vin− and the second input signal Vin + are input, the integrator 450 outputs an output voltage pair accordingly. In this case, when the first input signal Vin− is higher than the second input signal Vin +, a in FIG. 8 is high and b is low, and the second input signal Vin + is the first input signal (Vin +). If the level is higher than Vin-), a is low and b is high. Since the transmitted signal is very small and changes over time, it uses an integrator to integrate it to get a more accurate level. The storage unit 460 receives and stores a and b, and the amplifier 470 amplifies it. The latch 480 stores this and outputs an MSB when the completion signal ψ is activated. At this time, the amplified signals of a and b are outputted. When a is high level and b is low level, the first bit signal d1 is determined as 0. When b is high level and a is low level, the first bit signal is outputted. (d1) is determined to be 1.

The zeroth bit signal discrimination units 420, 430, and 440 include a second differential amplifier 420, a third differential amplifier 430, and a multiplexer 440.

The second differential amplifier 470 includes an integrator 450, a storage 460, an amplifier 470, and a latch. When the reference voltage Vref and the second input signal Vin + are input to the integrator 450, the output of the integrator 450 is high when the second input signal Vin + is higher than the reference voltage Vref. Level, d is low level, and the reference voltage Vref is higher than the second input signal Vin +, d is high level and c is low level. The storage unit 460 receives and stores c and d, and the amplifying unit 470 amplifies it. The latch 480 stores the amplified signals of c and d to output the second differential amplification output LSB + to the multiplexer 440 whenever the completion signal ψ is activated.

The third differential amplifier 430 includes an integrator 450, a storage 460, an amplifier 470, and a latch 480. When the reference voltage Vref and the first input signal Vin- are input to the integrator 450, the signal output from the integrator 450 has a level at which the first input signal Vin- is higher than the reference voltage Vref. In the case where e is a high level and f is a low level, when the reference voltage Vref is higher than the first input signal Vin−, f is a high level and e is a low level. The storage unit 460 receives and stores e and f, and the amplifier 470 amplifies it. The latch 480 stores the amplified signals of e and f to output the third differential amplifier output LSB- to the multiplexer 440 whenever the completion signal ψ is activated.

The multiplexer 440 receives the second differential amplifier output LSB + and the third differential amplifier output LSB-, receives the MSB signal generated by the first bit signal discriminator 410, and accordingly receives the second differential amplifier. One of the output LSB + and the third differential amplifier output LSB- is selected. According to the MSB, when the first bit signal d1 is 1, the second differential amplifier output LSB + is selected and output. When the first bit signal d1 is 0, the third differential amplitude output LSB- is selected. To print. When the first bit signal d1 is 1 to output the second differential amplification output LSB +, when c is low level and d is high level, the 0 bit signal d0 is 0, c is high level, and d is At the low level, the zeroth bit signal d0 is one. When the first bit signal d1 is 1 to output the third differential amplification output LSB +, when e is high level and f is low level, the 0 bit signal d0 is 0, e is low level and f is At the high level, the zeroth bit signal d0 is one.

9A shows integrators 452 and 454 and storage units 462 and 464. Integrators 452 and 454 include a precharging portion 452 and a power storage portion 454. It receives the first integration input V1, the second integration input V2, the completion signal ψ, the progress signal φ, and the progress signal inversion φ_b. The progress signal φ is a signal representing a clock cycle in which the first integration input V1 and the second integration input V2 are processed, the progress signal inversion φ_b is an inversion signal of the progress signal φ, and the completion signal (ψ) is activated for a predetermined time interval after the differential amplification of the first integral input (V1) and the second integral input (V2) from the integrator (450). 9A and 9B, operations of the integrator 450 and the storage unit 460 will be described in detail.

The integrator 450 charges both the power storage component of the eleventh node N11 and the power storage component of the twenty-second node N22, and the first integration input V1 is higher than the second integration input V2. The electric charge of the electrical storage component of the eleventh node N11 is discharged so that the potential of the twenty-second node N22 is higher than that of the eleventh node N11, and the second integration input V2 is connected to the first integral input ( When the level is higher than V1), the charge of the storage component of the twenty-second node N22 is discharged to make the potential of the eleventh node N11 higher than that of the twenty-second node N22. This generates differential amplifier output pairs (Vo1 and Vo2) and outputs them from the integrator.

All of the power storage components seen at the eleventh node N11 and the twenty-second node N22 before the traveling signal φ becomes high level are charged. The power storage component seen at the eleventh node N11 is a parasitic power storage component by MP5, MP3, MN40. The power storage component seen at the twenty-second node N22 is a parasitic power storage component by MP7, MP10, and MN41. When the progress signal φ is at the high level, the first integration input V1 and the second integration input V2 are input, and when the first integration input V1 has a higher level, When the power storage component has the higher level of the second integration input V2, the storage component of the twenty-second node N22 is discharged. The current flowing through MN42 or MN43 is determined by current source MN44. While the progress signal φ is at the high level (A), the progress signal inversion φ_b is at the low level, and MP3 and MP10 are turned on and MP1 and MP8 are turned off, so the thirty-third node N33 and the forty-fourth node The voltage at N44 is equal to the voltage at the eleventh node N11 and the twenty-second node N22, respectively. While the traveling signal φ is at the high level (A), the voltages of the eleventh node N11 and the twenty-second node N22 are determined according to the first integration input V1 and the second integration input V2. Since the MP3 and MP10 are turned off while the advancing signal φ transitions to the low level and the completion signal ψ maintains the high level (B), the thirty-third node N33 and the forty-fourth node N44 While the progress signal φ is at the high level (A), the voltages of the determined eleventh node N11 and the twenty-second node N22 are stored and output to the amplifier 470. After the output to the amplifier 470 is completed, the completion signal ψ is maintained at a low level for a predetermined time interval (C). When the progress signal φ and the completion signal ψ are at the low level (X), the p-type transistors MP1, MP2, MP4, MP5, MP6, which receive the progress signal φ and the completion signal ψ as the gate inputs, MP7, MP8, and MP9 are turned on, and the eleventh node N11, the twenty-second node N22, the thirty-third node N33, and the forty-fourth node N44 all have a VDD voltage. In addition, both parasitic storage components of the eleventh node N11 and the twenty-second node N22 are charged. Therefore, all the information stored in the eleventh to the 44th node is erased. After the predetermined time interval C has passed, the completion signal ψ and the progress signal φ transition to the high level again, and the next first integration input V1 and the second integration input V2 are input.

The pulse amplitude modulation reception driver 500 according to the fourth embodiment of the present invention includes a first bit signal discrimination unit 510 and a second bit signal discrimination unit 520. Since the operation of the first bit signal determination unit 510 is the same as that of the third embodiment, description thereof will be omitted. The second bit signal determination unit 520 according to the fourth embodiment includes a converter 530, an integrator 450, a storage unit 460, and an amplifier 470. Since the operations of the integrator 450, the storage 460, and the amplifier 470 are the same as in the third embodiment, description thereof is omitted. The converter 530 outputs the third output voltage V3 and the fourth output voltage V4 by comparing the first input signal Vin− and the second input signal Vin + with the reference voltage Vref. The detailed operation of the converter 530 will be described with reference to FIGS. 11A-11B.

11A-11B are detailed views of the transducer of FIG. 10.

The converter 530 receives the first input signal Vin− and the second input signal Vin + and outputs a relationship between the reference voltage Vref as the third output voltage V3 and the fourth output voltage V4. do. The first input signal Vin− enters an input of the reference voltage Vref and the transistor pairs MN51 and MN52. In addition, MN51 is connected to the fifth resistor R5 and MN52 is connected to the sixth resistor R6. When the first input signal Vin− is higher than the reference voltage Vref, a current is supplied to the sixth resistor R6 by the MN53 transistor so that a voltage drop of the fourth output voltage V4 occurs. The MN53 transistor can be configured as a current mirror. When the reference voltage Vref is higher than the first input signal Vin−, a current supplied from the MN53 is supplied to the fifth resistor R5 to cause a voltage drop of the third output voltage V3. When the second input signal Vin + is higher than the reference voltage Vref, the current supplied from the MN56 is supplied to the sixth resistor R6 to cause a voltage drop of the fourth output voltage V4 to occur. When Vin + is lower than the reference voltage Vref, a current supplied from the MN56 is supplied to the fifth resistor R5 to cause a voltage drop of the third output voltage V3. The transistor MN50 is always turned on by the reference voltage Vref to supply current to the sixth resistor R6 and cause a voltage drop of the fourth output voltage V4 to occur. Preferably, MN53, MN56, and MN57 are configured as current mirrors, and supply the same magnitude of current in all channel widths.

Assuming that a current of size i is supplied from MN53, 56, and MN57, the output of converter 530 according to the data input from the transmitter will be described with reference to FIG. 11B. Since the first bit signal d1 is known by the first bit signal discrimination unit, a method of determining the 0th bit signal d0 from the output of the first bit signal d1 and the converter 530 will be described. . When the input data is '01', the first bit signal d1 is '0' and the 0th bit signal d0 is '1'. Since the first input signal Vin− and the second input signal Vin + are signals transmitted from the transmitting terminal Tx, the signals shown in FIG. 2 are referred to.

When the input data is 00, since the first input signal Vin− is higher than the reference voltage Vref and the second input signal Vin + is lower than the reference voltage Vref, the current flowing through the fifth resistor R5 Io. ) Is i supplied from MN51 and current Iob flowing through sixth resistor R6 is 2i supplied from MN50 and MN55. When the input data is 01, since the first input signal Vin- and the second input signal Vin + are at a level lower than the reference voltage Vref, the MN50, MN51, and MN54 are turned on so that the fifth resistor R5 and Current flows through the sixth resistor R6 by 2i and i, respectively. When the input data is 10, the first input signal Vin- and the second input signal Vin + have a lower level than the reference voltage Vref, so that the fifth resistors R5 and 6 are the same as when the input data is 01. Current flows through the resistor R6 by 2i and i, respectively. When the input data is 11, since the first input signal Vin− is lower than the reference voltage Vref and the second input signal Vin + is higher than the reference voltage Vref, the fifth resistor R5 and the sixth resistor ( The current flows through R6) by i and 2i, respectively.

Therefore, when the first bit signal d1 is '0', when the zeroth bit signal d0 is 0, the third output voltage V3 is higher than the fourth output voltage V4 and the zeroth bit signal d0 is used. Is 1, the fourth output voltage V4 is higher than the third output voltage V3. On the contrary, when the first bit signal d1 is '1', when the zeroth bit signal d0 is 0, the fourth output voltage V4 is higher than the third output voltage V3 and the zeroth bit signal d0 is used. Is 1, the third output voltage V3 is higher than the fourth output voltage V4.

The integrator 450, the storage unit 460, the amplifier 470, and the latch amplify and output the third output voltage V3 and the fourth output voltage V4. Since the detailed operation is the same as in the third embodiment, the description is omitted.

Since the first bit signal d1 is known from the first bit signal discrimination unit 410, the 0 th bit signal d0 may be determined from the third output voltage V3 and the fourth output voltage V4. That is, when the third output voltage V3 is higher than the fourth output voltage V4, when the first bit signal d1 is 1, the 0th bit signal d0 is 1 and the first bit signal d1 is 0. In this case, the zero bit signal is zero. When the fourth output voltage V4 is higher than the third output voltage V3, when the first bit signal d1 is 1, the 0-bit signal is 0 and when the first bit signal d1 is 0, the 0-bit signal Is 1.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the pulse amplitude modulation method, the transmission driver, the transmission device, and the reception driver according to the present invention change the common mode level when the exclusive logical sum of the first bit signal and the zero bit signal of the input data is true, When comparing the transmitted signals, it has the effect of increasing the voltage margin. In addition, the process of determining the transmission data in the reception driver using only one reference voltage is simpler and faster, and there is an advantage of reducing the number of signals transmitted by transmitting only one reference voltage.

Claims

A first load connected in series between the voltage source and the first output node;

A second rod connected in series between the voltage source and a second output node;

A first current source and a second current source electrically connected to a ground voltage, and electrically connected to the first output node and the second output node, a differential input pair of a zero bit signal and a differential input of a first bit signal An input data driver for distributing currents of the first current source and the second current source to the first rod and the second rod in response to a pair to determine voltages of the first output node and the second output node; And

The common mode voltages of the first output node and the second output node are electrically connected to the first output node and the second output node, and the amount of common mode current flowing through the first rod and the second rod is controlled. A pulse amplitude modulation transmission driver comprising a common mode changer for determining a value.

The method of claim 1, wherein the common mode changing unit,

And change the common mode current in response to a differential input pair of an exclusive logical sum (XOR) of the 0th bit signal and the first bit signal.

The method of claim 1, wherein the common mode changing unit,

A third load connected in series between the voltage source and a third node;

A fourth rod connected in series between the voltage source and a fourth node;

A third current source electrically connected to the ground voltage; And

The first output node, the second output node, the third node, the fourth node, and the third node are configured to receive a differential input pair of an exclusive OR of the 0 bit signal and the first bit signal. A common mode electrically connected to a current source to supply the current of the third current source to the first rod and the second rod or to the third rod and the fourth rod according to the differential input pair of the exclusive OR; Pulse amplitude modulation transmit driver comprising a control unit.

The method of claim 3, wherein the common mode control unit,

At least one of a current electrically connected to the first output node, the third node, and the third current source and supplied to the first rod or the third rod from the third current source according to the exclusive OR-pair input pair; A first output common mode control unit which supplies a part; And

At least one of a current electrically connected to the second output node, the fourth node, and the third current source, and supplied to the second rod or the fourth rod from the third current source according to the exclusive-OR differential input pair; And a second output common mode control unit for supplying a portion thereof.

The method of claim 4, wherein

The first output common mode control unit,

A seventh transistor connected in series in a source / drain direction between the first output node and the third current source and receiving a positive input among the exclusive OR pairs; And

An eighth transistor connected in series in a source / drain direction between the third node and the third current source and receiving a negative input of the exclusive OR gate pair;

The second output common mode control unit,

A tenth transistor connected in series in a source / drain direction between the second output node and the third current source and receiving a positive input among the exclusive OR sum pairs; And

And a ninth transistor connected in series in a source / drain direction between the fourth node and the third current source and receiving a negative input of the exclusive OR gate pair.

The method of claim 4, wherein

The third current source includes a fourth current source and a fifth current source,

The fourth current source is connected in series between the first output common mode controller and the ground voltage,

The fifth current source is connected in series between the second output common mode controller and the ground voltage,

And the fourth current source and the fifth current source supply a current having the same magnitude.

The method of claim 1,

And wherein the first current source and the second current source supply currents of different magnitudes.

The method of claim 1, wherein the input data driver,

The first load or the second current being electrically connected to the first output node, the second output node, and the first current source to supply a current supplied from the first current source according to a differential input pair of the 0-bit signal; A 0-bit processor for supplying a load; And

The first load or the second current being electrically connected to the first output node, the second output node, and the second current source and supplied from the second current source according to a differential input pair of the first bit signal. And a first bit processing unit for supplying the load.

The method of claim 8,

The zero bit processing unit,

A first transistor connected in series in a source / drain direction between the first output node and the first current source and receiving a positive input among differential input pairs of the 0-bit signal; And

A second transistor connected in series in a source / drain direction between the second output node and the first current source and receiving a negative input among differential input pairs of the 0-bit signal;

The first bit processing unit,

A third transistor connected in series in a source / drain direction between the first output node and the second current source and receiving a positive input among differential input pairs of the first bit signal; And

And a fourth transistor connected in series in a source / drain direction between the second output node and the second current source and receiving a negative input of a differential input pair of the first bit signal.

The method of claim 9,

The second current source includes a sixth current source and a seventh current source,

The third transistor includes a twenty-third transistor and a twenty-fifth transistor electrically connected to a sixth current source and a seventh current source, respectively,

The fourth transistor includes a twenty-fourth transistor and a twenty-six transistor electrically connected to a sixth and seventh current sources, respectively,

The twenty-third to twenty-six transistors have the same channel width.

The method of claim 10,

And the sixth current source and the seventh current source supply a current having the same magnitude.

In the pulse amplitude modulation method,

A zero bit processing step of determining a voltage drop of any one of a first output node for determining a first output signal and a second output node for determining a second output signal according to the zero bit signal;

A first bit processing step of determining a voltage drop of any one of the first output node and the second output node according to a first bit signal; And

And a common mode changing step of changing a common mode level of the first output node and the second output node according to a combination of the 0th bit signal and the first bit signal.

The method of claim 12,

The first bit processing step may include bringing a voltage drop of the first output node when the first bit signal is the first logic level, and bringing a voltage drop of the second output node when the first bit signal is the second logic level. Coming pulse amplitude modulation method.

The method of claim 13,

The magnitude of the voltage drop caused by the zeroth bit signal and the voltage drop caused by the first bit signal are different from each other.

The method according to any one of claims 12 to 14,

The common mode changing step of changing the common mode of the first output node and the second output node in accordance with the exclusive logical sum (XOR) of the 0 bit signal and the first bit signal.

The method of claim 15,

The common mode changing step lowers the common mode level of the first output node and the second output node when the exclusive OR is true, and reduces the common mode level of the first output node and the second output node when the exclusive OR is false. Pulse amplitude modulation method that does not change the common mode level.

In a transmitter for transmitting a signal of n (even greater than zero) bits,

N / 2 exclusive logic gates for generating an exclusive OR (XOR) of the kth bit signal and the k + 1th bit signal for each k (even number less than n);

A first multiplexer for receiving the n / 2 exclusive ORs and outputting one of the exclusive ORs according to the value of k;

A second multiplexer for receiving the k-th bit signals for each k and outputting one of the k-th bit signals in accordance with the k value;

A third multiplexer for receiving the k + 1th bit signals for each k and outputting one of the k + 1th bit signals according to the k value;

A predriver for modulating the outputs of the first to third multiplexers with respective differential input pairs; And

Pulse amplitude modulation for receiving the respective differential input pairs and outputting a first output signal and a second output signal according to the differential input pairs of the kth bit signal, the k + 1th bit signal, and the exclusive logical sum; Including a send driver,

And the common mode level of the first output signal and the second output signal is changed according to the exclusive logical sum.

The pulse amplitude modulation transmission driver of claim 17, wherein

A first current source electrically connected to a ground voltage;

A second current source electrically connected to the ground voltage;

And electrically connected to the first output node, the second output node, the first current source, and the second current source, in response to a differential input pair of a zero bit signal and a differential input pair of a first bit signal. An input data driver for distributing currents of one current source and the second current source to the first rod and the second rod; And

A common mode electrically connected to the first output node and the second output node and supplying a common mode current to the first rod and the second load according to a combination of the first bit signal and the second bit signal; Transmitter comprising a change unit.

The pulse amplitude modulation transmission driver of claim 17, wherein

And a predetermined reference voltage having a magnitude between two levels depending on the common mode level.

In the pulse amplitude modulation reception driver,

A first bit signal discriminating unit for discriminating a first bit signal according to a polarity of a first differential amplifying output obtained by differentially amplifying a first input signal and a second input signal; And

Obtaining a second differential amplifier output differentially amplifying the first input signal and the reference voltage and a third differential amplifier output differentially amplifying the second input signal and the reference voltage, and calculating the second differential amplifier output according to the polarity of the first differential amplifier output. And a zero bit signal discrimination unit configured to select one of a second differential amplifier output and a third differential amplifier output to determine a zero bit signal.

The method of claim 20,

The zero bit signal determination unit,

A second differential amplifier for differentially amplifying the first input signal and a reference voltage to obtain the second differential amplifier output;

A third differential amplifier for differentially amplifying the second input signal and the reference voltage to obtain the third differential amplifier output; And

A pulse amplitude including a multiplexer configured to receive the second differential amplifier output and the third differential amplifier output and output one of the second differential amplifier output and the third differential amplifier output according to the polarity of the first differential amplifier output; Modulation Receive Driver.

The method of claim 21,

The first bit signal determination unit, the second differential amplifier, and the third differential amplifier,

An integrator that receives each differential input pair and outputs one of the output voltage pairs at a high level according to the input signal of the differential input pair;

A storage unit for receiving and storing an output pair of the integrator;

An amplifier for receiving and amplifying the output of the storage unit; And

And a latch for receiving and storing the output of the amplifier and outputting the stored data each time the completion signal is activated.

In the pulse amplitude modulation reception driver,

A first bit signal discrimination unit configured to compare the first input signal and the second input signal with a reference voltage, output a third output voltage and a fourth output voltage according thereto, and determine a zero bit signal according to the first bit signal; ,

The zero bit signal determination unit,

Receiving the first to second input signals and the reference voltage, and according to the relationship between the first input signal and the reference voltage, and the relationship between the second input signal and the reference voltage and the third output voltage and the fourth output voltage. A converter to generate;

An integrator configured to output one of a second output voltage pair at a high level according to the third output voltage and the fourth output voltage;

A storage unit to receive and store the second output voltage pair;

An amplifier for receiving and amplifying the output of the storage unit;

And a latch for receiving and storing the output of the amplifier.

The method of claim 23, wherein the converter,

When the first input signal and the second input signal are both lower than the reference voltage, the fourth output voltage has a voltage level higher than the third output voltage.

When the first input signal is lower than the reference voltage and the second input signal is higher than the reference voltage or when the first input signal is higher than the reference voltage and the second input signal is lower than the reference voltage. 3, the pulse amplitude modulation reception driver having an output voltage higher than the fourth output voltage.