CN217643335U

CN217643335U - Fast comparator, digital-analog hybrid circuit and vehicle-mounted controller

Info

Publication number: CN217643335U
Application number: CN202220559437.9U
Authority: CN
Inventors: 黄钧
Original assignee: Beijing Ziguang Xinneng Technology Co Ltd
Current assignee: Beijing Ziguang Xinneng Technology Co Ltd
Priority date: 2022-03-15
Filing date: 2022-03-15
Publication date: 2022-10-21
Anticipated expiration: 2032-03-15

Abstract

The application discloses quick comparator, digital-analog hybrid circuit and vehicle-mounted controller has realized the quick establishment of reference voltage that can dynamically adjust, has improved the operating voltage range and the comparison speed of comparator. The fast comparator comprises a digital logic circuit, a reference voltage generating circuit and a comparison circuit; the digital logic circuit outputs a reference voltage selection signal to the reference voltage generation circuit; the signal is a digital code value which is changed at regular time, the digital code value is N-bit binary number, and N is more than or equal to 2; the size, the output sequence and the time interval of the timing change of each digital code value are configured in advance; the reference voltage generating circuit establishes a reference voltage according to the received signal and then provides the reference voltage to the homodromous input end of the comparison circuit; the reference voltage generating circuit comprises an N-bit voltage mode R-2R resistor network; the comparison circuit comprises two stages of operational amplifiers, the front stage adopts rail-to-rail differential input operational amplifier, and the rear stage outputs 1-bit binary data by converting double ends of the high-speed operational amplifier into single ends.

Description

Fast comparator, digital-analog hybrid circuit and vehicle-mounted controller

Technical Field

The utility model relates to a power electronic technology field, more specifically say, relate to a fast comparator, digifax hybrid circuit and on-vehicle controller.

Background

The comparator is a circuit that compares an analog voltage signal with a reference voltage, and the comparison result is represented by the high and low of the output voltage. From the viewpoint that the two paths of inputs of the comparator are both analog signals, and the output is

binary signals

0 or 1, the comparator can also be used as a 1-bit analog-to-digital converter and is widely applied to various circuit systems.

The reference voltage generating circuit in the traditional comparator can only generate one or more than a few fixed reference voltages, and cannot realize the quick establishment of the reference voltage which can be dynamically adjusted, so that the working voltage range and the comparison speed of the comparator are limited.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model provides a fast comparator, digifax hybrid circuit and vehicle-mounted controller to realize the quick establishment of reference voltage that can dynamically regulated, improve the operating voltage range and the comparative speed of comparator.

A fast comparator, comprising: a digital logic circuit, a reference voltage generating circuit and a comparison circuit;

the digital logic circuit is used for outputting a reference voltage selection signal to the reference voltage generating circuit when an enabling signal is effective; the reference voltage selection signal is a digital code value which is changed at regular time, the digital code value is N-bit binary number, and N is more than or equal to 2; the size, the output sequence and the timing change time interval of each digital code value are all configured in advance;

the reference voltage generating circuit is used for establishing reference voltage according to the received reference voltage selection signal and then providing the reference voltage to the homodromous input end of the comparison circuit; the reference voltage generating circuit comprises an N-bit voltage mode R-2R resistor network;

the comparison circuit is used for comparing the input voltage received by the reverse input end with the reference voltage received by the same-direction input end and outputting one-bit binary data; the comparison circuit comprises two stages of operational amplifiers, the front stage operational amplifier adopts a rail-to-rail differential input operational amplifier, and the rear stage operational amplifier directly converts a comparison result into 1-bit binary data through the high-speed operational amplifier with double ends converting into a single end.

Optionally, the N-bit voltage mode R-2R resistor network is a segmented R-2R resistor network.

Optionally, each two-select switch in the N-bit voltage mode R-2R resistor network is replaced with a driving circuit unit;

the driving circuit unit includes: the power supply end and the ground end of the M-level push-pull circuit are respectively connected with a second power supply and the ground; the size of an MOS tube in the multistage push-pull circuit is increased step by step;

the input end of each inverter receives one bit of the reference voltage selection signal, and the output end of each M-level push-pull circuit is connected with one end of one resistor 2R in the N-bit voltage mode R-2R resistor network.

Optionally, an inverter in the driving circuit unit is omitted, and an input terminal of each M-stage push-pull circuit receives one bit of the reference voltage selection signal.

Optionally, M is equal to 2, 3 or 4.

Optionally, the digital logic circuit is configured to delay for a preset time and output a reference voltage selection signal to the reference voltage generation circuit when the enable signal is valid.

Optionally, the pre-stage operational amplifier includes two current sources I1 and I4, six PMOS transistors MP1 to MP6, and six NMOS transistors MN1 to MN6; the rear-stage operational amplifier comprises two current sources I2 and I3, two PMOS tubes MP 7-MP 8, three NMOS tubes MN 7-MN 9 and an inverter INV1;

the input end of a current source I1 and the source electrodes of PMOS tubes MP 3-MP 6 are connected with a third power supply VDD1, the output end of the current source I1 is connected with the source electrodes of the PMOS tubes MP 1-MP 2, the grid electrodes of the PMOS tube MP1 and the NMOS tube MN1 are both connected with the in-phase input end of the comparison circuit, the grid electrodes of the PMOS tube MP2 and the NMOS tube MN2 are both connected with the inverting input end of the comparison circuit, the drain electrode of the PMOS tube MP1 is connected with the drain electrode of the PMOS tube MP5, the drain electrode of the NMOS tube MN6, the grid electrode of the NMOS tube MN6, the drain electrode of the NMOS tube MN5, the grid electrode of the NMOS tube MN4 and the grid electrode of the PMOS tube MP8, the drain electrode of the PMOS tube MP2 is connected with the drain electrode of the PMOS tube MP4, the drain electrode of the NMOS tube MN3, the grid electrode of the NMOS tube MN3, the drain electrode of the NMOS tube MN4, the grid electrode of the PMOS tube MP5 and the grid electrode of the PMOS tube MP7, the drain electrode of the NMOS tube MP1 is connected with the drain electrode of the PMOS tube MP3, the drain electrode of the PMOS tube MP2 is connected with the drain electrode of the PMOS tube MP6, the drain electrode of the NMOS tube MP6 and the grid electrode of the NMOS tube MP5, and the drain electrode of the PMOS tube MP2 are grounded; the source electrodes of the NMOS tubes MN 3-MN 6 are grounded with VSS;

the input ends of the current sources I2 to I3 and the power end of the inverter INV1 are connected with a third power VDD1, the output end of the current source I2 is connected with the source electrodes of PMOS tubes MP7 to MP8, the drain electrode of the PMOS tube MP7 is connected with the drain electrode of the NMOS tube MN7, the grid electrode of the NMOS tube MN7 and the grid electrode of the NMOS tube MN8, the drain electrode of the PMOS tube MP8 is connected with the drain electrode of the NMOS tube MN8 and the grid electrode of the NMOS tube MN9, and the source electrodes of the NMOS tubes MN7 to MN9 and the ground end of the inverter INV1 are connected with a VSS; the output end of the current source I3 is connected with the drain electrode of the NMOS tube MN9 and the input end of the inverter INV1; the output end of the inverter INV1 is the output end of the comparison circuit.

Optionally, the fast comparator further includes a channel selection circuit; the channel selection circuit is used for receiving an input voltage provided by the outside from a chip pin and then transmitting the input voltage to the reverse input end of the comparison circuit through the multichannel channel selection switch.

A digital-to-analog hybrid circuit, comprising: any of the fast comparators disclosed above.

An onboard controller comprising: any of the digital-to-analog hybrid circuits disclosed above.

According to the technical scheme, the utility model discloses utilize N position voltage mode R-2R resistance network as reference voltage generating circuit, realized the quick establishment of reference voltage that can dynamically adjust; meanwhile, the front stage of the comparison circuit adopts rail-to-rail differential input operational amplifier, so that the full-swing input range of the comparator is realized; the rear stage directly converts the comparison result into a 1-bit binary signal through the high-speed operational amplifier double-end to single-end conversion, and the fast conversion rate of the comparator is guaranteed. The reference voltage is quickly established and compared with the comparison circuit quickly, so that the working voltage range and the comparison speed of the comparator are improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a fast comparator according to an embodiment of the present invention;

FIG. 2 is a timing diagram of signals of the fast comparator shown in FIG. 1;

fig. 3 is a schematic diagram of a reference voltage generating circuit according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a reference voltage generating circuit according to another embodiment of the present invention;

fig. 5 is a schematic diagram of a reference voltage generating circuit according to another embodiment of the present invention;

fig. 6 is a schematic structural diagram of a driving circuit unit according to an embodiment of the present invention;

fig. 7 is a graph showing the variation of the reference voltage VIP and the input voltage VIN;

fig. 8 is a schematic diagram of a comparison circuit structure according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1, an embodiment of the present invention discloses a fast comparator, which comprises: a digital logic circuit 1, a reference voltage generating circuit 2 and a comparison circuit 3. The following is a detailed description of the structure and connection relationship of the constituent elements:

1) Digital logic circuit 1

The digital logic circuit 1 is configured to output a reference voltage selection signal REF to the reference voltage generation circuit 2 when the enable signal EN is active; the reference voltage selection signal REF is a digital code value which is changed at fixed time, the digital code value is N (N is more than or equal to 2) bit binary number, and the size, the output sequence and the time interval of the fixed time change of each digital code value are configured in advance.

The time interval is set to be short to ensure a fast change of the digital code value, for example: the digital logic circuit 1 may set the time interval to four clock cycles with reference to the high-speed clock CLK whose oscillation frequency is in the range of 50MHz to 200 MHz.

Digital logic circuit 1 can be immediately to reference voltage generating circuit 2 output reference voltage selection signal REF when enabling signal EN is effective, but considers that doing so leads to reference voltage selection signal REF to generate the initial stage and appear the shake easily, consequently the embodiment of the utility model provides a recommend digital logic circuit 1 when enabling signal EN is effective, output reference voltage selection signal REF to reference voltage generating circuit 2 again after the time delay is preset.

The timing diagram of the signals of the fast comparator is shown in fig. 2, for example. Fig. 2 shows the timing of the high-speed clock CLK, the enable signal EN (for example, the enable signal EN is active at a high level), and the reference voltage selection signal REF (for example, the reference voltage selection signal REF is output after a delay of one clock cycle when the enable signal EN is active, and digital code values are changed every four clock cycles, where the first two digital code values are 10-bit binary numbers 1000000001 and 10-bit binary numbers 1000000010, respectively).

2) Reference voltage generating circuit 2

The reference voltage generating circuit 2 is used for establishing a reference voltage VIP according to a received reference voltage selection signal REF, and then providing the reference voltage VIP to a non-inverting input terminal of the comparison circuit 3.

The reference voltage generating circuit in the conventional comparator usually uses a resistor series voltage division form, as shown in fig. 3, a plurality of resistors R are connected in series between a power source VREF and a ground VGND, and an output voltage VIP is obtained after selection by a switch. Fig. 3 is suitable for the case that the reference voltage is only a few, and the advantage of this form is that the circuit is simple, the layout area is small, and the matching is easy. However, if the reference voltage is hundreds or even thousands of reference voltages, hundreds or thousands of resistors and switches are needed to be used in fig. 3, which causes the circuit cost of the reference voltage generation circuit to be extremely high, the layout area to be huge, and the matching to be difficult to be done.

In order to obtain a large amount of reference voltage on the premise of ensuring low cost, small layout area and easy matching, a novel reference voltage generating circuit can be designed, an N-bit voltage mode R-2R resistor network is adopted, and as shown in figure 4, the N-bit voltage mode R-2R resistor network comprises N-1 resistors R, N +1 resistors 2R and N two-way switches b ₁ ～b _N 。b ₁ b ₂ ……b _N Combined to represent an N-bit binary number, the N-th bit, i.e. the most significant bit, of which is b ₁ The first, lowest bit of the N-bit binary number is b _N When the switch is one of two _i (i =1, 2, …, N) and ground VGND _i =0, when the switch b is one of two switches _i When connected to the power source VREF b _i =1, select signal REF pair b by reference voltage ₁ 、b ₂ 、……b _N After the switch selection is carried out, the output voltage VIP of the reference voltage generation circuit is obtained, and the voltage VIP formula is as follows:

VIP＝(b ₁ 2 ^-1 +b ₂ 2 ^-2 +…+b _N 2 ^-N )(VREF-VGND)

for example, when N =10 is set, pair b ₁ 、b ₂ 、……b _N Can be combined into 2 after switch selection ¹⁰ A reference voltage VIP, assuming that the reference voltage selection signal REF is a 10-bit binary number of 1000000000

FIG. 3 requires 1024 resistors R and 1024 switches to combine 2 ¹⁰ A reference voltage VIP, whereas FIG. 4 only requires 9 resistors R11 resistors 2R and 10 alternative switches can be combined to form 2 ¹⁰ The number of resistors and switches used by the reference voltage VIP is greatly reduced, the area of a layout can be well reduced, the circuit cost is lower, and the matching is easier.

Optionally, when the number of bits is large, the N-bit voltage mode R-2R resistor network may also adopt a resistor segmentation mode, which is called a segmented R-2R resistor network, and a topology structure of the segmented R-2R resistor network is a circuit topology structure known in the art, and is not described herein again.

Optionally, each two-way switch in the N-bit voltage mode R-2R resistor network/segmented R-2R resistor network may be replaced with a driving circuit unit, for example, as shown in fig. 5 (fig. 5 only takes as an example that each two-way switch in the N-bit voltage mode R-2R resistor network is replaced with a driving circuit unit), the driving circuit unit includes an inverter and an M-level push-pull circuit, an output terminal of the inverter is connected to an input terminal of the M-level push-pull circuit, a power supply terminal and a ground terminal of the inverter are respectively connected to the power supply VDD and the ground VGND, a power supply terminal and a ground terminal of the M-level push-pull circuit are respectively connected to the ground VGND of the power supply, and M is greater than or equal to 1. The size of the MOS tube in the multistage push-pull circuit is increased in a stepwise mode so as to prevent overshoot when the VREF voltage is selected. The larger M is, the stronger the anti-interference capability is, but the higher the cost is, and the setting of M is more than or equal to 2 and less than or equal to 4 is generally recommended. Fig. 5 is a schematic structural diagram of an inverter + multistage push-pull circuit, taking M =1 as an example only, and fig. 6 is a schematic structural diagram of an inverter + multistage push-pull circuit.

Still referring to FIG. 5, the N + 1-i-th driving circuit unit (denoted by D in FIG. 5) _N+1-i Indicating that the input end of the inverter in i =1, 2, …, N) receives the i-th bit of the reference voltage selection signal REF, and the output end of the M-stage push-pull circuit in each driving circuit unit is connected to one end of one resistor 2R; in fig. 5, N +1 resistors 2R are provided in total, and the resistor 2R connected to the (N + 1) -i th driving circuit unit is referred to as the (N + 1) -i) th resistor 2R, and the remaining one resistor 2R is referred to as the (N + 1) -th resistor 2R, so that the other end of the 1 st resistor 2R is used for outputting the voltage VIP, a resistor R is further connected between the other end of the 1 st resistor 2R and the other end of the 2 nd resistor 2R, a resistor R is connected between the other end of the 2 nd resistor 2R and the other end of the 3 rd resistor 2R, and … … is provided between the other end of the 2 nd resistor 2R and the other end of the 3 rd resistor 2RThe other end of the (N-1) th resistor 2R is connected with the other end of the (N + 1) th resistor 2R through a resistor R, and the other end of the (N + 1) th resistor 2R is grounded. Since the reference voltage selection signal REF has a high-speed clock timing, in order to prevent noise interference caused by the reference voltage selection signal REF, the inverter uses another power supply VDD having a voltage value equal to VREF, so that interference of the high-speed clock timing with VREF can be effectively isolated. The push-pull circuit is used for improving the driving capability of an output signal and pushing the following R-2R resistor string to quickly establish VIP voltage, so that the aim of quickly generating a final comparison result DOUT is fulfilled. Fig. 7 is a variation curve of the reference voltage VIP and the input voltage VIN, which are obtained by the present invention and vary rapidly under a certain working condition.

Optionally, in an occasion that the requirement for noise interference caused by a high-speed clock timing is not high, the inverter in the driving circuit unit may also be omitted.

3) Comparison circuit 3

The inverting input terminal of the comparison circuit 3 receives an input voltage VIN; the comparison circuit 3 is configured to compare the input voltage VIN with the reference voltage VIP, output one-bit binary data DOUT, sequentially output the binary data DOUT to the result processing module, and finally send the processed data to the chip system.

Optionally, the comparison circuit 3 comprises two stages of operational amplifiers. The pre-stage operational amplifier adopts a rail-to-rail differential input operational amplifier to realize the full swing range (namely from a power supply to the ground) input range of the comparator; the rear-stage operational amplifier directly converts the comparison result into a 1-bit binary signal through the high-speed operational amplifier from double ends to single ends, and the rapid conversion rate of the comparator is guaranteed.

As shown in fig. 8, the pre-stage operational amplifier includes two current sources I1 and I4, six PMOS transistors MP1 to MP6, and six NMOS transistors MN1 to MN6; the post-stage operational amplifier comprises two current sources I2 and I3, two PMOS tubes MP 7-MP 8, three NMOS tubes MN 7-MN 9 and an inverter INV1;

the input end of a current source I1 and the source electrodes of PMOS tubes MP 3-MP 6 are connected with a third power supply VDD1, the output end of the current source I1 is connected with the source electrodes of the PMOS tubes MP 1-MP 2, the grid electrodes of the PMOS tube MP1 and the NMOS tube MN1 are both connected with the in-phase input end VIP of a comparison circuit 3, the grid electrodes of the PMOS tube MP2 and the NMOS tube MN2 are both connected with the inverted input end VIN of the comparison circuit 3, the drain electrode of the PMOS tube MP1 is connected with the drain electrode of the PMOS tube MP5, the drain electrode of the NMOS tube MN6, the grid electrode of the NMOS tube MN6, the drain electrode of the NMOS tube MN5, the grid electrode of the NMOS tube MN4 and the grid electrode of the PMOS tube MP8, the drain electrode of the PMOS tube MP2 is connected with the drain electrode of the PMOS tube MP4, the drain electrode of the NMOS tube MN3, the grid electrode of the NMOS tube MN3, the drain electrode of the NMOS tube MN4, the grid electrode of the PMOS tube MP5 and the grid electrode of the PMOS tube MP7, the drain electrode of the NMOS tube MN1 is connected with the drain electrode of the PMOS tube MP3, the drain electrode of the PMOS tube MP2 is grounded through the VSS of the NMOS tube MP6, the drain electrode of the PMOS tube MP6 and the grid electrode of the NMOS tube MP 2; the source electrodes of the NMOS tubes MN3 to MN6 are grounded to VSS;

the input ends of the current sources I2 to I3 and the power end of the inverter INV1 are connected with a third power VDD1, the output end of the current source I2 is connected with the source electrodes of PMOS tubes MP7 to MP8, the drain electrode of the PMOS tube MP7 is connected with the drain electrode of the NMOS tube MN7, the grid electrode of the NMOS tube MN7 and the grid electrode of the NMOS tube MN8, the drain electrode of the PMOS tube MP8 is connected with the drain electrode of the NMOS tube MN8 and the grid electrode of the NMOS tube MN9, and the source electrodes of the NMOS tubes MN7 to MN9 and the ground end of the inverter INV1 are connected with a VSS; the output end of the current source I3 is connected with the drain electrode of the NMOS tube MN9 and the input end of the inverter INV1; the output end of the inverter INV1 is the output end of the comparison circuit 3.

In fig. 7, the input terminal of the preceding operational amplifier is composed of MOS transistors MP1, MP2, MN1, MN2 and current sources I1, I4, and it adopts a rail-to-rail differential input structure, thereby implementing the full swing input range of the comparison circuit. The output end of the preceding operational amplifier is composed of MOS tubes MP3, MP4, MP5, MP6, MN3, MN4, MN5 and MN6, two bias current source output stages are formed, and signals which are amplified rapidly can be provided for the subsequent operational amplifier. The rear-stage operational amplifier is composed of MOS tubes MP7, MP8, MN7, MN8 and MN9 and current sources I2 and I3, a five-tube operational amplifier structure is used, double-end signals input to the MP7 and the MP8 are converted into single-end signals, the single-end signals are shaped through an inverter INV1, finally comparison results are converted into 1-bit binary logic signals to be output, and the fast conversion rate of the comparison circuit is guaranteed.

As can be seen from the above description, the present invention utilizes an N-bit voltage mode R-2R resistor network as a reference voltage generating circuit, which realizes the fast establishment of dynamically adjustable reference voltage; meanwhile, the front stage of the comparison circuit adopts a rail-to-rail differential input operational amplifier, so that the full swing range (namely from a power supply to the ground) of the comparator is realized; the rear stage directly converts the comparison result into a 1-bit binary signal through the high-speed operational amplifier double-end to single-end conversion, and the fast conversion rate of the comparator is guaranteed. The reference voltage is quickly established and compared with the comparison circuit quickly, so that the working voltage range and the comparison speed of the comparator are improved.

Optionally, the fast comparator further includes: a channel selection circuit. The channel selection circuit is used for receiving an externally provided input voltage from a chip pin, and transmitting the voltage VIN to an inverted input end of the comparison circuit 3 through the multipath channel selection switch.

Optionally, the utility model also discloses a digital-analog hybrid circuit, include: any of the fast comparators disclosed above.

Optionally, the utility model also discloses an on-vehicle controller, including any kind of digifax hybrid circuit that the above-mentioned was disclosed. At the moment, the application requirements of peak current detection, zero current detection, braking and the like in the vehicle-mounted controller can be met.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the embodiments of the invention. Thus, the present embodiments are not intended to be limited to the embodiments shown herein but are to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A fast comparator, comprising: a digital logic circuit, a reference voltage generating circuit and a comparison circuit;

the digital logic circuit is used for outputting a reference voltage selection signal to the reference voltage generating circuit when the enable signal is effective; the reference voltage selection signal is a digital code value which is changed at regular time, the digital code value is an N-bit binary number, and N is more than or equal to 2; the size, the output sequence and the timing change time interval of each digital code value are all configured in advance;

the reference voltage generating circuit is used for establishing a reference voltage according to the received reference voltage selection signal and then providing the reference voltage to the homodromous input end of the comparison circuit; the reference voltage generating circuit comprises an N-bit voltage mode R-2R resistor network;

the comparison circuit is used for comparing the input voltage received by the reverse input end with the reference voltage received by the same-direction input end and outputting one-bit binary data; the comparison circuit comprises two stages of operational amplifiers, the front stage operational amplifier adopts a rail-to-rail differential input operational amplifier, and the rear stage operational amplifier directly converts a comparison result into 1-bit binary data by converting double ends of the high-speed operational amplifier into a single end.

2. The fast comparator as claimed in claim 1, wherein the N-bit voltage mode R-2R resistor network employs a segmented R-2R resistor network.

3. The fast comparator as claimed in claim 1 or 2, wherein each of the two-out switches in the N-bit voltage mode R-2R resistor network is replaced with a driving circuit unit;

4. The fast comparator according to claim 3, wherein the inverter in the driving circuit unit is omitted, and each of the inputs of the M-stage push-pull circuits receives one bit of the reference voltage selection signal.

5. The fast comparator as claimed in claim 4, wherein M is equal to 2, 3 or 4.

6. The fast comparator as claimed in claim 1, wherein the digital logic circuit is configured to delay the output of the reference voltage selection signal to the reference voltage generation circuit for a predetermined time when the enable signal is asserted.

7. The fast comparator according to claim 1, wherein the pre-stage operational amplifier comprises two current sources I1 and I4, six PMOS transistors MP 1-MP 6 and six NMOS transistors MN 1-MN 6; the rear-stage operational amplifier comprises two current sources I2 and I3, two PMOS tubes MP 7-MP 8, three NMOS tubes MN 7-MN 9 and an inverter INV1;

the input end of a current source I1 and the source electrodes of PMOS tubes MP 3-MP 6 are connected with a third power supply VDD1, the output end of the current source I1 is connected with the source electrodes of the PMOS tubes MP 1-MP 2, the grid electrodes of the PMOS tube MP1 and the NMOS tube MN1 are connected with the in-phase input end of the comparison circuit, the grid electrodes of the PMOS tube MP2 and the NMOS tube MN2 are connected with the inverting input end of the comparison circuit, the drain electrode of the PMOS tube MP1 is connected with the drain electrode of the PMOS tube MP5, the drain electrode of the NMOS tube MN6, the grid electrode of the NMOS tube MN6, the drain electrode of the NMOS tube MN5, the grid electrode of the NMOS tube MN4 and the grid electrode of the PMOS tube MP8, the drain electrode of the PMOS tube MP2 is connected with the drain electrode of the PMOS tube MP4, the drain electrode of the NMOS tube MN3, the grid electrode of the NMOS tube MN3, the drain electrode of the NMOS tube MN4, the grid electrode of the PMOS tube MP5 and the grid electrode of the NMOS tube MP7, the drain electrode of the NMOS tube MN1 is connected with the drain electrode of the PMOS tube MP3, the drain electrode of the NMOS tube MP2 of the PMOS tube MP6 and the grid electrode of the NMOS tube MP5, and the grid electrode of the NMOS tube MP2 are grounded through the drain electrode of the PMOS tube MP 2; the source electrodes of the NMOS tubes MN 3-MN 6 are grounded with VSS;

8. The fast comparator according to claim 1, further comprising a channel selection circuit; the channel selection circuit is used for receiving an input voltage provided by the outside from a chip pin and then transmitting the input voltage to the reverse input end of the comparison circuit through the multi-channel selection switch.

9. A digital-to-analog hybrid circuit, comprising: the fast comparator as claimed in any one of claims 1 to 8.

10. An onboard controller, comprising: a digital to analog hybrid according to claim 9.