JPS62284524A - Complementary type mos integrated circuit - Google Patents
Complementary type mos integrated circuitInfo
- Publication number
- JPS62284524A JPS62284524A JP61128367A JP12836786A JPS62284524A JP S62284524 A JPS62284524 A JP S62284524A JP 61128367 A JP61128367 A JP 61128367A JP 12836786 A JP12836786 A JP 12836786A JP S62284524 A JPS62284524 A JP S62284524A
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- JP
- Japan
- Prior art keywords
- channel mos
- circuit
- mos transistor
- output
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 230000000295 complement effect Effects 0.000 title claims description 12
- 238000010586 diagram Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明は相補型ＭＯＳ集積回路（以下ＣＭＯＳ回路）に
関し、特に高速化を図る等の理由で出力回路のドライバ
能力を大きく設定した場合でもノイズの発生を低減でき
るものに関するものである。[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a complementary MOS integrated circuit (hereinafter referred to as a CMOS circuit), and particularly relates to a complementary MOS integrated circuit (hereinafter referred to as a CMOS circuit). This relates to something that can reduce the generation of noise even when the value is set to a large value.
第３図はＣＭＯ５出力回路を示し、図において５．１は
入力端子、２は出力端子、３は電圧ＶＣＣの電源が供給
される電源端子、４はグランド（ＧＮＤ）端子、５は第
１のｐチャネルＭＯＳトランジスタ、６は第１のｎチャ
ネルＭＯＳ）ランジスクである。Figure 3 shows the CMO5 output circuit, in which 5.1 is an input terminal, 2 is an output terminal, 3 is a power supply terminal to which power of voltage VCC is supplied, 4 is a ground (GND) terminal, and 5 is a first terminal. A p-channel MOS transistor, 6 is a first n-channel MOS transistor.
このようなＣＭＯＳ回路では、入力端子ｌの入力電圧が
ＧＮ０１１位である時はｐチャネルＭＯＳトランジスタ
５がオンし、ｎチャネルＭｏ５１〜ランジスタロがオフ
し、出力端子２はＶＣＣの電位となる。逆に入力電圧が
ＶＣＣ電位である時、ｐチャネルＭＯＳトランジスタ５
がオフし、ｎチャネルＭＯＳトランジスタロがオンし、
出力端子２はＧＮＤ電位となる。入力電位がＧＮＤとＶ
ＣＣＯ間にある時は、ｐチャネルＭｏＳトランジスタ５
とｎチャネルＭＯＳＩ−ランジスタロのオン抵抗比によ
り出力端子２の電位が決定される。In such a CMOS circuit, when the input voltage of the input terminal 1 is about GN011, the p-channel MOS transistor 5 is turned on, the n-channel Mo51 to transistor are turned off, and the output terminal 2 has the potential of VCC. Conversely, when the input voltage is at VCC potential, the p-channel MOS transistor 5
turns off, the n-channel MOS transistor turns on,
Output terminal 2 is at GND potential. Input potential is GND and V
When between CCO, p-channel MoS transistor 5
The potential of the output terminal 2 is determined by the on-resistance ratio of the n-channel MOSI and transistor.
第４図は、第３図の回路に於ける貫通電流（Ｉ６．）対
入力電圧（ＶＩＮ）の関係を示す図である。FIG. 4 is a diagram showing the relationship between the through current (I6.) and the input voltage (VIN) in the circuit of FIG.
図中■７□はｎチャネルＭＯＳトランジスタ６のしきい
値電圧、Ｖ Ｔ １１ ＰはｐチャネルＭＯＳトランジ
スタのしきい値電圧である。同図に示す様に、通常は入
力電位がおよそ１／２Ｖｃｃの時に貫通電流（Ｉ ｃｃ
）の値がピークをもつ様にｐチャネルＭＯＳトランジス
タ５及びｎチャネルＭＯＳトランジスタロのトランジス
タサイズが決定されている。In the figure, ■7□ is the threshold voltage of the n-channel MOS transistor 6, and V T 11 P is the threshold voltage of the p-channel MOS transistor. As shown in the figure, normally when the input potential is approximately 1/2 Vcc, the through current (Icc
) The transistor sizes of the p-channel MOS transistor 5 and the n-channel MOS transistor 5 are determined so that the value of ) has a peak.
第５図は、出力回路を駆動する出力前段回路を含めた回
路図であり、第２のｐチャネルＭＯＳトランジスタ７及
び第２のｎチャネルＭＯＳトランジスタ８により、第３
図に示す出力回路が駆動される。第７図は、上記ＣＭＯ
Ｓ出力回路が基板に実装された場合の回路図であり、Ｖ
ＣＣ端子３と外部電源ＶＣＣ及びＧＮＤ端子４の外部電
源のＧＮＤとの間には、Ｌ成分（集積回路内のフレーム
、金線、プリント基板の配線にできるＬ成分）が入って
しまう。FIG. 5 is a circuit diagram including a pre-output circuit that drives the output circuit, in which a third p-channel MOS transistor 7 and a second n-channel MOS transistor 8 are used.
The output circuit shown in the figure is driven. Figure 7 shows the above CMO
This is a circuit diagram when the S output circuit is mounted on a board, and V
Between the CC terminal 3 and the external power supply VCC and the GND of the external power supply of the GND terminal 4, an L component (an L component formed in the frame in the integrated circuit, the gold wire, and the wiring on the printed circuit board) is introduced.
最近の高速化要求に伴い、出力回路を構成するＭＯＳト
ランジスタの電流容量（ドライブ能力）は、非常に大き
く設定されてきている（例えばＶｃｃ”５Ｖで２００〜
３０ｍＡ）ので、それニつれて、既に述べられた貫通電
流も増大し、第７図に示す回路に於いて、し成分により
発生するスパイク電圧
す事が多くなってきている。第８図は出力端子２の波形
の一例で横軸は時間、縦軸は電圧を示し、この図かられ
かるように回路の“Ｌ″−“Ｈ”。With the recent demand for higher speeds, the current capacity (drive capacity) of the MOS transistors that make up the output circuit has been set to be extremely large (for example, 200 to
30 mA), the through current mentioned above also increases, and in the circuit shown in FIG. 7, spike voltages generated by the ion component are becoming more common. FIG. 8 is an example of the waveform of the output terminal 2, where the horizontal axis shows time and the vertical axis shows voltage, and as can be seen from this figure, the "L"-"H" of the circuit.
又は′Ｈ”−”Ｌ”への動作時に大きなスパイクノイズ
が発生し、この回路で駆動する他の回路が誤動作を引き
起こすという問題点があった。Alternatively, there is a problem in that a large spike noise is generated during the operation from 'H' to 'L', causing malfunction of other circuits driven by this circuit.
この発明は上記の問題点を解決する為になされたもので
、出力回路を構成するＭＯＳトランジスタのドライブ能
力を上げた時でも、貫通電流の増加を抑え、スイッチン
グ（動作）時のスパイクノイズを低減すると共に、貫通
電流の増加による消費電力の増加をも抑えた相補型ＭＯ
Ｓ集積回路を提供することを目的とする。This invention was made to solve the above problems. Even when the drive capacity of the MOS transistors that make up the output circuit is increased, the increase in through current is suppressed and spike noise during switching (operation) is reduced. At the same time, it is a complementary MO that suppresses the increase in power consumption due to the increase in through current.
The purpose of the present invention is to provide an S integrated circuit.
この発明に係る相補型ＭＯ５集積回路装置は、出力回路
を駆動する出力前段回路を、ｐチャネルＭＯ５トランジ
スタと、ｎチャネルＭＯＳトランジスタと、該２つのト
ランジスタ間に直列に接続された抵抗器とから構成した
ものである。In the complementary MO5 integrated circuit device according to the present invention, the output pre-stage circuit that drives the output circuit is composed of a p-channel MO5 transistor, an n-channel MOS transistor, and a resistor connected in series between the two transistors. This is what I did.
この発明においては、上記出力前段回路をすをヤネルＭ
ＯＳトランジスタと、該２つのトランジスタ間に直列に
接続された抵抗器とから構成したから、出力回路のスイ
ッチング時の貫通電流を減少させ、これによりスイッチ
ング時のスパイクノイズの減少と共に消費電力の低減を
図ることができる。In this invention, the output pre-stage circuit is
Since it is composed of an OS transistor and a resistor connected in series between the two transistors, the through current during switching of the output circuit is reduced, thereby reducing spike noise during switching and reducing power consumption. can be achieved.
以下本発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例による相補型ＭＯＳ集積回路
の出力回路及び出力前段回路を示し、図において、第５
図と同一符号は同一のものを示し、９は出力前段回路の
第２のｐチャネルＭＯＳＩ−ランジスタつのドレインと
第２のｎチャネルＭＯＳトランジスタ８のドレインとの
間に挿入されたアナログスイッチであり、これはソース
・ドレインがそれぞれ共通な第３のｎチャネルＭＯＳト
ランジスタ１０と第３のｎチャネルＭＯＳＩ−ランジス
タ１１から構成されている。ここで上記第３のｐチャネ
ルＭＯＳトランジスタ１０のゲートはグランドに上記第
３のｎチャネルＭＯＳトランジスタ１１のゲートは電源
に接続されている。FIG. 1 shows an output circuit and a pre-output circuit of a complementary MOS integrated circuit according to an embodiment of the present invention.
The same reference numerals as in the figure indicate the same things, and 9 is an analog switch inserted between the drain of the second p-channel MOS transistor 8 and the drain of the second n-channel MOS transistor 8 of the output pre-stage circuit. This is composed of a third n-channel MOS transistor 10 and a third n-channel MOS I-transistor 11, each having a common source and drain. Here, the gate of the third p-channel MOS transistor 10 is connected to the ground, and the gate of the third n-channel MOS transistor 11 is connected to the power supply.
次に作用効果について説明する。Next, the effects will be explained.
まず、第５図の従来例について貫通電流の値を検討する
。第６図は、第５図の出力前段回路部の等価回路図で、
抵抗Ｒ１０７はｐチャネルＭＯＳトランジスタ７のオン
抵抗を表し、抵抗Ｒ１０８はｎチャネルＭＯＳトランジ
スタ８のオン抵抗を表す、また表１は、入力電圧（Ｖ’
、４）を０からＶＣ迄変化させた時のそれぞれ抵抗Ｒ１
０７，Ｒ１０８のオン抵抗値の変化を説明し易い様に基
準化して決めたものを示す。First, the value of the through current for the conventional example shown in FIG. 5 will be examined. FIG. 6 is an equivalent circuit diagram of the output pre-stage circuit section of FIG.
Resistor R107 represents the on-resistance of p-channel MOS transistor 7, resistor R108 represents the on-resistance of n-channel MOS transistor 8, and Table 1 shows the input voltage (V'
, 4) respectively when changing from 0 to VC.
07 and R108 are standardized and determined to facilitate explanation of the change in on-resistance value.
表１
例えばＶＩＮが０ （Ｖ）（Ｄ時、Ｒ１０７（７）抵抗
値を１とし■、がＶｌ （Ｖ）の時１０・・・・・・
と決めている。第５図に於いて出力回路のＭＯＳトラン
ジスタ５．６のゲート電圧は同電位で、表１の下段に示
した■。□ ＶＧＨの電圧となる。この例では貫通電流
のピークは入力電圧がｖ２の時で、この時出力回路の両
ＭＯＳトランジスタのゲート電圧は５０／１００ Ｖｃ
ｃすなわち１／２Ｖｃｃとなり、出力回路に流れる貫通
電流は次式の様に表せる。Table 1 For example, when VIN is 0 (V) (D, R107 (7) resistance value is 1, and when is Vl (V), it is 10...
I have decided that. In FIG. 5, the gate voltages of MOS transistors 5 and 6 in the output circuit are at the same potential, and are shown in the lower part of Table 1. □ The voltage becomes VGH. In this example, the peak of the through current is when the input voltage is v2, and at this time the gate voltage of both MOS transistors in the output circuit is 50/100 Vc.
c, that is, 1/2 Vcc, and the through current flowing in the output circuit can be expressed as in the following equation.
？
にはコンタクタンス係数、■７１１はＭＯＳトランジス
タのしきい値電圧である。なお、ここでは、ｐチャネル
ＭＯＳトランジスタ５とｎチャネルＭＯＳトランジスタ
６のコンダクタンス係数及びしきいチャネル電圧は同じ
としている。例えばＶ（ｃ＝５ Ｖ、 Ｖｔ、ｌ−０
，７Ｖとするととなる。? is the contactance coefficient, and 711 is the threshold voltage of the MOS transistor. Here, it is assumed that the conductance coefficient and threshold channel voltage of p-channel MOS transistor 5 and n-channel MOS transistor 6 are the same. For example, V (c=5 V, Vt, l-0
, 7V.
次に第１図の実施例について同様に貫通電流の値を検討
する。第２図は従来例の第６図に相当し、Ｒ１０７とＲ
１０８の間に抵抗Ｒ１０９が挿入されており、出力回路
のｐチャネルＭＯＳトランジスタ５とｎチャネルＭＯＳ
Ｉ−ランジスタロとではゲートに印加される電位が異な
る。なお、抵抗Ｒ１０９は第１図に於けるアナログスイ
ッチ９のオン抵抗を表す。ここでＶＧＰＩＩＯはｐチャ
ネルＭＯＳトランジスタ５のゲートにかかる電圧＋Ｖｌ
）Ｎ１１１はｎチャネルＭＯＳトランジスタロのゲート
にかかる電圧である。また、表２は表１に相当し、これ
と同様にＭＯＳトランジスタの抵抗値及び挿入した抵抗
器９の抵抗値を基準化して示している。Next, the value of the through current for the embodiment shown in FIG. 1 will be examined in the same manner. Figure 2 corresponds to Figure 6 of the conventional example, where R107 and R
A resistor R109 is inserted between the p-channel MOS transistor 5 and the n-channel MOS transistor of the output circuit.
The potential applied to the gate is different from that of the I-range star. Note that the resistor R109 represents the on-resistance of the analog switch 9 in FIG. Here, VGPIIO is the voltage +Vl applied to the gate of p-channel MOS transistor 5.
)N111 is the voltage applied to the gate of the n-channel MOS transistor. Further, Table 2 corresponds to Table 1, and similarly shows the resistance values of the MOS transistor and the resistance value of the inserted resistor 9 on a standardized basis.
表２
表２から貫通電流のピークは、入力電圧がｖ２の時で、
ｎチャネルＭＯＳトランジスタ８のゲート・ソース間に
かかる電圧は１／ＡＶｃｃ又、ｐチャネルＭＯＳＩ−ラ
ンジスタつのゲート・ソース間にかかる電圧もＶｅｃ
３ ／ ４ Ｖｃｃ＝１ ／ ４ Ｖｃｃである０表
１と同様に、この時出力回路に流れる貫通電流を計算す
ると次のようになる。Table 2 From Table 2, the peak of the through current is when the input voltage is v2,
The voltage applied between the gate and source of the n-channel MOS transistor 8 is 1/AVcc, and the voltage applied between the gate and source of the p-channel MOS transistor 8 is also Vec.
3/4 Vcc=1/4 Vcc 0 Similarly to Table 1, the through current flowing through the output circuit at this time is calculated as follows.
Ｖｃｃ＝ ５ Ｖ、Ｖｖｎ−０，７Ｖとするどとなる。Vcc=5V, Vvn-0.7V, etc.
すなわち、従来例の式（２）に比べ１／１０以下に貫通
電流を減少させることができる。That is, the through current can be reduced to 1/10 or less compared to the conventional equation (2).
このように本実施例回路では、出力回路のスイッチング
時の貫通電流を減少させることができ、スイッチング時
のスパイクノイズの減少、消費電力の低減を図ることが
できる。又、第１図と第５図を比較して、出力回路のｐ
チャネルＭＯＳトランジスタ５及びｎチャネルＭＯＳト
ランジスタロの電流容量（ドライブ能力）は全く差がな
く、容量性負荷に対しても充分な高速性を得られる事は
いうまでもない。また、表２におけるＶｃｐＨＯ。In this way, in the circuit of this embodiment, the through current during switching of the output circuit can be reduced, and spike noise during switching can be reduced, as well as power consumption. Also, by comparing Figures 1 and 5, the output circuit p
There is no difference in current capacity (drive ability) between the channel MOS transistor 5 and the n-channel MOS transistor 5, and it goes without saying that sufficient high speed can be obtained even with a capacitive load. Also, VcpHO in Table 2.
■。、１１１は抵抗比で決定されるが、第１図に於いて
全ての抵抗はＭＯＳトランジスタで形成されており、バ
ラツキは同様に発生（例えば、ゲート長しがなくなるあ
るいは細くなる等）するので、抵抗比はほとんど変化せ
ず、バラツキに対して、強い回路と言える。■. , 111 are determined by the resistance ratio, but in FIG. 1, all the resistors are formed by MOS transistors, and variations occur in the same way (for example, the gate length disappears or becomes thinner, etc.). The resistance ratio hardly changes, and it can be said that the circuit is resistant to variations.
なお、上記実施例ではアナログスイッチを常時オンさせ
て抵抗器として利用したが、これはＭＯＳトランジスタ
のオン抵抗を抵抗器として利用するものであればどのよ
うなものでも良い。In the above embodiment, the analog switch is always turned on and used as a resistor, but any type of switch may be used as long as it uses the on-resistance of a MOS transistor as a resistor.
また、本発明は相補型ＭＯＳ集積回路だけでな（他のＭ
ＯＳ回路にも適用可能である。Furthermore, the present invention is applicable not only to complementary MOS integrated circuits (other MOS integrated circuits).
It is also applicable to OS circuits.
以上のように本発明にかかる相補型ＭＯＳ集積回路によ
れば、出力前段回路をｐチャネルＭＯＳトランジスタと
、ｎチャネルＭＯＳＩ−ランジスタと、該２つのトラン
ジスタ間に直列に接続された抵抗器とから構成したので
、出力回路のスイッチング時の貫通電流を減少させ、こ
れによりスイッチング時のスパイクノイズの減少と共に
消費電力の低減を図ることができる。As described above, according to the complementary MOS integrated circuit according to the present invention, the output pre-stage circuit is composed of a p-channel MOS transistor, an n-channel MOS I-transistor, and a resistor connected in series between the two transistors. Therefore, it is possible to reduce the through current during switching of the output circuit, thereby reducing spike noise during switching and reducing power consumption.
第１図はこの発明の一実施例による相補型ＭＯＳ集積回
路を示す図、第２図は第１図の出力前段回路の等価回路
図、第３図は一般的なＣＭＯＳ回路の最小単位の回路構
成を示す図、第４図は第３図の回路の貫通電流を示す図
、第５図は従来の出力回路及び出力前段回路を示す図、
第６図は第５図の出力前段回路の等価回路図、第７図は
従来の回路の基板実装時の等価回路図、第８図はスパイ
クノイズを示す図である。
１・・・入力端子、２・・・出力端子、３・・・電源端
子、４・・・グランド端子、５．７．１０・・・ｐチャ
ネルＭＯＳトランジスタ、６．８．１１・・・ｎチャネ
ルＭＯＳトランジスタ、９・・・アナログスイッチ。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a diagram showing a complementary MOS integrated circuit according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of the output pre-stage circuit of FIG. 1, and FIG. 3 is a circuit of the minimum unit of a general CMOS circuit. A diagram showing the configuration, FIG. 4 is a diagram showing the through current of the circuit in FIG. 3, and FIG. 5 is a diagram showing the conventional output circuit and output pre-stage circuit.
FIG. 6 is an equivalent circuit diagram of the output pre-stage circuit of FIG. 5, FIG. 7 is an equivalent circuit diagram of the conventional circuit when it is mounted on a board, and FIG. 8 is a diagram showing spike noise. 1... Input terminal, 2... Output terminal, 3... Power supply terminal, 4... Ground terminal, 5.7.10... P channel MOS transistor, 6.8.11... n Channel MOS transistor, 9...analog switch. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (2)
チャネルＭＯＳトランジスタとを電源と接地間に直列に
接続してなる出力回路と、該出力回路を駆動する前段回
路とを有する相補型ＭＯＳ集積回路において、 上記前段回路は、第２のｐチャネルＭＯＳトランジスタ
と、第２のｎチャネルＭＯＳトランジスタと、該２つの
トランジスタ間に直列に接続された抵抗器とからなるこ
とを特徴とする相補型ＭＯＳ集積回路。(1) First p-channel MOS transistor and first n-channel MOS transistor
In a complementary MOS integrated circuit, the circuit includes an output circuit including a channel MOS transistor connected in series between a power supply and ground, and a front-stage circuit that drives the output circuit, the front-stage circuit comprising a second p-channel MOS transistor. A complementary MOS integrated circuit comprising: a second n-channel MOS transistor; and a resistor connected in series between the two transistors.
た第３のｐチャネルＭＯＳトランジスタとそのゲートが
電源に接続された第３のｎチャネルＭＯＳトランジスタ
とが並列に接続されてなることを特徴とする特許請求の
範囲第１項記載の相補型ＭＯＳ集積回路。(2) The resistor is characterized in that a third p-channel MOS transistor whose gate is connected to the ground and a third n-channel MOS transistor whose gate is connected to the power supply are connected in parallel. A complementary MOS integrated circuit according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61128367A JPS62284524A (en) | 1986-06-02 | 1986-06-02 | Complementary type mos integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61128367A JPS62284524A (en) | 1986-06-02 | 1986-06-02 | Complementary type mos integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62284524A true JPS62284524A (en) | 1987-12-10 |
Family
ID=14983070
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61128367A Pending JPS62284524A (en) | 1986-06-02 | 1986-06-02 | Complementary type mos integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62284524A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01305616A (en) * | 1988-06-02 | 1989-12-08 | Toshiba Corp | Output circuit for semiconductor integrated circuit |
| EP0416409A2 (en) * | 1989-09-06 | 1991-03-13 | National Semiconductor Corporation | Spike current reduction in CMOS switch drivers |
| JPH03230616A (en) * | 1990-02-05 | 1991-10-14 | Fujitsu Ltd | Cmos output circuit |
| JPH04330822A (en) * | 1991-01-14 | 1992-11-18 | Toshiba Corp | Cmos output buffer circuit |
| US6329866B1 (en) | 1999-01-29 | 2001-12-11 | Nec Corporation | Transient current producing method, transient current producing circuit, related semiconductor integrated circuit and logical circuit |
-
1986
- 1986-06-02 JP JP61128367A patent/JPS62284524A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01305616A (en) * | 1988-06-02 | 1989-12-08 | Toshiba Corp | Output circuit for semiconductor integrated circuit |
| EP0416409A2 (en) * | 1989-09-06 | 1991-03-13 | National Semiconductor Corporation | Spike current reduction in CMOS switch drivers |
| JPH03230616A (en) * | 1990-02-05 | 1991-10-14 | Fujitsu Ltd | Cmos output circuit |
| JPH04330822A (en) * | 1991-01-14 | 1992-11-18 | Toshiba Corp | Cmos output buffer circuit |
| US6329866B1 (en) | 1999-01-29 | 2001-12-11 | Nec Corporation | Transient current producing method, transient current producing circuit, related semiconductor integrated circuit and logical circuit |
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