JP2621628B2 - Semiconductor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly, to a semiconductor memory realizing high-speed operation.

[Conventional technology]

Conventionally, the number of output bits of a semiconductor memory is configured to simultaneously read the same number of memory cells corresponding to the number of output bits of a microprocessor used together with the semiconductor memory. The number of output bits is 1 bit, 4 bits,
There are many types such as 8-bit and 16-bit, but generally there are many types of 8-bit output corresponding to the 8-bit microcomputer. Here, one bit of the multi-bit output will be described as an example.

FIG. 4 is a circuit diagram showing a 1-bit portion of a multi-bit of a conventional multi-bit output semiconductor memory. The semiconductor memory in the figure, an external input terminal 1 for receiving an address input signal V _i, series connected between the internal ground line 5 the source-drain path connected in common gate and internal power supply line 8 to the external input terminal 1 and P-channel MOS transistor (hereinafter referred to as NMOST) (hereinafter PMOST referred) M ₁ and N-channel MOS transistor input circuit portion constituted by the input CMOS inverter gates consisting of M _2, which is the output of the output terminal 6 of the input circuit section as input V _a, the memory of the known contents and a sense amplifier circuit for reading decoder and a plurality of selecting a memory cell memory cell (ROM cell, EPROM cells or RAM cell) information of a sequence memory cell array and the memory cell The gate is commonly connected to the output section 7 of the memory section 10 and the memory section 10, and the source / drain path is connected in series between the internal power supply line 8 and the internal ground line 5. The PMOST M ₃ and NMOS
An inverter consisting TM ₄ receives the output i.e. sense amplifier output V _b of the memory portion 10 the external output terminal 2
And an output circuit for outputting data _Oi to the output circuit. The internal power line 8 and the internal ground line 5 are connected to the parasitic inductances L ₂ and L _{1 of the} package lead frame, respectively.
Are respectively connected to the external terminals 4 and 3 through the parasitic resistances R ₂ and R ₁ and.

The operation of FIG. 4 will be described with reference to the timing chart of FIG. 5 showing the operation of the semiconductor memory of FIG. First, in the period t ₁ the voltage of the external input terminal 1 to the applied address input signal from the TTL input level 0.8 ^v (low)
2.2 ^v When the (high level), the output V _a of the input circuit portion vary from about 0 ^v (low) voltage V _s1 of the internal ground wire 5 to about 5V (high level) of the voltage V _cc1 internal power supply line 8 Then, it is applied to the memory unit 10 to select one memory cell. Assuming that the data of the selected memory cell is read and the sense amplifier output _Vb changes from the low level (0 V) to the high level (5 V), the _Vb goes to the high level and the NM becomes high.
OS M ₄ is turned on, PMOS M ₃ is turned off, and the data output O _i of the output terminal 2 changes from high level (H) to low level (L). Although this time the charge stored in the capacitor C of the data output terminal 2 is discharged to the ground line 5 through M _4, the current i flowing into the grounding line 5 is the external ground terminal via R ₁ and L ₁ 3, the current i generates an electromotive force of L di / dt and the potential V _s1 of the internal ground line 5 rises from 0 ^v to 1 ^v . As a result, the source of the NMOST M ₂ input circuits sharing the internal ground wire 5 is changed to 1 ^v, the potential difference is 2.2 ^v between the gate input 2.2 ^v
From changes to 1.2 ^v, M ₂ would be off. So the period
The output V _a of the input circuit in t ₂ changes from low level to high level, thereby causing a malfunction that would read select another memory cell. Appear in the data output O _i after the lapse the erroneous reading of the period t _3, affecting between data output O _i of period t _4. Therefore, although the data output O _i should output a low level in the period (t ₁ + t ₂ ),
becomes stable outputs finally the low level after the lapse of a period of t ₁ ~t _4. That is, a phenomenon occurs in which the output speed is delayed by the time of (t ₃ + t ₄ ). This output circuit attempts to reduce the current i in order to prevent increases the period t ₂ which changes from the high level to the low level,
After all the speed is delayed. Therefore, it has been very difficult to develop a semiconductor memory that realizes high-speed operation.

[Problems to be solved by the invention]

While in the conventional semiconductor memory described above it is necessary to increase the gm of the NMOST M ₄ and PMOST M ₃ of the output circuit final stage output circuit attempts to speed up in order to realize a high speed, Then large during charge and discharge Current flows and the potential of the internal ground wiring and internal power supply wiring fluctuates, causing not only malfunction of the input circuit section commonly connected to these internal wirings, but also fluctuation of the power supply or ground of the sense amplifier circuit and memory cell. Cause malfunction. Therefore, there is a disadvantage that high speed cannot be easily realized. In particular, with the recent increase in the number of bits in microprocessors, the number of bits in EPROMs and mask ROMs is increasing. Accordingly, the sum of the charge / discharge currents also increases, and the fluctuations in the power supply and ground potential on the internal wiring further increase.

As described above, the gm of the transistor in the last stage of the output circuit must be increased in order to realize high speed, but on the other hand, noise is generated in the reference voltage of the internal wiring, and a high-speed and stable semiconductor memory is realized. There was a disadvantage that it could not be done.

Accordingly, an object of the present invention is to provide a high-speed semiconductor memory capable of preventing adverse effects due to noise generated at a reference potential.

[Means for solving the problem]

A semiconductor memory according to the present invention includes a memory unit including an external input terminal, an input circuit unit receiving an input from the external input terminal, a memory cell array receiving an output of the input circuit unit, and a sense amplifier. A semiconductor memory having an output circuit receiving an output of an amplifier and outputting data to an external output terminal, wherein a noise detection circuit having the same input circuit configuration as the input circuit is provided; A constant voltage is applied to the circuit as an input voltage, and a control circuit for controlling application of the output of the sense amplifier to the output circuit unit using an output of the noise detection circuit unit is provided.

In one embodiment of the present invention, the input circuit portion includes an inverter, and the noise detection circuit portion includes an input inverter having the same configuration. In the output circuit section, output transistors are provided between the external output terminal and the power supply and between the external output terminal and the ground, respectively, and the control circuit controls the gate potential of these output transistors.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to Figure 1, input and output circuits of each bit of the memory circuit according to an embodiment of the present invention, PMOST M ₁ and NMOST M connecting the input gate as in the conventional example of FIG. 4 to the external input terminal 1 an input circuit having an output terminal 6 made of CMOS inverters connected to the memory unit 10 by _2, the external data output terminal 2
CMOS by PMOST M ₃ and NMOST M ₄ and an output end connected to the
Output circuit consisting of inverter gate, PMOST M ₁ and
An internal power supply line 8 to be connected to an external V _cc terminal 4 via a connected to the source of M ₃ resistor R ₂ and the inductor L _2, was connected to a source of NMOST M ₂ and M ₄ resistors R ₁ and an inductor L ₁ And an internal ground wiring 5 connected to an external ground (V _s ) terminal 3 via the external ground (V _s ) terminal 3. In this embodiment, the CMOS of the input circuit unit is used.
A CMOS gate having the same configuration as the gate is connected to transistors M ₅ , M ₆ ,
Formed by M _7, M _8, and the noise detection circuit. The noise detection circuit, PMOST M ₅ and NMOST M connected in series between the constant voltage internal power supply line 8 and the internal ground line 5 a source-drain path and a gate connected in common to a terminal 9 for applying a V _{x 6} , a first CMOS inverter is formed, a detection signal _VST is taken out from its output terminal 61, a gate is commonly connected to the output terminal 61, and a source / drain path is connected between the internal power supply line 8 and the internal ground line 5. PMOST M ₇ connected in series between
And the NMOST M ₈ are those which constitute a second CMOS inverter taking out a detection signal _ST from the output terminal 62. The output terminal 61 of the first CMOS inverter is connected to the input terminal of the two-input NOR gate 12 together with the output terminal 7 of the memory unit 10 (that is, each bit output terminal of the sense amplifier).
The output terminal 62 of the inverter is connected to the input of the two-input NAND gate 11 together with each bit output terminal 7 of the sense amplifier.
The output of gate 12 NAND gate of the NMOST M ₄ of the output circuit section
The output of gate 11 is connected to the gate of the PMOST M ₃ of the output circuit section. That is, both gates 11 and 12
The control circuit controls the application of the output _Vb of the memory unit 10 to the output circuit unit using the outputs _VST and _ST of the noise detection circuit. Constant voltage V _X is the high level voltage applied to the external input terminal 1 as NMOST M ₆ operates faster than NMOST M ₂ input inverter by the potential variation of the internal ground line 5 to be applied to the input terminal 9 of the noise detection circuit ( At TTL level, the voltage is lower than 2.2 ^V ). For example, in this embodiment,
V _{x is set} to 1.9 ^V.

The operation of the semiconductor memory of this embodiment will be described with reference to FIG. First an address signal V _i to the external input terminal 1 TTL
Changing the output V _a of the input CMOS gates from the level of the low level (0.8 ^V) in the high level (2.2 ^V) from the high level (5 ^v) to low level (L), the memory cell by a decoder in the memory unit 10 Select the data and output the sense amplifier output V _b
Read as Here, the case where the sense amplifier output _Vb changes from the high level to the low level will be described. Since it is set to V _x = 1.9 ^v, the potential V _S1 of the internal grounding line 5 0 ^v noise detection signal when the V _ST = 0 ^v, becomes _ST = 5 ^v. Therefore, with the transition to the low level of the sense amplifier output V _b NOR gate for receiving the V _ST of this V _b and the low level
The 12 outputs V _n2 are from low level (0 ^v ) to high level (5 ^v )
It changes to turn on the NMOST M ₄ of the output circuit unit to. On the other hand, a NAND gate 11 that inputs _Vb and high-level _ST
The output V _n1 also changes from the low level to the high level and the output P
To the MOST M ₃ off. Thus the data output O _i obtained at the external output terminal 2 of the output circuit section starts to change from the high level to the low level. At this time, the charge Q = C × _Vcc stored in the capacitor C of the output terminal 2 is equal to the output NMO
Discharged to the external ground terminal 3 via the STM ₄ , but the potential V _S1 of the internal ground line 5 becomes 0 due to the influence of R ₁ and L ₁ in the path.
Try to float from ^v to 1.0 ^v . However turned off the output V _a NMOST M ₂ is turned off in the input circuit NMOST M ₆ of the noise detection circuit prior to a high level by detecting the noise gate is the detection signal V _ST is at the high level 1
Changing the second output V _n2 to the low level. The resulting output NM
OST M ₄ is prevented prior to malfunction input circuit to the raised potential V _S1 of the internal ground line 5 becomes off. Thus, the data output O _i is the stable operation can be realized without causing a malfunction. When the potential V _S1 of the internal ground line 5 becomes stable, the NMOS M ₆ of the noise detection circuit is turned on again to return the detection signal V _ST to the low level, and the output V _n2 of the NOR gate 12 also becomes the high level, and the output data O _The operation of lowering _i to the low level is restarted.

FIG. 3 shows a second embodiment of the present invention. In this embodiment, the input circuit section has a two-stage inverter configuration to improve the input characteristics, and accordingly, the first-stage inverter of the noise detection circuit has two stages. As a result, the effect of preventing malfunction is further enhanced. In this example, PMOST M
_11, using the M ₅₁ and NMOST M ₁₂ and M ₆₁ to form an input inverter of the second stage of the input circuit section and the noise detection circuit unit.

〔The invention's effect〕

As described above, according to the present invention, the noise detection circuit having the same configuration as the input circuit is provided, and the input voltage is set more strictly (lower) than the external input. This has the effect of preventing malfunction and preventing high-speed operation.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG.
3 is a circuit diagram of a second embodiment of the present invention, FIG. 4 is a circuit diagram of a conventional example, and FIG. 5 is a waveform diagram showing a circuit operation of a conventional example. It is. 1 external input terminal, 2 external output terminal, 3 external ground terminal, 4 external power supply terminal, 5 internal ground wire, 6
…… Output terminal of input circuit, 7… Output terminal of memory section, 8…
... internal power supply line, 9 ... constant voltage input terminal, 10 ... memory unit, 11 ... 2-input NAND circuit, 12 ... 2-input NOR circuit.

Claims (1)

(57) [Claims] An input circuit receiving an input from the external input terminal; a memory including an output of the input circuit, a memory cell array and a sense amplifier; and a sense amplifier of the memory. A noise detection circuit having the same input circuit configuration as that of the input circuit, wherein the input circuit of the noise detection circuit has the same input circuit configuration as the input circuit. And a control circuit for controlling application of the output of the sense amplifier to the output circuit unit using an output of the noise detection circuit unit.