JPH04146595A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent the malfunctions and to attain the high speed working of a semiconductor memory by providing a noise detection circuit having the same constitution as an input circuit and setting the input voltage of the noise detection circuit at a level lower than the external input level. CONSTITUTION:A CMOS gate of the same constitution as a CMOS gate of an input circuit part consists of transistors M5 - M8 and serves as a noise detection circuit. Meanwhile a NAND gate 11 and a NOR gate 12 form a control circuit which controls the application of the output Vb of a memory part 10 to an output circuit part by means of the output VST and the output, the inverse of VST of the noise detection circuit. Then the constant voltage VX applied to an input terminal 9 of the noise detection circuit is set at a level lower than the high level voltage applied to an external input terminal 1 so that an NMOST M6 works earlier than an NMOST M2 of an input inverter with the potential variance of an internal ground line 5. Thus it is possible to prevent the adverse influence caused by the noises produced at a reference potential.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and particularly to a semiconductor memory that achieves high-speed operation.

[Conventional technology]

Conventionally, the number of output bits of a semiconductor memory corresponds to the number of output bits of a microprocessor used with the semiconductor memory, and the same number of memory cells are configured to be read simultaneously. The number of output bits is 1 bit, 4 bits, 8 bits.
There are various types such as 16-bit and 16-bit, but most are compatible with 8-bit microcontrollers and have 8-bit output. Here, an example of all one bit of the multi-bit output will be explained.

FIG. 4 is a circuit diagram showing one bit of multiple hits in a conventional multi-bit output semiconductor memory. In the figure, the semiconductor memory has an external input terminal 1 that receives an address input signal V, a gate is commonly connected to the external input terminal 1, and a source/drain path is connected in series between an internal power supply line 8 and an internal grounding line 5. P-channel MOS transistor (referred to as PMOS T) Mt and N-channel MOS
An input circuit section constituted by an input CMOS inverter gate consisting of a transistor (hereinafter referred to as NMO8T) M2, and a decoder that selects a memory cell by inputting the output Va of the output terminal 6 of this input circuit section. , EPROM cells or RAM cells) and a sense amplifier circuit for reading information from the memory cells.
0, PMO8T M whose gate is commonly connected to the output terminal 7 of the memory section 10 and whose source/drain path is connected in series between the internal power supply line 8 and the internal ground line 5, and NMOS.
The memory section 10 is composed of an inverter consisting of TM4.
, that is, an output circuit section that receives the sense amplifier output (2) b and outputs data Oi to the external output terminal 2. The internal power supply line 8 and the internal ground line 5 are each connected to the parasitic inductance L of the lead frame of the package.
2 and L□ and are connected to external terminals 4 and 3 via parasitic resistances R2 and R1, respectively.

The operation of FIG. 4 will be explained with reference also to the timing chart of FIG. 5 showing the operation of the semiconductor memory of FIG. 4. During the period t1, the voltage of the address input signal applied to the external input terminal 1 '1TTL is input, and the voltage of the terminal 8 is approximately 5 V () of ccm () - - the voltage of the internal grounding line 5 is approximately Ov of (), □. low level),
One memory cell added to the memory section 10 is selected. The data of the selected memory cell is read and the sense amplifier output b goes to low level (OV), <#(5
V) K1m conversion 5aoh.

And, as ■b becomes high level, l) NMO8M4
turns on, PMO8M3 turns off, and the data output O1 of the output terminal 2 changes from high level (H) to low level (L). At this time, the charge stored in the capacitor C of the data output terminal 2 is discharged to the ground line 5 via M4.
Since the current i flowing into the external grounding terminal 3 flows through the terminal 1 and Ll, an electromotive force of L dt- is generated by the current i, and the potential V, □ of the internal grounding wire 5 rises from Ov to 1v. do. As a result, the input circuit NMO8TM2 that shares the internal ground line 5
The source changes to 1v, and the potential difference between it and the gate power 22v changes from z2v to 1.2v, turning M2 off. Therefore, in the period t2, the output v2 of the input circuit changes from low level to high level, which causes a malfunction in which another memory cell is selected and read out. That-! 5! The overflow appears on the data output O1 after the period t3 and affects the data output O1 during the period t4. Therefore, data output O1 should normally output a low level during the period (t□+t2゛), but from t1 to t
After the period 4 has elapsed, stable low level output is finally achieved. In other words, a phenomenon occurs in which the output speed is delayed by the time (t3+t4). If an attempt is made to reduce the current i to prevent this, the speed will be delayed during the period t2 during which the output circuit changes from high level to low level. Therefore, it has been extremely difficult to develop a semiconductor memory that achieves high-speed operation.

[Problem to be solved by the invention]

In the conventional semiconductor memory mentioned above, if you try to speed up the output circuit to achieve high speed, you have to increase the gm of NMO8TM4 and PMO8TM3 in the final stage of the output circuit, but this causes a large current to flow during charging and discharging. The potential of the internal ground wiring and internal power supply wiring fluctuates, which not only causes malfunctions in the input circuit section commonly connected to these internal wirings, but also fluctuates the power supply or ground of the sense amplifier circuit and memory cells, causing malfunctions. wake up

Therefore, there is a drawback that speeding up cannot be easily achieved. *Recently, as microprocessors have become more bit-rich, EFROMs and mask ROMs have become more bit-rich. Along with this, the total charging and discharging current also increases.
Fluctuations in the power supply and ground potentials on internal wiring become even greater.

As mentioned above, in order to achieve high speed rounding, it is necessary to increase the gm of the transistor in the final stage of the output circuit, but on the other hand, this results in imaging that generates noise in the reference voltage of the internal wiring, so it is necessary to use a high-speed and stable semiconductor memory. The drawback was that it could not be realized.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a high-speed semiconductor memory f: that can prevent the adverse effects of noise generated in the reference potential.

[Means for solving the lI problem]

The semiconductor memory of the present invention includes an external input terminal, an input circuit section that receives input from the external input terminal, a memory section that receives the output of the input circuit section and includes a memory array, a sense amplifier, and a metal. In a semiconductor memory having an output circuit section that receives an output from a sense amplifier and outputs data to an external output terminal, a noise detection circuit section having the same input circuit configuration as the input circuit section is provided, and the noise detection circuit section A constant voltage is applied as an input voltage to the input circuit of the sensor, and a control circuit is further provided for controlling application of the output of the sense amplifier to the output circuit section using the output of the noise detection circuit section. .

According to the -IIIi aspect of the present invention, the input circuit section includes an inverter, and the noise detection circuit section also includes an input inverter having the same configuration. Further, in the output circuit section, output transistors are provided between the external output terminal and the power supply and between the external output terminal and the ground, respectively, and the gate potentials of these output transistors are controlled by a control circuit.

〔Example〕

Next, the present invention will be described with reference to FIGS.

Referring to FIG. 1, the input/output circuit of each bit part of the memory circuit according to the embodiment of the present invention is a PMO8T M with an input gate connected to the external input terminal l, similar to the conventional example shown in FIG.
an input circuit comprising a CMOS inverter with NMO8T M2 and an output terminal 6 connected to a memory section 10;
PMO8T with output end connected to external data output terminal 2
M, and an output circuit consisting of a CMOS inverter gate using NMO8TM4, and PMO8TM M and M,
An internal power source 8 is connected to the source of the
8T Connect to M2 and M40 sources and resistor 11? +
1 and an internal ground wiring 5 connected to an external ground (■, ) terminal 3 via an inductor L1. In this example, CMO 8-gate gold transistors M, , M, , M, which have the same configuration as the input circuit fDcMOS gate,
, 1lii, and serves as a noise detection circuit. This noise detection circuit shares a gate with terminal 9 to which a constant voltage xt is applied! ! A PMO8TM and a NMO8TM, whose source/drain paths are connected in series between the internal power supply line 8 and the internal ground line 5,
The CMOS inverter f: is constructed so that the detection signal VST is taken out from the output terminal 61, the gate is commonly connected to this output terminal 61, and the source/drain diameter M is connected between the internal power supply line 8 and the internal grounding line 5. Connected in series (-PMO8T M7
and NMO8TM constitute a second CMOS inverter, and the detection signal sT1 is taken out from the output terminal 62 of the second CMOS inverter. The output terminal 61 of the first CMOS inverter is connected to the output terminal 7 of the memory section 10 (that is, each bit output m of the sense amplifier) as well as the two-manufactured NOR gate 12.
The output terminal 62 of the second CMG8 inverter is connected to the input of two NA/ND gates 11 along with each bit output terminal 7 of the sense amplifier, and the output of the NOR gate 12 is connected to the output circuit section. NMO8T M4 game)
PM08T of KNANDNOR gate 12 output circuit section
M, are connected to the gates of M, respectively.

That is, both gates 11 and 12 convert the application of the output b of the memory section 10 to the output circuit section from the output b of the noise detection circuit.
A control circuit is constructed using 8T and 8T. The constant voltage 8 applied to the input terminal 9 of the noise detection circuit is a high-l noise voltage (TTL+z For Bell, the voltage is set to !2V). For example, in this embodiment, Vx is set to L9■.

The operating tube of the semiconductor memory IjO of this embodiment will be explained with reference to FIG. First, 0 address signal Vit to external input terminal 1
TTL level low level (α8■) Kara high level (Z2
V) KL selects the output cell of the input CMOS gate and reads its data as the sense amplifier output b.Here, the time when the sense amplifier output vb changes from high level to low level will be explained. Since the voltage is set to 1.9V, when the potential ■8□ of the internal ground line 5 is oV, the noise detection signal becomes ■5T=Ov, ■5T=5V. Therefore, as the sense amplifier output b shifts to low level, NO
The output of R gate 12 n2 changes from low level (Ov) to high level (5v) and outputs NMO8TM of the output circuit section.
Turn on 4. On the other hand, the output (■) of the NAND gate 11 which receives vb and the high level (■8T) as inputs. □ also shifts from low level to high level to turn off the output PM08T M3. Therefore, the external output terminal 2 of the output circuit section
The data output 07 obtained at this point begins to change from high level to low level. At this time, the charge Q = Cxvcc stored in the capacitor C of the output terminal 2 is the output NMO8 which is on.
Although it is discharged to the external grounding terminal 3 via T M4, the potential (8) of the internal grounding edge 5 tends to rise from Ov to tOv due to the influence of R1 and L in the path. However, NMO8T M2 of the input circuit turns off and the output ■1
NMO8 of the noise detection circuit becomes high level.
TM detects noise and turns off, and its detection signal vsT becomes high level and output vn2 of gate 12.
changes to low level. The resulting output NMO8T
M4 is off and the potential of internal ground line 5 is Vs! To prevent an input circuit from floating before it malfunctions. This allows the data output O1 to operate stably without causing any malfunction. When the potential vs□ of the internal ground line 5 becomes stable, the noise detection circuit NMO8TM is turned on again, returning the detection signal ■s〒 to the low level, and the NOR gate 12
The output 'vn2 also becomes high level, and the operation of dropping the output data Oi to low level is restarted.

FIG. 3 shows a second embodiment of the invention. In this embodiment, the input circuit section has a two-stage inverter configuration to improve input characteristics, and accordingly, the first-stage inverter of the noise detection circuit is also configured with two stages. As a result, the effect of preventing malfunctions becomes even greater. In this example, PMO8T
M, 1. M,, and NMO8TM! 2 and M6,
is used to form a two-stage input inverter including an input circuit section and a noise detection circuit section.

〔Effect of the invention〕

As explained above, according to the present invention, by providing a noise detection circuit with the same configuration as the input circuit and setting its input voltage more strictly (lower) than the external input, it is possible to detect noise before the input circuit malfunctions. This has the effect of operating the detection circuit to prevent malfunctions and realize high-speed operation.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
3 is a circuit diagram of the second embodiment of the present invention, FIG. 4 is a circuit diagram of the conventional example, and FIG. 5 is a waveform diagram showing the circuit operation of the conventional example. It is. 1...External input terminal, 2...External output terminal, 3...
- External grounding terminal, 4... External power supply terminal, 5... Internal grounding wire, 6... Output end of input circuit, 7... Output end of memory section, 8... Internal power supply line, 9・・・Constant voltage input terminal, 1o...Memory part, 11...2 manual NAND
Circuit, 12...2 human powered NOR circuit.

Claims (1)

[Claims] an external input terminal, an input circuit section that receives input from the external input terminal, a memory section that receives the output of the input circuit section and includes a memory cell array and a sense amplifier, and a memory section that receives the output of the sense amplifier of the memory section. In a semiconductor memory having an output circuit section that outputs data to an external output terminal, a noise detection circuit section having the same input circuit configuration as the input circuit section is provided, and a constant input voltage is applied to the input circuit of the noise detection circuit section. A semiconductor memory comprising a control circuit that applies a voltage and further controls application of the output of the sense amplifier to the output circuit section using the output of the noise detection circuit section.