JPH02104130A - D/a converter - Google Patents

Abstract

PURPOSE:To reduce a chip size at the time of IC formation by respectively independently supplying two X decoded signal outputs having respectively positive and negative polarity and generated from an X decoder to constant current source reference circuits constituted of a matrix divided by the X decoder. CONSTITUTION:Out of the constant current source reference circuits (X, Y)=(0, 0) to (7, 7), an X decoder output Xn is used as the input of Xj in case of y=0, 2, 4, 6 and an X decoder output, the inverse of Xn as the input of the Xj in case of y=1, 3, 5, 7. Two X decoded signals can be converted to one X decoded signal by supplying the Xn and the inverse of Xn and the length of a wiring supplied from the X decoder to the constant current source reference circuits can be shortened to 1/2 by arranging the X decoder on the center of the matrix. Thus, the chip size can be reduced at the time of IC formation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a D/A conversion device used as an MO8 integrated circuit.

BACKGROUND OF THE INVENTION In recent years, D/A converters have been playing an important role as the interface between analog processing and digital processing, as the digital processing of all kinds of electronic equipment is progressing.

A conventional MO8 type segment type D/A converter will be described below. FIG. 3 is a diagram of a conventional 6-bit D/A converter.

φC is a two-phase clock pulse, DO"""DS is 6-bit data, 3 is a decoder, 4 is a Y decoder, 301°30
2.406,407 are NAND gates, 303°305
．． 403,405 are composite gates, 306°307.40
1,402,422,424,426°428.430
, 432, 434, 436 are NOR gates, 304.3
08～315,348,332゜334.336,33
8,340,342,344°346.404,408
~414,423,425°427.429,431,
433,435,437 Heinharta (hereinafter referred to as INV), 333°335.337,339,341,34
3,345°347 is buffer, 349.350 is AN
D, 316-331. 415-421 are transfer gates, Xo=X7. Xo''-X7 is the X decoder output YP
o~YP7. YSO""'YS7 is the X decoder output.

(0,0) to (7,7) are constant current source basic circuits arranged in a matrix. 10 is a resistor, which is connected to constant current source basic circuits (0,0) to (7,7).

Next, the circuit configuration of the constant current source basic circuit is shown in FIG. Reference numeral 30 indicates a constant current source basic circuit block, 31 is a two-man power AND gate, 32 is a two-man power NOR gate, 33 is a transfer gate, and 35 to 38 and 391 to 396 are n-channel MOS transistors. Xl is the output of the j-th X decoder, (YP, Ysl) is the output of the i-th This is the bias current that determines the current value of the constant current source.

The operation of the D/A converter configured as described above will be explained below. First, bit data DO-D
Of S, data Do-D3 is input to the X decoder. Among them, D3 has a high level (
It is used to switch between generating a low level (hereinafter referred to as "H level") and generating a low level (hereinafter referred to as "L" level), and is latched by clock pulse φC and the X decoder output (Xn, Xn) (n = o ~7) is generated.

This relationship is shown in Table 1.

(Margin below) Data D3 to D5 are also input to the X decoder 4, latched by the clock pulse φC, and output from the X decoder (Ypo
, Yso) ~(YP71 YS7) is generated.

This relationship is shown in Table 2.

(Margin below) [Xn, X,], [Y,, Ys
,](n, m=o~7), the constant current source basic circuits (0,0)~(7,7) are latched by the clock pulse 7c, and the output power 1 OUT flows. By counting up data bit by bit, as shown in Fig. 3,
The basic constant current source circuit is (0,○)→(1,0)→(2,0
)→・・・・・・(7,0)→(0,1)→(1,1)
→・・・・・・(7,1)→(0,2)→・・・・・・
It conducts in the order of (6, 7) (.

For example, if the data is (D5.D4.D3.D2.Dl, D
When O) = (0, O, O, 0, 0, 0), (XO,
Xl, X2°X3. X4. XS, XO, X7) - (1,
1, 1, 1, 1, l.

1.1〉・(Ypo・yso・YPI・YSI・YrJ
2・YS2・YI33・YS3・YF3・Ysn・Yp
s・YS5・yps・YSfi, YF3・YS7)=
(0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1.

1.1, 1.1, 1). Constant current source basic circuit (0,
0), from Fig. 4, Ypo= 0, Ys'o= l
.

Xo=1, the output of the NOR gate 32 becomes -L- level, and when the clock pulse φC is at the "H" level,
Transfer gate 33 conducts and the signal passes through INV 34 causing transistor 35 to conduct. It forms a current mirror structure with an external transistor 38 and acts as a constant current source (the current flowing through the transistor 36 is taken from the transistor 35. When the transistor 35 is non-conducting, the current is taken from the transistor 37. In a series of operations, data is input from DQ-Da.

Depending on the binary data, the output current is output to the corresponding number of constant current source basic circuits! OUT flows, and the currents flowing in all constant current source basic circuits are added and converted into an analog current amount. Note that the fact that a current flows through the output transistor 37 of the constant current source basic circuit is hereinafter referred to as conduction.

Problems to be Solved by the Invention However, in the above conventional configuration, two types of signals, Xn and Xo, are sent from the X decoder 3 as decode signals to the constant current source basic circuit block shown in FIG. Since the constant current source was supplied to the basic circuit, when it is integrated into an integrated circuit, it takes up extra wiring area and increases the chip size. Extra digital noise is added to capacitively coupled analog signal wiring (for example, signals flowing through bias current +1111AS, bias voltage CV, and output current +OUT), which in turn generates pulse noise (bridge) in the D/A conversion output. It had the disadvantage of being a contributing factor.

The present invention solves the above-mentioned shortcomings of the conventional technology, and proposes a D/A converter with a segmented matrix structure that reduces the chip area and reduces digital noise when integrated into an IC. This is the purpose.

Means for Solving the Problems To achieve this object, the D/A converter of the present invention includes:
Constant current source basic circuits are arranged in a matrix structure in the X-axis and Y-axis directions, and an
By inserting at least one of the decoder circuits into the same column or the same row of the matrix of the constant current source basic circuit, the matrix is divided, and the positive phase output of the inserted decoder circuit is divided. It has a configuration in which the input signal is supplied to one matrix block, and the opposite-phase output of the inserted decoder circuit is supplied to the other divided matrix block.

Effect: This configuration reduces the wiring for X or Y decode signals by 1/2.
It is possible to shorten the signal propagation time, reduce the chip area when integrated into an IC, and suppress the generation of digital noise that is superimposed on the analog signal.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a 6-bit D/A in a matrix-configured constant current source addition method according to an embodiment of the present invention.
It shows a conversion device.

In FIG. 1, a power supply voltage VOO and a ground voltage VSS.

Data Do-D5. The configurations of the output current 10UT and the constant current source basic circuits (0, O) to (7, 7) themselves are the same as those of the conventional example. Next, 1 is the X decoder, 2
is Y decoder, 101,102°204.207 is NA
ND gate, 103,105°202.203 is a composite gate, 106,107°201.205,222,22
4,226,228°230.232,234.236
is a NOR gate, 120, 122, 124, 126, 1
28°130.132.134 is a buffer gate, 10
4゜108.111~119,121,123,125
゜127.129,131,133.208-214゜223.225,227,229,231,233゜2
35.237 is [NV, 109.110 is an AND gate, 135 to 150.215 to 221 are transfer gates, and 10 is a resistor. XO-X7.

xo-X7 is the output of the X decoder. and Y. (n-〇・
...7) has the opposite signal polarity. (Ypo, Y
so ).

(Yp+, Ys+)・(YF3・YS2)・(Y
F3, YS3)・(YF41 YS4), (Y
'ps, Yss), (Ype, Yss).

(YF3. YS7> is the output of the Y decoder. Matrix array constant current source basic circuit (X, Y) = (0, O
) to (7, 7), y=0.2,4°6 uses the X decoder output Xn as the input of XJ in the constant current source basic circuit of Fig. 4, and y=1°3.5.7 uses the X decoder output Xo as the input of X. FIG. 2 shows the above connection relationship. This is a constant current source basic circuit with matrix configuration, X decode signal output Xn, Xn, Y
Decode signal output (YpIll, YslIl), bias voltage CV.

It is a schematic diagram showing the connection relationship of bias current IBIAS, clock pulse 7c, and output current +OUT.

The operation of the matrix-configured D/A converter of this embodiment configured as described above will be described below.

First, as shown in FIG. 1, among the 6-bit data D and -DS, data DO-DS is input to the X decoder 1. Among them, DS outputs the X decoder output X by the clock φC. To”
It is used for switching when generating H" level and 'L" level, and is latched by clock pulse φC to output X from the X decoder. ,Y.

(n-0 to 7) are generated. Then, each of the constant current basic circuit blocks in a matrix configuration, which is divided into two by the X decoder circuit, has a decoded output X. .

Supply Xn. Further, data D3 to D5 are input to the Y decoder 2, latched by clock pulse φC, and Y
Decoder output (ypo, Yso) ~(YF3.
YS7). This relationship is shown in Table 3.

(Hereafter, the rest is white) Therefore, data Ds~Do=(0, O, 0, 1.

1,1) to data D5~Do=(0,0,1,0°0
, O) and D5~Do=(0,0,1,O20°1)
To explain the operation of each part using the operation as an example, the initial data D o = D S is (0, 0, 0° 1.1
．． In the state of 1), from Table 1, the output signal of X decoder 1 is X7=1 and Xo=Xe=O, and its opposite phase is X7=O,X
o~Xa=1. Also, as shown in Table 3, the output signal of the X decoder 2 is (Ypo, Yso) - (
0,1), (Yp+, Ys+) ~(YF3.
YS7) = (1, 1>, latched by φC, supplied to the constant current source basic circuit, (0, 0) to (6
, O) is conductive, and the other (0
, 2) to (7, 7) are in the cutoff state. Next, when the data D5 to Do = (0, 0, 1, O, O, O), among the outputs of the X decoder, X o = X e ,
X o −X s does not change, Xo=Xs=O, Xo=
With Xe=1, X7-1 becomes X? =O, X7=
O changes to X7=1.

Also, the output of the X decoder Ypo=O, YSI~YS7=
1 remains as before, Y decoder output yso changes from Yso=1, YSQ=O, YPI changes from ypt=1 to Ypt=O
becomes. As a result, (7°0) of the constant current source basic circuit
changes from the cut-off state to the conduction state, and therefore the constant current source basic circuit (0,O) to (7,O) becomes conductive, and (0,1)
to (7, 7) are in the cutoff state. And data D
When s~Do= (0,0,1゜0.0.1), X
Among the outputs of the decoder, X1 to X7. XI to X7 do not change, X + -X 7 = 0, X + to Xt = 1
As it is, Xo=O becomes Xo=1, and Xo=1 becomes Xo=
The output of the X decoder remains unchanged (Ypo,
¥so) = (0,0) +(Yp+, Ys+)
= (0,1) + (YP2T YS2) ~(Y
F3. YS7) = (1, 1), and in the constant current source basic circuit, 0°1) is conductive from (0,0) to (7,0), and 1.1) to (7,7) is cut off. become a state.

As described above, according to this embodiment, the constant current control basic circuit blocks in the matrix configuration divided by the X decoder have Xn and X, respectively. By supplying
In addition, by placing the X decoder in the center of the matrix, the length of the wiring from the X decoder to the constant current source basic circuit can be reduced to 1/2. The output buffer and INV of the decoder can also be designed with half the capacity, and when integrated into an IC,
Chip size can be reduced. In addition, the decoded signal that causes digital noise is reduced to 1/2 by the X decoder.
Also, the output buffer of the X-decoder, IN
By reducing the capacity of V, noise can also be reduced.

In addition, in this embodiment, D with a 6-bit matrix structure
Although the A/A converter is taken as an example, it is also applicable to all D/A converters having a 71 trix configuration.

Furthermore, it is also possible to configure the matrix configuration by dividing it into two in the Y-axis direction (but by dividing it in the X-axis direction by an X decoder).

In addition, the X decoder 1 that decodes the lower bit group of the input signal is configured with a gate circuit and a transfer gate switch to simplify the explanation, but the A gate circuit may be configured and decoded only by inputting the least significant bit data D3 of the bit group. And all of this explanation is N
Although channel MOS transistors are used as the basis, it is clear that the circuit configuration may be a P-channel MOS transistor circuit or a CMO8 circuit.

Effects of the Invention The present invention can perform decoding by separately supplying two output X decode signals of positive phase and negative phase generated from an X decoder to one constant current source basic circuit in a matrix configuration divided from one X decoder. It is possible to realize an excellent D/A conversion device that can reduce signal wiring, reduce the chip size when integrated into an IC, and suppress the digital noise multiplied by the decoded signal to the analog signal. be.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a 6-bit D/A converter using a matrix-configured constant current source addition method according to an embodiment of the present invention, and Fig. 2 is a basic constant current source circuit of the D/A converter according to the same embodiment. FIG. 3 is a circuit diagram of a conventional 6-bit D/A converter, and FIG. 4 is a circuit diagram of its basic constant current source circuit. 1...X decoder, 2...Y decoder, 3...X decoder, 4...Y decoder, 10...Resistance, 31 .109,110,3
49.350...AND gate, 32,106
,107,201,205°222.224,226,
228,230,232゜234.236,306,3
07,401,402゜422.424,426,42
8,430,432゜434.436...NO
R gate, 33.135-150,215,221,3
16~331...Transfer gate, 35~
38,391-396...MOS transistor, 34,104,108°111-118,121,1
23,125,127゜129.131,133,20
8～214,223゜225.227,229,231
,233,235°237.304.308~315,
332,334°336.338,340,342,3
44,346°348.408~414,423,42
5,427°429.431,433,435.437
...INV, 103, 105, 202, 203
,303゜305.403.405...Composite gate, 120-134,333,335,337,33
9゜341.343,345,347...Buffer gate, DO-D5...6 bit data,
φC...Clock pulse, <6C...
・Clock pulse with opposite phase of φC, xo-X7...
・X decode output, Xo=X7...X decode output of opposite phase of Xn, (Ypo, Yso) ~ (YF3
．． YS7)...X decode output, I OUT
...Output current, IBI^S...Bias current, CV...Bias voltage. Name of agent: Patent attorney Shigetaka Awano and one other person Figure 2 Figure 1 Figure 4

Claims (1)

[Claims] Constant current source basic circuits are arranged in a matrix structure in the X-axis and Y-axis directions, and an
By inserting at least one of the decoder circuits into the same column or the same row of the matrix of the constant current source basic circuit, the matrix is divided, and the positive phase output of the inserted decoder circuit is divided. A D/A conversion device, characterized in that the D/A converter is supplied to one matrix block, and the opposite phase output of the inserted decoder circuit is supplied to the other divided matrix block.