CN116796679A - Multi-voltage domain CMOS IO design - Google Patents
Multi-voltage domain CMOS IO design Download PDFInfo
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- CN116796679A CN116796679A CN202310791908.8A CN202310791908A CN116796679A CN 116796679 A CN116796679 A CN 116796679A CN 202310791908 A CN202310791908 A CN 202310791908A CN 116796679 A CN116796679 A CN 116796679A
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- 230000003044 adaptive effect Effects 0.000 claims description 13
- 229910044991 metal oxide Inorganic materials 0.000 claims 2
- 150000004706 metal oxides Chemical class 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000006243 chemical reaction Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 13
- 238000004088 simulation Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
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Abstract
The invention relates to the technical field of integrated circuit design, in particular to a multi-voltage domain CMOS IO design, in which IO can work in various voltage domains. The core of the circuit is the drive of the PMOS tube, comprising: the drive circuit with the two PMOS tubes connected in series, the PGATE voltage generation circuit, the FBK generation circuit, the self-adaptive circuit, the VGND voltage generation circuit and the PGATE control switch voltage generation circuit capable of controlling the PGATE voltage generation circuit and the FBK voltage generation circuit can meet a plurality of voltage requirements, the design of the circuit is adopted to greatly improve the flexibility of the circuit, a special voltage conversion circuit is not needed, the cost and the power consumption are saved, the volume of the system is reduced, and the circuit has great practical value.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a multi-voltage domain CMOS IO design.
Background
The scheme of the current IO is as follows if the IO is to interact with circuits with different voltages outside: 1. the MOS tube of the IO circuit can support the required voltage, but the MOS tube is usually a high-voltage MOS tube and is not usually used in the SOC, so the MOS tube is not usually used in the SOC; 2. the IO circuit can only tolerate the input of external high voltage, and can only tolerate the input of external high voltage, but cannot output high voltage; 3. the voltage conversion circuit is built in the PCB or the SOC, but thus the cost is increased and the area and power consumption of the entire circuit are increased. In view of the foregoing and various shortcomings, a need exists for a chip that can support multiple voltages.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a technical solution, which can design multi-voltage IO by using a MOS tube with lower voltage, is truly low in cost and power consumption, can be integrated in an SOC, and solves the defects of the prior art.
The technical scheme adopted by the invention is as follows: the utility model provides a many voltage domain CMOS IO designs, includes two PMOS pipes that establish ties as drive circuit, marks PGATE with the grid of one, and the grid of another marks FBK, and the source of the PMOS pipe that the grid marks PGATE is connected to VDDPST, its characterized in that: the PGATE is connected to a plurality of PGATE voltage generating circuits, and the FBK is also connected to a plurality of FBK generating circuits; each PGATE voltage generating circuit and each FBK voltage generating circuit is connected to PGATE and FBK through a switch. The circuit also comprises an adaptive circuit and a VGND voltage generation circuit, wherein the VGND voltage generation circuit is used for generating a variable VGND voltage signal; the PGATE voltage generating circuits and the PGATE control switch voltage generating circuits are connected with the adaptive circuit and the VGND voltage generating circuit.
Further, the output of the adaptive circuit includes an inter_power voltage signal and an inter_gnd voltage signal.
Further, the PGATE voltage generating circuit includes voltage generating circuits of 1.8V,2.5V, and 3.3V.
Further, the PGATE control switching voltage generation circuit includes control switching voltage generation circuits of 1.8V,2.5V, and 3.3V.
Further, the self-adaptive circuit comprises 3 PMOS and 1 NMOS tubes connected in series, wherein the first three PMOS tubes are in a diode mode; the gate of the NMOS transistor is connected to 1.8V. The first PMOS tube is used for generating an inter_power voltage signal, and the second PMOS tube is used for generating an inter_gnd voltage signal.
Further, the VGND voltage is derived from VDD or VGND. There are two switches for selection, the control voltages of which are respectively noted: pefbk_ P, PEFBK _ N, PEFBK _n and pefbk_p.
Further, the FBK voltages are from VDD, VDD18_post and vsspst_post. The MOS control voltages of the switches are respectively: ps_ P, PS _ N, PEFBK _ P, PEFBK _ N, HEFBK _p and hefbk_n.
The beneficial effects are that: in a chip design, IO can work in various voltage domains, and the core of the circuit is the drive of a PMOS tube, comprising: the drive circuit with the two PMOS tubes connected in series, the PGATE voltage generation circuit, the FBK generation circuit, the self-adaptive circuit, the VGND voltage generation circuit and the PGATE control switch voltage generation circuit capable of controlling the PGATE voltage generation circuit and the FBK voltage generation circuit can meet a plurality of voltage requirements, the design of the circuit is adopted to greatly improve the flexibility of the circuit, a special voltage conversion circuit is not needed, the cost and the power consumption are saved, the volume of the system is reduced, and the circuit has great practical value.
Drawings
FIG. 1 is a schematic diagram of a PMOS drive circuit according to an embodiment of the invention;
FIG. 2 is a schematic diagram of an adaptive circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a PGATE voltage generating circuit with 1.8V IO voltage according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a PGATE voltage generating circuit with 2.5V IO voltage according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a PGATE voltage generating circuit with 3.3V IO voltage according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a VGND voltage generation circuit according to an embodiment of the invention;
FIG. 7 is a schematic diagram of an FBK voltage generating circuit according to an embodiment of the invention;
FIG. 8 is a schematic diagram of the switching voltage generation circuit controlled by the FBK and PGATE at 1.8V IO according to the embodiment of the present invention;
FIG. 9 is a schematic diagram of the voltage generation circuit of the FBK and PGATE control switches and the vgnd control switch at 2.5V IO according to the embodiment of the present invention;
FIG. 10 is a schematic diagram of the switching voltage generation circuit controlled by the FBK and PGATE at 3.3V IO according to the embodiment of the present invention;
FIG. 11 is a diagram illustrating the core and PAD signal simulations at 1.8V voltage according to an embodiment of the present invention;
FIG. 12 is a diagram of core and PAD signal simulations at 2.5V voltage according to an embodiment of the present invention;
FIG. 13 is a diagram illustrating the core and PAD signal simulations at 3.5V voltage according to an embodiment of the present invention.
It should be noted that, the reference numerals at the pins of each PMOS transistor in fig. 1-10 are the same, which means that they are connected; the leftmost PS, PE and HE pins in fig. 8-10 are control pins that control the design output voltage.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the invention, fall within the scope of protection of the invention.
1-10, a multi-voltage domain CMOS IO design comprises two PMOS tubes connected in series as a drive circuit, wherein one of the PMOS tubes is marked as PGATE, the other one of the PMOS tubes is marked as FBK, the source electrode of the PMOS tube is marked as PAD, and the other ports are connected with VDDPST signals; the PGATE is connected with a plurality of PGATE voltage generating circuits in parallel, and the FBK is connected with an FBK generating circuit; each PGATE voltage generating circuit is also connected with a PGATE control switch voltage generating circuit capable of controlling the PGATE voltage generating circuit and the FBK voltage generating circuit; the circuit also comprises an adaptive circuit and a VGND voltage generation circuit, wherein the VGND voltage generation circuit is used for generating a variable VGND voltage signal; the PGATE voltage generating circuits and the PGATE control switch voltage generating circuits are connected with the adaptive circuit and the VGND voltage generating circuit.
In this embodiment, the output of the adaptive circuit includes an inter_power voltage signal and an inter_gnd voltage signal.
In this embodiment, the PGATE voltage generation circuit includes voltage generation circuits of 1.8V,2.5V, and 3.3V.
In this embodiment, the PGATE control switching voltage generation circuit includes control switching voltage generation circuits of 1.8V,2.5V, and 3.3V.
In this embodiment, the adaptive circuit includes 4 PMOS transistors connected in series, where the connection modes of the first three PMOS transistors are all that the source of the previous one is connected to the drain of the next one; the drain electrode of the fourth PMOS tube is connected with the source electrode of the third MPOS tube, the source electrode of the fourth PMOS tube is connected with VSS, and the grid electrode of the fourth PMOS tube is marked as a VDD18 interface; the grid electrode and the source electrode of the first PMOS tube are connected to be used as an inter_power voltage signal interface, the grid electrode and the source electrode of the second PMOS tube are connected to be used as an inter_gnd voltage signal interface, and the grid electrode and the source electrode of the third PMOS tube are connected to each other.
In this embodiment, the VGND voltage generating circuit is a PMOS tube having 4 drain parallel connections as VGND output, the first two source parallel connections being connected to VDD together, and the second two source parallel connections being connected to an inter_gnd voltage signal interface together; and the grid electrodes of the first PMOS tube to the fourth PMOS tube are respectively marked as follows: pefbk_ P, PEFBK _ N, PEFBK _n and pefbk_p.
In this embodiment, the FBK voltage generating circuit is a PMOS transistor with 6 drains connected in parallel as the FBK voltage signal output, the first two sources connected in parallel as the vsspst_post interface, the middle two sources connected in parallel as the VDD interface, and the last two sources connected in parallel as the VDD18_post interface, and the gates of the first to sixth PMOS transistors are respectively denoted as: ps_ P, PS _ N, PEFBK _ P, PEFBK _ N, HEFBK _p and hefbk_n.
It should be noted that, in the above description, the "one gate is referred to as PGATE", "the fourth PMOS transistor gate is referred to as VDD18 interface", "the second PMOS transistor gate is connected to the source, and is used as the inter_gnd voltage signal interface", etc. are not limited only for convenience of distinction and description; the reference numerals at the pins of each PMOS transistor in fig. 1-10 are the same to illustrate that they are connected.
When the IO design is used, as shown in fig. 8-10, three selection pins of PS, PE and HE are arranged at the leftmost end of each graph, and 1.8V,2.5V and 3.3V are selected correspondingly. While only one logic state is 1.
When the voltages of PAD are 1.8,2.5 and 3.3, FBK corresponds to 0,0.9 and 3.3. Only one choice of the switch control voltages generated by PS, PE, HE is needed at this time, as shown in fig. 7.
The adaptive circuit shown in fig. 2 is used to generate inter_power and inter_gnd, which is an adaptive circuit, and the voltage value varies with the change of VDDPST.
When vddpst=2.5v, vgnd=0.9v, otherwise vgnd=inter_gnd.
There are 3 PGATE voltage generation circuits:
at 1.8V, the control voltage of PGATE is 1.8 or 0V, respectively, which is a normal 1.8VIO circuit, but here a switching circuit is required because the usage scenario is multi-voltage. The voltages ps_n_gate and ps_p_gate controlling the switches must vary with the voltage used, otherwise problems of reliability and incorrect functioning are faced. Fig. 8 shows a circuit for generating this voltage, and the signal variation trace is [ 0.9 ] 1.8.0 ] 1.8.9, 0.9 ] inter_power,0.9 ] VDDPST, vgnd.
At 2.5V, the control voltage of PGATE is 2.5 or vgnd, respectively. Fig. 4 is used to generate the voltage of PGATE. The signal change trace is [ 0.9.0 ] - > [ 1.8.0 ] - > [ 1.8.0.9 ] - > [ VDDPST, vgnd ]. Similarly, a switch is necessary to control whether this voltage is connected to PGATE, fig. 9 is a circuit for generating this voltage, and the signal variation trace is [ 0.9 0 ] - > [ 1.8.0 ] - > [ 1.8.0.9 ] - > [ inter_power,0.9 ] - >
【inter_power,vgnd】-->【VDDPST，vgnd】。
At 3.3V, the control voltage of PGATE is 3.3 or 1.8, respectively. Fig. 5 is used to generate the voltage of PGATE. The signal change trace is [ 0.9 0 ] - > [ 1.8 0 ] - > [ 1.8.9 ] - > [ inter_power,0.9 ] - > [ inter_power,1.8 ] - > [ VDDPST,1.8 ]. Similarly, a switch is necessary to control whether this voltage is connected to PGATE, and fig. 10 is a circuit for generating this voltage, where the signal trace is [ 0.9 0 ] - > [ 1.8.0 ] - > [ 1.8.9 ] - > [ inter_power,0.9 ] - > [ inter_power,1.8 ] - > [ VDDPST,1.8 ].
The circuit designed in this way can work under different voltages, and has no reliability problem, and the performance under different voltages can be ensured.
As shown in fig. 11-13, the waveforms of the PAD end output from the driving circuit at 1.8,2.5,3.3V are very good. The design of the circuit greatly improves the flexibility of the circuit, does not need a special voltage conversion circuit, saves the cost and the power consumption, reduces the volume of the system and has great practical value.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.
Claims (7)
1. The utility model provides a many voltage domain CMOS IO designs, includes two PMOS pipes that establish ties as drive circuit, marks PGATE with the grid of one, and the grid of another marks FBK, and the source of the PMOS pipe that the grid marks PGATE is connected to VDDPST, its characterized in that: the PGATE is connected to a plurality of PGATE voltage generating circuits, and the FBK is also connected to a plurality of FBK generating circuits; each PGATE voltage generating circuit and each FBK voltage generating circuit is connected to the PGATE and the FBK through a switch; the circuit also comprises an adaptive circuit and a VGND voltage generation circuit, wherein the VGND voltage generation circuit is used for generating a variable VGND voltage signal; the PGATE voltage generating circuits and the PGATE control switch voltage generating circuits are connected with the adaptive circuit and the VGND voltage generating circuit.
2. The multi-voltage domain CMOS IO design of claim 1 wherein: the output of the adaptive circuit includes an inter_power voltage signal and an inter_gnd voltage signal.
3. The multi-voltage domain CMOS IO design of claim 1 wherein: the PGATE voltage generating circuit includes voltage generating circuits of 1.8V,2.5V, and 3.3V.
4. A multi-voltage domain CMOS IO design according to claim 3 wherein: the PGATE control switching voltage generation circuit includes control switching voltage generation circuits of 1.8V,2.5V, and 3.3V.
5. The multi-voltage domain CMOS IO design of claim 1 wherein: the self-adaptive circuit comprises 3 PMOS (P-channel metal oxide semiconductor) and 1 NMOS (N-channel metal oxide semiconductor) tubes which are connected in series, wherein the first three PMOS tubes are in a diode mode; the grid electrode of the NMOS tube is connected to 1.8V; the first PMOS tube is used for generating an inter_power voltage signal, and the second PMOS tube is used for generating an inter_gnd voltage signal.
6. The multi-voltage domain CMOS IO design of claim 2 wherein: the VGND voltage is from VDD or VGND; there are two switches for selection, the control voltages of which are respectively noted: pefbk_ P, PEFBK _ N, PEFBK _n and pefbk_p.
7. The multi-voltage domain CMOS IO design of claim 1 wherein: FBK voltages are from VDD, VDD18 POST and VSSPST POST; the MOS control voltages of the switches are respectively: ps_ P, PS _ N, PEFBK _ P, PEFBK _ N, HEFBK _p and hefbk_n.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310791908.8A CN116796679A (en) | 2023-06-30 | 2023-06-30 | Multi-voltage domain CMOS IO design |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310791908.8A CN116796679A (en) | 2023-06-30 | 2023-06-30 | Multi-voltage domain CMOS IO design |
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| Publication Number | Publication Date |
|---|---|
| CN116796679A true CN116796679A (en) | 2023-09-22 |
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| CN202310791908.8A Pending CN116796679A (en) | 2023-06-30 | 2023-06-30 | Multi-voltage domain CMOS IO design |
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- 2023-06-30 CN CN202310791908.8A patent/CN116796679A/en active Pending
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