JPH06112823A - A/d converter - Google Patents

Abstract

PURPOSE:To improve A/D conversion speed without increasing the operating speed of the hardware such as a comparator that compares a comparison reference voltage with an analog input in the case of A/D conversion. CONSTITUTION:A reference voltage generating circuit 10 is provided with high- order A/D converters 30a, 30b and low-order A/D converters 40a, 40b. The A/D conversion speed is doubled by only adding one high-order A/D converter to a conventional A/D converter provided with two low-order A/D converters with respect to one high-order A/D converter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to A / A while comparing a large number of comparison reference voltages obtained by dividing a standard voltage by using a ladder resistor in which a large number of resistance elements are connected in series with an input analog signal voltage. A / D to convert D (analog to digital)
The present invention relates to a converter, and in particular, to A / D conversion without increasing the operating speed of hardware such as a comparator that compares a comparison reference voltage with an analog signal voltage (hereinafter also referred to as an analog input) during A / D conversion. The present invention relates to an A / D converter that can improve speed.

[0002]

2. Description of the Related Art A / D converters have long been used in industrial fields such as measuring devices such as digital voltmeters and programmable power supplies. In recent years, A / D
Converters are also used in consumer products such as compact disc players and in special fields such as codecs for connecting telephones to digital lines.

A home VTR (video tape recorder)
) For special playback and noise reduction on the device,
A capable of high-speed operation of 10 to 20 MHz with 6 to 8 bits
A / D converter is used. Relatively large capacity DR
With the recent development of digital technology such as the use of AM (dynamic random access memory) at relatively low cost, A / D converters are widely used in image processing devices and digital signal processors.
A / D converters used in such image processing devices and digital signal processors are required to operate at higher speed.

A flash type A / D converter is known as an A / D converter capable of high-speed operation. This flash type A / D converter is, for example, when this is an n-bit flash type A / D converter,
A total of (2 ⁿ -1) comparators are operated simultaneously and A
/ D conversion. These total (2 ⁿ −
1) To each of the comparators, reference reference voltages which are obtained by dividing the reference voltage using a ladder resistor in which a total of 2 ⁿ resistance elements having the same resistance value are connected in series are input respectively. . Therefore, the individual comparators are
The comparison reference voltage input to each and the analog signal voltage are compared. Also, an encoded n-bit digital signal is output based on the comparison result by such a total of (2 ⁿ -1) comparators. According to such a flash type A / D converter, a digital signal corresponding to the input analog signal voltage can be obtained at a much higher speed than the integration type A / D converter or the successive approximation type A / D converter. it can.

Regarding the A / D converter capable of high-speed operation, Japanese Patent Publication No. 2-39136 discloses a technique related to what is called a two-step flash type A / D converter in recent years. The 2-step flash type A / D converter disclosed in Japanese Patent Publication No. 2-39136 is
For example, if this is an (m + n) -bit A / D converter, first (2 ^m -1) comparators are used to perform A / D conversion corresponding to the upper m bits, and then the upper m bits are equivalent. Based on the result of the A / D conversion, a total of (2 ⁿ −1) different comparators are used to perform A / D conversion corresponding to the lower n bits. Therefore, the total number of comparators used in the 2-step flash A / D converter is (2 ^{(m + n)} −2).
This is a number, and can be greatly reduced compared to the general flash type A / D converter described above.

Also, such a two-step flash type A
In recent years, a chopper type comparator has been used as a comparator of a / D converter. This chopper type comparator is a CMOS (complementary metal oxide se
miconductor) First, input analog signal voltage to the capacitor connected in series to the input of the inverter.
By shorting its input and output of the CMOS inverter, a charge Q corresponding to the analog signal voltage is stored in the capacitor. After that, the capacitor to which the analog signal voltage is input is connected to the comparison reference voltage. At this time, the output of the CMOS inverter becomes an output according to the positive or negative value of the difference between the analog signal voltage and the comparison reference voltage.

A specific example of a conventional A / D converter will be described below in more detail with reference to the drawings in order to clarify the features of the embodiments of the present invention described later.

FIG. 6 is a block diagram showing the configuration of the A / D converter of the first conventional example.

In FIG. 6, the Japanese Patent Publication No. 2-39
An example of a two-step flash type A / D converter as disclosed in 136 etc. is shown. The 2-step flash A / D converter is mainly composed of a reference voltage generating circuit 10, an upper A / D converter 30, and a lower A / D converter 40.

As will be described later with reference to FIG. 7, the reference voltage generating circuit 10 has a total of 15 comparison reference voltages VH1 to VH1 obtained by equally dividing a reference voltage using a ladder resistor in which a number of resistance elements are connected in series. VH3, VL11 to VL13, VL2
1-VL23, VL31-VL33, VL41-VL4
3 is obtained. The ladder resistance has a total of four resistance element groups (a total of four sets) in which a total of four resistance elements are connected in series and obtain a total of three comparison reference voltages VL.
Further, by connecting in series and applying a predetermined reference voltage to both ends, the comparative reference voltage VH is obtained from each series connection point of the resistance element groups.
Further, from the reference voltage generating circuit 10, such a total of 3
A total of 12 comparison reference voltages VL can be obtained together with the comparison reference voltages VH.

The upper A / D converter 30 is a chopper type comparator UCPn which will be described later in detail with reference to FIG.
It is a flash type A / D converter using a total of three. The upper A / D converter 30 includes an encoder that encodes the A / D conversion result by the chopper type comparator UCPn. The A / D converter 40 is a flash type A / D converter including a total of three chopper type comparators LCPn, which will be described later in detail with reference to FIG.
It is a D converter. The lower A / D converter 40 also includes an encoder that encodes the A / D conversion result using the chopper type comparator LCPn.

FIG. 7 is a circuit diagram of a ladder resistor used in the reference voltage generating circuit 10 of the first conventional example.

As shown in FIG. 7, the ladder resistor used in the first conventional example has a total of four resistor elements R1 to R4 connected in series and a first resistor element group. A second resistance element group in which four resistance elements R5 to R8 are connected in series, a third resistance element group in which four resistance elements R9 to R12 are connected in series, and a total of four resistance elements R13 to R
A total of four resistance element groups including a fourth resistance element group in which 16 are connected in series are further connected in series. In this way, a total of 16 resistance element groups R1 are connected in series.
A predetermined reference voltage is applied between the extreme ends of R16, that is, between the reference sign VG and the reference sign VR. The reference voltage has a minus sign on the VG side and a plus sign on the VR side. Therefore, these 16 resistance elements R1 to R in total are provided.
16 divides the reference voltage into 16 equal parts.

The comparison reference voltage VH1 is obtained from the series connection point of the first resistance element group and the second resistance element group. The comparative reference voltage VH2 is obtained from the series connection point of the second resistance element group and the third resistance element group.
The comparison reference voltage VH3 is obtained from the series connection point of the third resistance element group and the fourth resistance element group. In addition, in the first resistance element group, the comparison reference voltage VL starts from the series connection point of the resistance element R1 and the resistance element R2.
11 is obtained. The resistance element R2 and the resistance element R3
The comparative reference voltage VL12 is obtained from the point of series connection with. The comparison reference voltage VL13 is obtained from the series connection point of the resistance element R3 and the resistance element R4. Similarly,
Also in the second resistance element group, a total of three comparison reference voltages VL21 to VL23 can be obtained. Also, the third
In the resistance element group of No. 3, similarly, a total of three comparison reference voltages VL31 to VL33 are obtained. In the fourth resistance element group, a total of three comparison reference voltages VL are provided.
41 to VL43 are obtained.

FIG. 8 is a circuit diagram of a chopper type comparator used in the high-order A / D converter 30 of the first conventional example.

As shown in FIG. 8, the chopper type comparator UCPn is a CMOS (metal oxide semi).
conductor) Inverters CPAN and CPbn, capacitors C1n and C2n, switches SWCan and SWCbn
It is composed of and. The switches SWIn and SWRn are connected to the input of the chopper type comparator UCPn. The switch SWIn is connected to an analog input A which is an A / D conversion target. On the other hand, the switch SWRn is input with any one of the three comparison reference voltages VH1 to VH3 shown in FIG.

Each of the three chopper type comparators UCP1 to UCP3 in total of the upper A / D converter 30 has the different comparison reference voltages VH1 to VH3.
Has been entered. That is, each of the three chopper type comparators UCP1 to UCP3 in total compares any one of the comparison reference voltages VH1 to VH3 input to each of them with the analog input A, and outputs the comparison results, respectively. Output as OUT1 to OUT3.

When the two voltages are compared in the chopper type comparator UCPn, that is, when the magnitude relation between the analog input A and the comparison reference voltage VHn is compared, first, one voltage is applied to the chopper type comparator UC.
Input to the input of Pn to turn on both the switch SWCan and the switch SWCbn. This allows
Electric charges corresponding to the voltage input at this time are stored in the capacitors C1n and C2n.
After this, the switch SWCan and the switch SWC
Both bn are turned off, and the other voltage to be compared is input to the input of the chopper type comparator UCPn. At this time, the output of the chopper type comparator UCPn follows the sign of the difference between the two voltages to be compared.

For example, first, the switch SWIn is turned on, the switch SWRn is turned off, and the analog input A is input to the chopper type comparator UCPn. At this time, both the switch SWCan and the switch SWCbn are turned on, and charges corresponding to the voltage value of the analog input A are stored in the capacitors C1n and C2n. These capacitors C1n
And a predetermined time after the charge is stored in the capacitor C2n,
By turning off both the switch SWCan and the switch SWCbn, turning off the switch SWIn and turning on the switch SWRn,
The comparison reference voltage VHn is input to the chopper type comparator UCPn. When the comparison reference voltage VHn is input, the chopper type comparator UCPn outputs to the output OUTn corresponding to the positive / negative difference value between the analog input A and the comparison reference voltage VHn.

FIG. 9 shows the lower A / D of the first conventional example.
It is a circuit diagram about the chopper type comparator used for a converter.

As shown in FIG. 9, the chopper type comparator LCPn is similar to the chopper type comparator UCPn in the CMOS inverter CP.
It is composed of an and CPbn, capacitors C1n and C2n, and switches SWCan and SWCbn.
Regarding the chopper type comparator LCPn,
There are a total of five switches at its input, namely switch S
WIn and SWL1n to SWL4n are connected.
An analog input A to be A / D converted is connected to the switch SWIn. The switch SWL1n
To SWL4n respectively, the comparison reference voltage VL1n
.About.VL4n are connected. Regarding the three chopper type comparators LCP1 to LCP3 used in the lower A / D converter 40, the switch SWL1
n to SWL4n are, specifically, the switch SWL11 to SWL11.
SWL41, SWL12 to SWL42, SWL13 to S
WL43 (hereinafter, these 12 switches in total are collectively referred to as a switch matrix SWL),
Each of the comparison reference voltages VL11 to VL41,
VL12 to VL42 and VL13 to VL43 are connected.

As described above, the lower A / D converter 40 uses a total of three chopper type comparators LCPn as shown in FIG. 9. First, the first chopper type comparator LCPn is used. Regarding the comparator LCP1, a switch SWL11 is provided, and the comparison reference voltage VL11 of the first resistance element group is supplied to the switch SW.
It is turned on and off at L11. The switch SWL21 is provided in the first resistance element group, and the reference voltage VL21 obtained from the second resistance element group is
The switch SWL21 is turned on / off. Further, the switch SWL31 is provided, and the comparison reference voltage VL31 obtained from the third resistance element group is turned on / off by the switch SWL31. The switch SWL
41 is provided, and the comparison reference voltage VL41 obtained from the fourth resistance element group is turned on / off by the switch SWL41.

Next, with respect to the second chopper type comparator LCPn, the switch SWL12 is provided, and the comparison reference voltage VL12 obtained from the first resistance element group is turned on / off by the switch SWL12. . Further, the switch SWL22 is provided, and the comparison reference voltage VL22 obtained from the second resistance element group is provided.
Is turned on / off by the switch SWL22. The switch SWL32 is provided, and the comparison reference voltage VL32 obtained from the third resistance element group is turned on / off by the switch SWL32. The switch SWL
42 is provided, and the comparison reference voltage VL42 obtained from the fourth resistance element group is turned on / off by the switch SWL42.

Next, in the third chopper type comparator LCP3, the switch SWL13 is provided, and the comparison reference voltage VL13 obtained from the first resistance element group is turned on / off by the switch SWL13. . The switch SWL23 is provided, and the comparison reference voltage VL23 obtained from the second resistance element group is
The switch SWL23 is turned on / off. The switch SWL33 is provided, and the comparison reference voltage VL33 obtained from the third resistance element group is the switch SWL.
It is turned on and off at L33. The switch SWL43
And the comparison reference voltage VL43 obtained from the fourth resistance element group is turned on / off by the switch SWL43.

The lower A / D converter 40, which uses a total of three chopper type comparators LCPn, explained above, is the A / D converter of the upper A / D converter 30.
It operates according to the D conversion result. That is, according to the A / D conversion result of the higher-order A / D converter 30, the comparison reference voltage VL of one of the resistance element groups out of three in total.
To the lower A / D converter, the switch SWL
11 to SWL13, SWL21 to SWL23, SWL3
1 to SWL33 and SWL41 to SWL43 are selected by the switch matrix SWL. This is the top A
Based on the A / D conversion result of the A / D converter 30, the switches SWL1n, SWL2n, SWL3n and SWL of the chopper type comparator LCPn of each of the lower A / D converters 40 as shown in FIG.
Any one of WL4n is turned on. This relationship is as shown below.

(1) The analog input A is the upper A /
At the time of the A / D conversion operation in the D converter 30, when it is determined that the comparison reference voltage is VH1 or less: the switch S
WL11, SWL12, and SWL13 are turned on, and other switches are turned off.

(2) The analog input A is larger than the comparison reference voltage VH1, and the comparison reference voltage VH
If it is smaller than H2: the switch SWL2
1, SWL22 and SWL23 are turned on and the other switches are turned off.

(3) The analog input A is larger than the comparison reference voltage VH2 and the comparison reference voltage VH
If it is determined to be H3 or less: the switch SWL3
1, SWL32 and SWL33 are turned on and the other switches are turned off.

(4) When the analog input A is larger than the comparison reference voltage VH3: The switches SWL41, SWL42 and SWL43 are turned on,
The other switches are off.

In the lower A / D converter 40,
Thus, when each switch is turned on / off and connected to the predetermined resistance element group, all the comparators LCP are
For n, the analog input A is compared, and the result is encoded and becomes the A / D conversion result of the lower bit.

FIG. 10 is a time chart showing the operation of the A / D converter of the first conventional example.

In FIG. 10, the waveform of the analog input A to be A / D converted in the A / D converter of the first conventional example, the operating state of the upper A / D converter 30, and the upper A Comparison reference voltage VL input to the lower A / D converter 40, which is determined based on the A / D conversion result of the A / D converter 30, the operating state of the lower A / D converter 40, and the first conventional method. The digital output D output from the example A / D converter is shown.

First, in FIG. 10, at time t ₁ , sampling of the analog input A (n) to be A / D converted by the upper A / D converter 30 and the lower A / D converter 40 is performed. Be started. That is, at the time t ₁ , the switch SW shown in FIG.
In, SWCan and SWCbn are turned on, and the switch SWRn is turned off. Further, at the time t ₁ , the switches SWIn, SWCan and SWCbn of FIG.
Is turned on, and the switches SWL1n to SWL4n are turned off.

Sampling is started at the time t ₁ , charges corresponding to the analog input A are stored in the capacitors C1n and C2n of FIG. 8, and the analog input A is stored in the capacitors C1n and C2n of FIG. Is stored, and at time t ₂ , sampling of the upper A / D converter 30 and lower A / D conversion are performed.
The sampling of the D converter 40 is completed.
That is, in the time t _2, the switch SWI of the 8
All of n, SWCan and SWCbn are turned off, and all of the switches SWIn, SWCan and SWCbn of FIG. 9 are turned off. When the switches of the high-order A / D converter 30 and the low-order A / D converter 40 are turned off, the respective sampling operations are completed. Further, at the time t ₂ , the switch SWRn shown in FIG. 8 of the upper A / D converter 30 is turned on, and the comparison operation (A / D conversion operation) in the upper A / D converter 30 is started. To be done.

When the A / D conversion is completed by the comparison operation in the upper A / D converter 30, the switch matrix SWL is set correspondingly, and the lower A
The comparison reference voltage VL input to the / D converter 40
Output of (n) starts. Then, at time t _4, the comparison operation of the lower A / D converter 40, i.e. A / D conversion is started. The A / D conversion of the lower A / D converter 40 ends at time t ₅ . Therefore, at the time t ₅ , all A / D conversion started from the time t ₁ is completed, and the digital output D (n) is output. In the digital output D, the upper 2 bits are the A / D conversion result of the upper A / D converter 30, and the lower 2 bits are the A / D conversion result of the lower A / D converter 40. Incidentally, in this time t _5, the next A / D conversion is started.

As described above with reference to FIG.
The A / D converter of the first conventional example is based on the high-order A / D
The analog input A is A / D converted while the converter 30 and the lower A / D converter 40 operate alternately. Therefore, general flash type A
Compared with the / D converter, the 2-step flash A / D converter as in the first conventional example has a double A / D conversion time.

FIG. 11 is a block diagram showing the structure of the A / D converter of the second conventional example.

A / D of the second conventional example shown in FIG.
The converter is one upper A / D converter,
This is a two-step flash type A / D converter in which a total of two lower A / D converters are used. The A / D converter mainly includes a reference voltage generating circuit 10 and a high-order A / D converter.
It has a D converter 30, a total of two lower A / D converters 40a and 40b, and a selector 52. The respective configurations of these second conventional examples are the same as those of the above-mentioned first conventional example. The lower A / D converters 40a and 40b have the same configuration as that of the lower A / D converter 40 of the first conventional example. Further, in FIG. 11, the selector 52 outputs one of the outputs of the lower A / D converters 40a and 40b which operate alternately to the digital output D, as will be described later with reference to FIG. It is to switch. The A / D converter of the second conventional example uses a total of two lower A / D converters 40a and 40b in this way, so that the A / D conversion speed of the A / D converter of the first conventional example is The speed has doubled.

FIG. 12 is a time chart showing the operation of the second conventional A / D converter.

In FIG. 12, the waveform of the analog input A to be A / D converted by the A / D converter of the second conventional example, the operating state of the upper A / D converter 30, and the upper A The reference voltage VL set by the A / D converter 30, the operating state of the lower A / D converter 40a, and the lower A / D converter 40b.
2 and the digital output D output from the A / D converter of the second conventional example are shown.

First, in the flow chart of FIG.
At time t₁From time t₂In the period of, the upper A / D
The converter 30 and the lower A / D converter 40a
The analog input A (n) is sampled. or,
After this time t₂From time t ₃Up to the above in the period
The A / D converter 30 is the above sampling result.
A / D conversion is performed based on The A / D conversion is completed
And the following time t₃From time t_FiveIn the period up to
According to the A / D conversion result of the upper A / D converter 30,
Therefore, refer to the comparison to the lower A / D converter 40a.
The illumination voltage VL (n) is set. The comparison reference voltage VL (n
 ) Is set, the subsequent time t_Four~ Time t_FiveIn the period
In the lower A / D converter 40a,
D conversion is performed. When the A / D conversion is completed,
Tick t₁~ Time t₂Before sampled in the period
The analog input A (n) A / D conversion result,
The digital output D (n) is the time t_Five~ Time t₇Period output
To be done.

In the A / D converter of the second conventional example, unlike the A / D converter of the first conventional example, the lower A / D converter 40a performs A / D conversion and the like. Period, that is, time t in FIG.
Even during the period from ₃ to time t ₅ , the upper A / D
The converter 30 is operating. This is because the analog input A (n + 1) is A / D converted by the other lower A / D converter 40b.

As described above, the A / D converter of the second conventional example has the lower A / D converters 40a and 40b.
By providing two in total, these are operated alternately, and the processing speed of the A / D converter of the first conventional example is 2
The processing speed is doubled. That is, according to the A / D converter of the second conventional example, the 2-step flash type A
Even if it is a / D converter, a general flash type A /
The same processing speed as the D converter can be achieved.

[0044]

However, the A / D conversion speed of the above-mentioned second conventional example A / D converter is improved, and even if it is twice as fast as that of the above-mentioned first conventional example, it is faster. A conversion rate A / D converter is desired. In order to improve the A / D conversion speed of the A / D converter, firstly, the operation speed of hardware such as a comparator that compares the comparison reference voltage with the analog input A at the time of A / D conversion. Can be improved. However, there is a limit to the improvement of the operation speed of such hardware, and there is also a problem in terms of cost, etc. Therefore, the A / D conversion speed can be improved by improving the configuration of the A / D converter. The need for improvement is high.

The present invention was made to solve the above-mentioned conventional problems, and the operating speed of hardware such as a comparator for comparing the comparison reference voltage with the analog input during A / D conversion. It is an object of the present invention to provide an A / D converter that can improve the A / D conversion speed without improving the above.

[0046]

According to the present invention, a plurality of comparison reference circuits in which a reference voltage is divided by a ladder resistor in which a plurality of resistance elements are connected in series are compared with an input analog signal voltage. In an A / D converter for A / D conversion, a plurality of resistance element groups in which a plurality of resistance elements are connected in series to obtain a plurality of comparison reference voltages VL are further connected in series,
The ladder resistor is configured to obtain the comparative reference voltage VH from each of the series connection points of the resistance element groups, and the analog reference voltage is A / D by using the comparative reference voltage VH.
A high-order A / D converter to convert, and one of a plurality
Using the comparative reference voltage VL of the two resistive element groups,
According to the A / D conversion result of the lower A / D converter that performs A / D conversion of the analog signal voltage and the higher A / D converter, the comparison reference voltage VL of one of the plurality of resistance element groups, Switch matrix SWL selected as comparison reference voltage of the lower A / D converter
The above object is achieved by providing a plurality of sets of the upper A / D converter, the lower A / D converter, and the switch matrix SWL for the ladder resistor.

[0047]

In the present invention, in order to improve the conversion speed of the 2-step flash type A / D converter, a plurality of sets of the upper A / D converter, the lower A / D converter, and the switch matrix SWL are used. It was made by finding the composition. If a plurality of independent A / D converters are used to operate sequentially, the A / D
The D conversion speed can be improved. However, the required hardware, such as the number of comparators used, increases by the number of A / D converters used. Further, the respective A / D converters are provided with different ladder resistors, which causes a problem of variation in the ladder resistors. Conventionally, it has been performed that a conversion error caused by the ladder resistance or the like is obtained in advance and the obtained digital output is corrected by this. However, it is extremely difficult to make such a correction when a plurality of A / D converters having different characteristics are sequentially operated.

Focusing on such a point, the present invention forms a set of the upper A / D converter, the lower A / D converter, and the switch matrix SWL for a single ladder resistor. I am trying to prepare multiple sets of items. As a result, the problem of the conversion error related to the ladder resistance as described above and the increase in hardware are reduced. For example, in an embodiment described later, two sets of the upper A / D converter, the lower A / D converter, and the switch matrix SWL are provided. Thus, for example, compared with the second conventional example, the A / D conversion speed can be doubled even though the number of the upper A / D converters is increased by one.

[0049]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the A / D converter of the first embodiment to which the present invention is applied.

As shown in FIG. 1, the A / D converter of the first embodiment mainly comprises a reference voltage generating circuit 10 and two A / D converters 30a and 30b in total.
And a total of two lower A / D converters 40a and 40b
And selectors 50 and 52.

The reference voltage generating circuit 10 is the same as that having the same reference numeral as described above with reference to FIG. The upper A / D converters 30a and 30b are the same as those described above with reference to FIG. A feature of this embodiment is that such upper A / D converters 30a and 30 are provided.
Two b's are provided in total. In addition, such a total of two high-order A / D converters 30a and 30b.
The operation of the entire A / D converter using
This will be described later in detail using the time chart of.

The lower A / D converters 40a and 40
Similar to the second conventional example described above with reference to FIG. 11, two b are provided. Also, the lower A /
The specific circuits of the D converters 40a and 40b are almost the same as those described above with reference to FIG. 9, but there are some differences. The lower A / D converters 40a and 40
Details of b will be described later with reference to FIG.

The selector 50 corresponds to A of the first embodiment.
The A / D conversion result of the upper A / D converter 30a or the A / D conversion result of the higher A / D converter 30b is used as the upper bit of the digital output D of the overall output of the A / D converter. To do. Further, the selector 52 uses the A / D conversion result of the lower A / D converter 40a as the lower bit of the digital output D of the output of the entire A / D converter of the first embodiment,
Whether or not to use the A / D conversion result of the lower A / D converter 40b is selectively switched. In this embodiment, the output of the selector 50 is a binary output of 2 bits in total. The output of the selector 52 is also a binary output of 2 bits in total. That is, the digital output D of the entire A / D converter is a binary output of 4 bits in total.

FIG. 2 shows the lower A / D of the first embodiment.
It is one circuit diagram of a total of three chopper type comparators LCPn used in a converter.

The portion surrounded by the alternate long and short dash line of the chopper type comparator LCPn shown in FIG. 2 is the same as that described above with reference to FIG.
The chopper type comparator LCPn of the first embodiment
Regarding the input part, unlike the one shown in FIG. 9, the switch SWIn and the switch SWRn are connected. An analog input A to be A / D converted is input to the switch SWIn. On the other hand, the switches SWR1n to SWL are connected to the switch SWRn.
4n and are connected.

These switches SWIn and switches SWR
N and n are not turned on, and only one of them is turned on. When the switch SWIn is turned on, the analog input A is input to the input of the chopper type comparator LCPn. On the other hand, when the switch SWRn is turned on, the comparison reference voltage VL1 described above with reference to FIG. 7 is input to the input of the chopper type comparator LCPn.
Any one of n to VL4n is input. The comparison reference voltage VL1n is a comparison reference voltage VL of the first resistance element group, the comparison reference voltage VL2n is a comparison reference voltage VL of the second resistance element group, the comparison reference voltage VL3n is the comparison reference voltage VL with the third resistance element group, and the comparison reference voltage VL4n is one of the comparison reference voltages VL with the fourth resistance element group. That is, in the chopper type comparator LCPn of the lower A / D converters 40a and 40b used in the first embodiment, the switch SWRn is added and the switch SWL1 is added as compared with the chopper type comparator LCPn of FIG.
When any of n to SWL4n is turned on, the switch SWRn is also turned on.

In the chopper type comparator LCPn shown in FIG. 2, when the switch SWIn is turned on and the analog input A is input, the switch SWRn is turned off so that the analog input A
The load amount on the chopper type comparator LCPn with respect to is reduced. The load of the chopper type comparator LCPn viewed from the analog input A side is only the chopper type comparator LCPn itself indicated by the one-dot chain line and the switch SWRn that is off. In comparison, in the chopper type comparator LCPn shown in FIG. 9, the load of the chopper type comparator LCPn seen from the analog input A side is off with the chopper type comparator LCPn itself shown by the chain line. There are a total of 4 switches SWL
1n to SWL4n.

As will be described later in detail, the chopper type comparator LCPn and its peripheral circuit shown in FIG. 2 are also used in the second embodiment described later. In the case of the second embodiment, an analog input V which is an output of a delay element 56 described later is applied to the switch SWIn of FIG.
IN will be input.

FIG. 3 is a time chart showing the operation of the first embodiment.

In the time chart of FIG. 3, A
The lower A / D that is output based on the waveform of the analog input A that is the target of the D / D conversion, the operating state of the upper A / D converter 30a, and the A / D conversion result of the upper A / D converter 30a. The comparison reference voltage VL used in the converter 40a and the lower A / D converter 40
The comparison used by the lower A / D converter 40b, which is set based on the operating state of a, the operating state of the upper A / D converter 30b, and the A / D conversion result of the upper A / D converter 30b. The reference voltage VL, the operating state of the lower A / D converter 40b, and the digital output D output as the A / D conversion result of the entire A / D converter of the second embodiment are shown.

The digital output D is, at a certain point of time, a total of 2 high-order bits of the A / D conversion result of the high-order A / D converter 30a and A / D conversion of the low-order A / D converter 40b. It is a combination of the lower 2 bits of the total 2 bits of the result. Alternatively, the digital output D at another point of time is the high-order A / D converter 30.
It is a combination of a total of 2 high-order bits of the A / D conversion result of b and a low-order bit of the 2-bit A / D conversion result of the low-order A / D converter 40a.

First, in the time chart of FIG. 3, in the period from time t ₁ to time t ₂ , the upper A / D
The converter 30a and the lower A / D converter 40b
Of the analog input A (n), that is, sampling is performed. The sampling is confirmed at time t ₂ .
Subsequently, in the period from time t ₂ to time t ₃ , the A / D of the upper A / D converter 30a and the lower A / D converter 40b sampled in the period from the time t ₁ to the time t ₂ is sampled. The conversion operation, that is, the comparison operation is performed. The comparison reference voltage VL used in the comparison operation of the lower A / D converter 40b is the upper A / D
It is output by the converter 30b and is in accordance with the A / D conversion result of the analog input A (n-1).

This comparison operation in the lower A / D converter 40b is intended for the analog input n, and the comparison reference voltage VL used in the lower A / D converter 40b is the analog input (n-1). Since it is used as a reference, there are some differences in the sampling time of the analog input A. The analog input A, which is the object of A / D conversion in this embodiment, is a continuous signal. Therefore, the comparison reference voltage VL (n -1) obtained as the A / D conversion result (upper bit) of the upper A / D converter 30b for the analog input (n -1) and the upper A of the analog input n. It is assumed that these are the same as the comparative reference voltage VL (n) obtained as the A / D conversion result of the / D converter 30b. That is, the comparison reference voltage VL (n
-1) is the expected output of the comparative reference voltage VL (n).

In the period from time t ₂ to time t ₃ ,
The digital output D having the A / D conversion result of the upper A / D converter 30a as the upper bit and the lower A / D conversion result 40b as the lower bit is output.

On the other hand, in the period from the time t ₂ to the time t ₃ , the upper A / D converter 30b and the lower A
The analog input (n + 1) of the / D converter 40a is sampled. The sampling is performed at the time t
Confirm with ₃ .

Next, in the period from the time t ₃ to the time t ₄ , the upper A / D converter 30b and the lower A / D converter 40a sampled in the period from the time t ₂ to the time t ₃ are sampled. Each comparison operation is performed. The comparison operation of the upper A / D converter 30b is performed for the analog input (n + 1). or,
The comparison operation of the lower A / D converter 40a is performed by comparing the analog input (n + 1) and the upper A of the analog input (n).
8 is a comparison of the A / D conversion result of the / D converter 30a with the comparison reference voltage VL (n). The comparison reference voltage VL
(N) is the expected output of the comparative reference voltage VL (n + 1).

From time t ₃ to time t ₄ , the upper A
The digital output D having the A / D conversion result of the / D converter 30b as the upper bit and the A / D conversion result of the lower A / D converter 40a as the lower bit is output.

After time t ₄ , the same A
A / D conversion operation is performed, and the upper A / D converter 3
The A / D conversion result of 0a is used as the upper bit and the lower A / D
The digital output D whose lower bit is the A / D conversion result of the D converter 40b, and the upper A / D converter 3
The A / D conversion result of 0b is used as the upper bit, and the lower A / D
The A / D conversion result of the D converter 40a and the digital output D whose lower bits are output alternately.

As described above, according to the first embodiment, the operating speed of hardware such as a comparator for comparing the comparison reference voltage with the analog input A is not increased,
The A / D conversion speed can be improved. For example, as compared with the second conventional example, the number of the upper A / D converters 30a and 30b is two in total, and the A / D conversion speed is doubled by only increasing the number of the upper A / D converters by one. ing.

FIG. 4 is a block diagram showing the configuration of the A / D converter of the second embodiment to which the present invention is applied.

As shown in FIG. 4, the A / D converter of the second embodiment is different from the A / D converter of the first embodiment described with reference to FIG. 1 in the delay circuit 56.
Has been added. The delay circuit 56 converts the analog input A into 1 of the time chart of FIG. 3 and FIG. 5 described later.
The unit period t ₁ is delayed by one unit period t 1 as shown by, for example, one period from time t ₁ to time t ₂ or one period from time t ₂ to time t ₃ . That is, the upper A / D converters 30a and 3
0b, 1 of the lower A / D converters 40a and 40b
It is delayed by the period of one comparison operation or one sample operation. The delay circuit 56 is composed of a sampling and holding circuit.

Further, the selector 50a used in the second embodiment is the A / D converter of the upper A / D converter 30a.
The conversion result and the A / D of the upper A / D converter 30b
When outputting the conversion result, it has a delay circuit for delaying the conversion result by the one unit period t. Such a delay circuit of the selector 50a is constructed by using a latch circuit.

FIG. 5 is a time chart showing the operation of the second embodiment.

In the second embodiment, time t in FIG.
_The digital output D output during the period from ₂ to the time t ₃ has the A / D conversion result of the analog input (n −1) of the upper A / D converter 30a as the upper bit and the lower A / D converter. The lower bit is the A / D conversion result of the analog input (n-1) of 40b. Further, in the A / D conversion in the lower A / D converter 40b, the comparison reference voltage VL (n-n according to the A / D conversion result of the analog input (n-1) by the higher A / D converter 30b. 1) is used.

Also during the period from time t ₃ to time t ₄ , the A / D conversion result of the analog input n by the upper A / D converter 30b is set as the upper bit and the analog input of the lower A / D converter 40a is set. The digital output D having the A / D conversion result of n as the lower bit is output. A comparison reference voltage VL (n) based on the A / D conversion result of the higher A / D converter 40a is used for the A / D conversion in the lower A / D converter 40a.

As described above, in the second embodiment, the selector 50a including the delay circuit 56 and the delay circuit allows the lower A / D converters 40a and 40b to use the corresponding comparison reference voltage VL. ing. For example, when the lower A / D converter 40a or 40b A / D converts the analog input A (n),
The comparison reference voltage VL (n) that corresponds to this correctly is used. Further, when outputting the digital output D, by using the selector 50a having a delay circuit, the upper bit and the lower bit obtained by converting the corresponding analog input are combined and output. For example, the analog input A (n) that has undergone upper A / D conversion and the analog input A (n) that correctly corresponds to this has undergone lower A / D conversion are combined and output.

[0078]

As described above, according to the present invention, A
It is possible to obtain an excellent effect that the A / D conversion speed can be improved without increasing the operation speed of hardware such as a comparator that compares a comparison reference voltage and an analog input during the D / D conversion. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an A / D converter of a first embodiment to which the present invention is applied.

FIG. 2 is a circuit diagram showing a chopper type comparator of a lower A / D converter used in the first embodiment and circuits around the chopper comparator.

FIG. 3 is a time chart showing the operation of the first embodiment.

FIG. 4 is a block diagram showing a configuration of an A / D converter according to a second embodiment of the present invention.

FIG. 5 is a time chart showing the operation of the second embodiment.

FIG. 6 is a block diagram showing a configuration of an A / D converter of a first conventional example.

FIG. 7 is a circuit diagram of a ladder resistance of a reference voltage generating circuit used in the first conventional example.

FIG. 8 is a circuit diagram of a chopper type comparator of an upper A / D converter used in the first conventional example and its peripherals.

FIG. 9 is a circuit diagram showing a chopper type comparator of a lower A / D converter used in the first conventional example and a circuit around it.

FIG. 10 is a time chart showing the operation of the first conventional example.

FIG. 11 is a block diagram showing a configuration of an A / D converter of a second conventional example.

FIG. 12 is a time chart showing the operation of the second conventional example.

[Explanation of reference numerals] 10 ... Reference voltage generating circuit 30, 30a, 30b ... Upper A / D converter 40, 40a, 40b ... Lower A / D converter 50, 52 ... Selector 50a ... Selector 56 having delay circuit ... Delay circuit UCPn , LCPn ... Chopper type comparators CPan, CPbn ... CMOS inverters C1n, C2n ... Capacitors R1 to R16 ... Resistor elements VL, VL11 to VL13, VL21 to VL23, VL
31-VL33, VL41-VL43, VL (a), V
L (b), VH1 to VH3 ... Comparative reference voltage

Claims (1)

[Claims] 1. An A / D that performs A / D conversion while comparing a plurality of comparison reference circuits in which a reference voltage is divided using a ladder resistor in which a plurality of resistance elements are connected in series with an input analog signal voltage. In the converter, a plurality of comparison reference voltages V in which a plurality of resistance elements are connected in series
A plurality of resistance element groups for obtaining L are further connected in series, and the comparison reference voltage VH is obtained from each series connection point of the resistance element groups.
And a higher-order A / D converter that A / D-converts the analog signal voltage by using the comparison reference voltage VH, and the ladder resistor is configured to obtain one of the resistance element groups. According to the A / D conversion result of the lower A / D converter for A / D converting the analog signal voltage by using the comparison reference voltage VL, and the upper A / D converter,
A switch matrix SWL that selects the comparison reference voltage VL of one of the plurality of resistance element groups as a comparison reference voltage of the lower A / D converter, and the upper A / D converter and the lower A / D converter. An A / D converter comprising a switch matrix SWL and a plurality of sets for the ladder resistor.