JPS60102024A - Analog-digital conversion system - Google Patents

Abstract

PURPOSE:To obtain a small-sized, fast A/D converter with small power consumption by using the same (n)-bit A/D converter twice repeatedly and thus obtaining a digital signal consisting of (n) high-order digit bits and (n) low-order digit bits. CONSTITUTION:An analog signal Vin inputted to an input terminal 20 is inputted to a sample holding circuit 21 and when a decision on the high-order digit bits is made, a reference voltage changeover switch 25 is placed at the side of the full-scale reference voltage VFS of a reference voltage generating circuit; and this is used as the reference voltage of the (n)-bit A/D converter 22 to convert the analog signal Vin from analog to digital, and thus the high-order (n)-bit signal is obtained and applied to a register 27 and a D/A converter 23. When a decision on the low-order digit bits is made, the reference voltage changeover switch 25 is placed at the side of the 1/2<n> full-scale reference voltage VFS/2<n> and the reference voltage is used as the reference voltage of the A/D converter 22; and the difference obtained by subtracting the output of the D/A converter 23 from the input analog signal Vin is A/D-converted to obtain the low-order (n)-bit signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an improvement in a serial-parallel type analog-to-digital conversion system.

[Prior art]

As is well known, a fully parallel comparison type analog-to-digital converter (A/D converter) can perform A/D conversion at high speed, but in the case of an A/D converter with N-bit resolution, , 2N-1 voltage comparators are required, and the number of voltage comparators increases exponentially as the number of pins increases. To solve this problem, a so-called serial-parallel type A/D converter has been proposed, which converts an input analog signal by dividing it into upper bits and lower bits.

Figure 1 shows a 2 n (2r1=N) bit series/parallel type A/
This is a conventional example of a D converter. In FIG. 1, an input analog signal Vin is input from an input terminal 10 to a sample and hold circuit 11, where it is sampled and held. This held analog signal is first converted into a digital signal of upper Tl bits by the 1-bit A/D converter 12. The output of the A/D converter 12 is then input to the n-bit D/A converter 13, which outputs the analog voltage corresponding to the digital (number 8) of the upper n pins.This output voltage and the sample hold circuit The subtracter 14 generates a difference between the input signal voltage held in the input signal voltage 11 and the difference voltage as "1 bit A".
The signal is input to the /D converter 15 and converted into a digital signal of lower r1 bits.

In this series/parallel A/D converter, the first n bits A/D
The voltage ratio of the converter 12 and the number of dividers are 2n-1.

The voltage comparator of the next n-bit A/D converter 15 is also the same (2
The number of voltage comparators is n-1, and the number of voltage comparators is very small compared to one 2Z0 required in an all-parallel comparison type A/D converter. Therefore, in the conventional configuration shown in Figure 1,
A/D conversion excess f111 during the previous half cycle] - 11
When the bit A/D converter 12 is in operation, the lower one bit A/D converter 15 is inactive and the state is reversed in the next half cycle.

That is, since each Δ/1] converter performs unnecessary operations b), it has the disadvantage of requiring extra hardware and consuming extra power.

[LI style of invention]

An object of the present invention is to eliminate the drawbacks of the conventional series/parallel type A/D converters described in 1. and provide a small, high-speed, low power consumption A/D converter.

[Summary of the invention]

The present invention uses the same 11-bit A/D converter twice to perform N-2n-bit A/D conversion. [It is characterized by obtaining a digital signal 4 of bits and lower n bits 1-.

[Embodiments of the invention]

FIG. 2 is a diagram showing the basic structure of the present invention, in which 2011 is an input terminal, 2nd line is an () simple hold circuit, 22nd line is an n-bit A/L converter, 23 is an n-bit D/A converter, 24 is an analog subtracter, 25 is a reference voltage changeover switch, 26 is a reference voltage generation circuit, and 27 is a 20-bit output register.

The analog signal Vin input to the input terminal 20 is sampled and held in the sample hold circuit 21 and then input to the subtracter 24 hi. In the first cycle for determining 1 bit, n pin 1 to D/A converter 2
The output of 3 is O. therefore.

The input analog signal Vin becomes the output of the subtracter 24 as it is, and is input to the n-bit A/D converter 22 to obtain a digital signal of the upper n bits. At this time, the switch 25 is on the Vi side of the reference voltage generation circuit 26, and
A full scale pressure of Fg is applied to the n-bit A/D converter 22.

The high-order n-bit digital signal is stored in the high-order bit of the register 27, and is also applied to the n-bit D/A converter 23, where it is converted into an analog signal.

The analog output from the D/A converter 23 is input to the subtracter 4, and the sampled and held input analog signal Vin
Subtraction from 9 is performed. The noise subtraction output is again input to the n-bit A/D converter 22, and a digital signal of the lower n bits is obtained. At this time, the switch 25 switches to the VS'/2n side of the reference voltage circuit 26, and the reference voltage of the n-bit A/D converter 22 is Vi/2''. The lower n bits of digital obtained in step 22 are also stored in the lower n bits of register 27, and together with the previous 1- bit, 2n bits of digital (i+ is output from register 27). be done.

As mentioned above, in Figure 2. Only one n-bit A/D converter is required, and a conversion speed equivalent to that of the configuration shown in FIG. 1 can be obtained.

FIG. 3 shows a specific configuration example in the case of 20=8 bits, in which the sample hold circuit 21 and the D/A converter 2 shown in FIG.
3. There is an example in which a function equivalent to the subtracter 24 is realized using only a weighting capacitor and a switch, thereby simplifying the circuit, achieving higher precision, lower power consumption, and smaller size. In Figure 3, 30
is the input terminal, SWl is the sampling switch, SW2
is a switch that changes the reference voltage ±vR applied to the capacitor series C to 4C, SW3 to SW5 are switches that switch one end of the capacitor series to ground or the reference voltage, C is the unit capacity, 2C is the capacity twice the unit capacity, and qC is the switch that changes the reference voltage ±vR applied to the capacitor series C to 4C. It has four times the capacity. 31 is 15
32 is an encoder that converts the outputs of the 15 voltage comparators into 4-bit codes;
33 is an 8-bit register + rl-rlg is a string of 16 resistors with equal values.

R is a unit resistance, and 7R is a resistance seven times the unit resistance. 3
4 and 35 are buffer amplifiers with a gain of 1, and SW6 is a resistor string r.
1~r A switch for switching the voltage on the r side of to to earth voltage, negative reference voltage -vR, or -V□/8 of the output of the buffer amplifier 35, SWl is the resistor series rI This switch is used to select whether the voltage on the rIll side of -rlG is the ground voltage, the positive reference voltage vR, or VR/8 of the output of the buffer amplifier 34.

First, SWl is turned on, SW3 to SW5 are switched to ground, and the analog signal Vin applied to the input terminal 30 is sampled.

Next, only the switch SWI is turned off, and the capacitor column C
The analog value vh is held at ~4C. Next, in order to convert the upper bits, SW6 is set to -vIl side, and SWl is set to VIl side.
Switching to the rl side, the full scale 2vFI reference voltage is divided into 16 by the resistor array r1 to r18, and is applied to the 15 voltage comparators 31 as a reference voltage for the upper 4 bits. On the other hand, the analog voltage Vb held in the capacitor arrays C to 4C is also input to the voltage comparator group 31, and the reference voltage 2V,
compared to The comparison results of the 15 voltage comparators 31 are applied to the encoder 32 and converted into an upper 4-bit code. This high-order 4-bit code output is held in the high-order bits of register 33, and the most significant bit
- The switches SW2 to SW5 are controlled in order from the (MSB) side. That is, when the polarity of the holding analog voltage V h is positive (when the MSB is 1), SW2 switches to the -V11 side, and the capacitor series C to C4C are switched to the -V11 side under the control of SW3 to SW5 using the remaining 3 bits. Vh-Vo/8・m
Subtraction (m=0, 1, -, 7) is performed, and a voltage between 0 and vR/8 is applied to the voltage comparator group 31. At this time, SWl is switched to the output of the buffer amplifier 34, and SWl is switched to the output of the buffer amplifier 34.
6 switches to ground. On the other hand, when the polarity of the holding analog voltage V h is negative (when the MSB is 0), 6W2 is V
Switch to the II side, and under the control of SW3 to SW5, the capacitance series C to
At 4C, Vh+VR/s ・m (m = o
r ip..., 7) is performed, and the voltage comparator group 3
1 is applied with a voltage between 0 and -V n /8. At this time, SWl is switched to ground, and SW6 is switched to the output of the buffer amplifier 35. The voltage of Vn/s or -vR/8 applied to the resistor examples r, ~r, 6 is the resistor string r, ~r6
The voltage is divided into 16 by , and is input to the voltage comparator group 31 as a reference voltage for the lower 4 bits.

This reference voltage and analog voltage Vh+V, /8・m are 15
The voltage comparators 31 compare the voltages, and the comparison results are sent to the encoder 32.
The lower 4-bit code is converted by /\. The lower 4-bit code output is input to the lower bits of register 33, and together with the upper 4 bits previously held, the final 8
Form a bit code.

FIG. 4 shows another example of the configuration when 2n=8 bits,
The difference from FIG. 3 is that 16 capacitor strings with the same value are used instead of the resistor strings r□ to r4, and switches 5L- to 5L- are used to connect the connection nodes of the capacitor strings to the ground voltage.
315 is provided, thereby eliminating the need for buffer amplifiers 3/1 and 35.

A/l) Before starting the conversion, 81 to S15. SW6
, SW1 are switched to the ground voltage side, and excess charges at each connection node of the capacitor array C0 to C1° are discharged.

Next, set S□~S6 to OFF state, SW6 to -v1 side, SW7
In addition to the series-connected capacitance series 01 to C, the reference voltage of full scale 2vn is set as the v□ side, and 2■□ is divided into 16 equal parts to generate a reference voltage for converting the upper 4 bits. When converting the lower 4 bits, when the held analog voltage vh is positive, SW1 is switched to the V, . . . /8 side and SW6 is switched to the ground voltage. On the other hand, when the holding analog voltage vh is negative, SWl is switched to the ground voltage and SW6 is switched to the -V n /8 side - as a result, the V
A voltage of n/JS or -vR/8 is applied, and C4 to C
The reference voltage for the lower 4 bits divided into 16 by 1o is ↑! ) can be done. Other circuit operations are the same as in the case of FIG.

〔Effect of the invention〕

As explained above, according to the present invention, N=2n(n>
1) In the case of bits, one n-bit A/l) converter is used twice per conversion, which has the advantage of being able to use less electricity and be smaller at the same conversion speed as the conventional series/parallel type. Furthermore, if columns and switches are used in the binary weight capacity, the functions of a sample bold circuit, a D/A converter, and a subtracter can be realized using these, which has the advantage of simplifying the circuit and making it suitable for high precision.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional serial-parallel A/D converter, Fig. 2 is a block diagram of the principle configuration of the method of the present invention, and Figs. 3 and 4 are block diagrams showing an embodiment of the present invention. be. 20... Input terminal, 21... Sample hold circuit, 22... n-bit A/D converter, 23... n-bit D/A converter, 24... analog subtracter, 25.
...Switch, 26...Reference voltage generation circuit, 27.
··register. Makoto Suzuki Figure 1 Figure 2 Figure 3-V.

Claims (2)

[Claims] (1) In an analog-to-digital conversion method that divides an analog signal into upper n bits and lower n bits and converts it into a digital signal, the input analog signal is sampled and held, and the sampled and held input analog signal is used as a reference for the upper n bits. The voltage is applied to an n-bit analog-to-digital converter (hereinafter referred to as an A/D converter) to output a high-order n-bit digital signal, and the digital signal is converted to an analog signal to convert the sampled and held input analog signal. The difference signal and the reference voltage for the lower n bits are given again to the A/D converter to convert the lower n bits.
An analog-to-digital conversion method characterized by outputting a bit digital signal. (2) Perform binary weighting on the function of sampling and holding the input analog signal, the function of converting the digital signal into an analog signal, and the function of taking the difference between the analog signal and the sampled and held input analog signal. Da11
3. The analog-to-digital conversion method according to claim 1, wherein the analog-to-digital conversion method is realized by the ↑3V characteristic using the capacitors and switches.