JPH04162828A - Pcm encoder - Google Patents

Abstract

PURPOSE:To reduce the circuit scale and to quicken the conversion speed by providing a logarithmic A/D converter outputting a high-order bit, an antilogarithmic D/A converter receiving its output and converting it into an analog signal, and a linear A/D converter applying density conversion to a difference output of a gain adjustment circuit and outputting a low-order bit of a PCM code to the PCM coder. CONSTITUTION:In the case of implementing nonlinear quantization of a logarithmic compression characteristic, the dynamic range of an input signal is divided into a rough range and an accurate range, the one, that is, the rough range is converted to decide a high-order bit by using a parallel A/D converter 5 having a logarithmic compression characteristic. The other range, that is, the accurate range is converted to decide a low-order bit by using a D/A converter 6 having an antilogarithmic expansion characteristic, which restores the digital signal into an analog signal, in which a gain adjustment circuit 4 takes a difference, and using an accurate range parallel A/D converter 8 after proper amplitude correction. Thus, the function of linear PCM conversion processing is integrated into each of the parallel A/D converters 5, 8. Thus, the circuit scale is reduced and the conversion speed is quickened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PCM encoder, which is particularly suitable for integrated circuits.
Regarding CM encoder.

[Conventional technology]

Conventional PCM encoders suitable for integrated circuits use serial-parallel AD conversion circuits to generate PCM codes.

FIG. 8 is a block diagram of a PCM encoder showing an example of such a conventional encoder.

As shown in FIG. 8, the PCM encoder IA includes a sample and hold circuit (S/H) 3 connected to an input terminal 2,
A gain adjustment circuit 4 that uses the output of H3 as one input, a parallel flash A/D converter (logarithmic A/D converter) 5A that converts analog input into a digital signal, and a logarithmic A/D converter.
an antilogarithmic D/A converter 6A that converts the output of the converter 5A into an analog signal and supplies the output to the other input of the gain adjustment circuit 4; and a linear A converter that converts the output of the gain adjustment circuit 4 into a digital signal. /D converter 8, upper bit register 7 and lower bit register 9, linear PCM conversion circuit 31 that linearly converts the outputs of these upper bit register 7 and lower bit register 9, and is connected to output terminal 11 and performs linear PCM conversion. The conversion output register 10 holds the output of the circuit 31.

First, the rough conversion of the input signal is assigned to the upper code, and this is executed at high speed by the parallel flash type logarithmic A/D converter 5A. At the same time, the antilogarithm D as a local D/A converter
/A converter 6A converts the upper code into an analog signal,
A signal obtained by taking the difference between the input signal value and the input signal value stored in the sample and hold circuit (S/H) 3 is amplified, and then converted into a lower code by a parallel flash type linear A/D converter 8. These higher-order codes and lower-order codes are converted into codes by the linear PCM converter 31, and the PC
M code is obtained.

Figure 9 shows μmLaw during conventional 4-bit A/D conversion.
FIG. 3 is a conversion characteristic diagram based on the law.

As shown in Figure 9, this characteristic varies with the analog input voltage and μ
This represents the relationship between the upper 4 bits of the mLaw law PCW code. Full scale voltage is +Vref to -Vref
It is between. The static and negative voltages were increased by 8, respectively, so that the voltage range doubled for each segment increase.
Each segment is divided into 16 equal parts by the 4 lower bits.

[Problem to be solved by the invention]

The PCM encoder using the conventional serial-parallel type A/D converter described above needs to perform linear PCM conversion processing after the A/D conversion is completed in order to obtain a PCM code output. Therefore, this digital processing increases the circuit scale and limits the conversion speed.

An object of the present invention is to provide a PCM encoder that can reduce the circuit scale and increase the conversion speed.

[Issues, means for solving problems]

The PCM encoder of the present invention includes a logarithmic A/D converter that outputs the upper bits obtained by coarsely converting an analog input and the upper bits of the PCM code, and a logarithmic A/D converter that outputs the upper bits of the logarithmic A/D converter. The inverse logarithm D to be converted into an analog signal
/A converter, a gain adjustment circuit that takes a difference between a signal obtained by sampling and holding the analog input and the output of the antilogarithm D/A converter, and a gain adjustment circuit that performs fine conversion on the differential output of the gain adjustment circuit to generate the PCM code. a linear A/D converter that outputs the lower bits of the logarithmic A/D converter, and an upper bit register and lower bits that respectively store the upper bits obtained from the logarithmic A/D converter and the lower bits obtained from the linear A/D converter. It is configured to include a bit register and a conversion output register that combines the respective outputs of the upper bit register and the lower bit register to generate a converted output.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a PCM encoder showing one embodiment of the present invention.

As shown in FIG. 1, the PCM encoder 1 of this embodiment includes a sample and hold circuit (S/H) 3 connected to an analog signal input terminal 2, and a logarithmic A/D converting the input signal into the upper 4 bits. a converter 5; an antilogarithmic D/A converter 6 that converts the conversion output of the logarithmic A/D converter 5 into an analog signal;
A gain adjustment circuit 4 that takes and amplifies the difference between the output of the S/H 3 and the output of the antilogarithm D/A converter 6, and a linear A that converts the output of the gain adjustment circuit 4 into a linear 4-bit PCM code.
/D converter 8, an upper bit register 7 and a lower bit register 9 that latch the upper and lower conversion results, respectively, and a conversion output register that is connected to the digital signal output terminal 11 and latches the PCM code of each register 7.9. 10.

FIG. 2 is a timing diagram for explaining the system clock of the circuit in FIG. 1 and the operation of each part.

As shown in FIG. 2, the system timing of the circuit shown in FIG. 1 operates in four phases φ1 to φ4.

First, when φ,=H, the S/H 3 goes into sampling mode and the logarithmic A/D converter 5 starts conversion.

Next, when φ2=H, the S/H3 enters the hold mode, and at the same time the converted digital data is output from the logarithmic A/D converter 5, the antilogarithmic D/A converter 6
/A Start conversion. At this time, the linear A/D converter 8 that receives the output of the gain adjustment circuit 4 starts conversion. Furthermore, the upper pit which is the output of the logarithmic A/D converter 5 is latched into the upper bit register.

Next, when φ,=H, the converted digital data is output from the linear A/D converter 8, and the converted lower-order code is latched into the lower-order bit register 9.

Next, when 'f'4=H, the upper code of the upper bit register 7 and the lower code of the lower bit register 9 are output together to the conversion output register 10 as the A2 conversion result. l Also, at this time, the antilogarithm D/A converter 6 is reset.

Incidentally, as shown in the system timing, each circuit block has an idle period when it is not used, so it is also possible to perform multiple operations using this period.

FIG. 3 is a circuit diagram showing an example of a logarithmic A/D converter in the first section.

As shown in FIG. 3, this logarithmic A/D converter 5 generates segment end point voltages for dividing the full scale voltage into 16 segments.

This segment end point voltage is created by dividing the voltage of the resistor string 12.13 made up of R to 128R so that the voltage range doubles each time the segment increases, as shown in the PCM conversion characteristics of FIG. 9 described above. and approximates the logarithmic transformation characteristics. These 16 segment end point voltages and the input signal voltage value are compared at the same time by the comparator 14 in the subsequent stage and decoded. In this process, the positive or negative of the signal is determined, and the upper 3 bits output 18 and the code signal (OVRI )
17 and a comparator 14 which is further combined by a multiplexer (MPX) 15 and selected by the code signal 17.
The 8-bit output (Do to D7) 16 can be seen. The output 16 of the MPX 15 and the code signal (OVRI) 17 are sent to the antilogarithm D/A converter 6, and the upper 3 bits output 18 and the code signal (OVRI) 17 are sent to the upper bit register 7.

FIG. 4 is a circuit diagram showing an example of the antilogarithmic D/A converter in FIG. 1.

As shown in FIG.
A capacitive array D/A converter 19 consisting of a switch controlled by the 8-bit 16 of the converter 5, and a code signal (OVR
I) a switch 20,21 controlled by 17. In short, this anti-logarithm D/A converter 6 converts logarithmically compressed upper bits into linear analog signal voltage values.
/A conversion and subtraction from the input voltage sampled and held in the sample and hold circuit (S/H) 3.

In the circuit operation of the antilogarithmic D/A converter 6, all the capacitors forming the capacitor array D/A converter 19 are first discharged in the reset mode when the system clock φ4=H. Next, when φ=H, the signal voltage is charged to the hold capacitor 256C of S/H3. When φ2=H, the comparator 14 of the logarithmic A/D converter 5 becomes a latch output, the sign is selected by the multiplexer MPX15, and 8-bit unsigned data is output as the input code of the antilogarithmic D/A converter 6. .

Further, by turning on the analog switch of the capacitor array D/A converter 19 described above when the inverted output of the data codes Do to D7=H, the input code can be returned to an analog voltage value obtained by anti-logarithm conversion. Here, when the sign signal 0VR1=H, that is, if the input signal has a positive sign, -VREP/2 is selected by the switch 20, and a negative sign signal voltage is reproduced. On the contrary, 0VR
When 1=L, that is, if the input signal has a negative sign, +V FLEF / 2 is selected by the switch 21, and a positive sign signal voltage is reproduced. These reproduced signal values are subjected to a charge difference from the value of the capacitor 256C at the summing node 22 of the operational amplifier 23 of the gain adjustment circuit 4, and are simultaneously inverted and held in the capacitor 256C of the gain adjustment circuit 4.

FIG. 5 is a diagram of the gain adjustment circuit shown in FIG. 1.

As shown in FIG. 5, this gain adjustment circuit 4 has an antilogarithm D/
The range of the segment end point voltage reproduced by the capacitive array D/A converter 19 of the A converter 6 is set to the operational amplifier 23 and 2C to 1.
This is a circuit for amplifying the voltage up to the full scale VR1F voltage range with a capacity of 28C and matching it with the input of the linear A/D converter 8 in the next stage. The structure is such that the gain is varied according to the magnitude of the segment end point voltage.

FIG. 6 is a circuit diagram showing an example of the linear A/D converter in FIG. 1.

As shown in FIG. 6, the linear A/D converter 8 includes resistor strings 24, 25, a comparator 26, and
This circuit includes an OR circuit and inputs the output of the gain adjustment circuit 4 and converts it into a linear 4-bit lower code. In other words, the lower 3 bits are sent to the lower bit register 9.
A bit output 28 and a code signal (OVR2) 27 are sent out. This is equivalent to a conventional parallel A/D converter.

FIG. 7 is a circuit diagram showing another example of a logarithmic A/D converter similar to that in FIG. 3.

As shown in FIG. 7, this logarithmic A/D converter 5 has R -2R ladder resistance string 29.30 is used to create a circuit that uses the current ratio as the load, and the comparator 14 and MPX
15 can be used to obtain equivalent outputs 16-18. According to the configuration shown in FIG. 3, the ratio of the load resistances is required in a geometric progression of 2, which significantly increases the circuit area.

Therefore, to compensate for this, R-2R ladder resistance string 29.3
By using 0, the resistance area can be reduced to about 1/4.

In short, according to the present embodiment described above, the upper bits of the PCM code are output using the input signal using a logarithmic A/D converter, while the lower bits are the voltage obtained by anti-logarithmically D/A converting the upper bits, By taking the difference between the input signal and the sample-and-hold value, amplifying it, and converting it with a linear A/D converter, the digital conversion process of linear PCM is not necessary, and the processing speed and size can be increased.

〔Effect of the invention〕

As explained above, when performing nonlinear quantization of logarithmic compression characteristics, the PCM encoder of the present invention divides the dynamic range of the input signal into two, coarse and fine, and transforms the coarse range into logarithmic compression characteristics. The upper bits are determined using a parallel A/D converter with On the other hand, the conversion code is returned to an analog value by a D/A converter with anti-logarithmic expansion characteristics, the difference with the input value is taken, and this is sent to a fine range parallel A/D converter after appropriate amplitude correction. A range of parallel A/D converters are used to determine the lower bits.

With this configuration, the function of linear PCM conversion processing can be incorporated into each parallel A/D converter, which has the effect of reducing the circuit scale, realizing an integrated circuit, and increasing the speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a PCM encoder showing an embodiment of the present invention, FIG. 2 is a timing diagram for explaining the system clock and operation of each part of the circuit in FIG. 1, and FIG.
The figure is a circuit diagram showing an example of the logarithmic A/D converter in Fig. 1, Fig. 4 is a circuit diagram showing an example of the antilogarithmic D/A converter in Fig. 1, and Fig. 5 is the circuit diagram shown in Fig. 1. Gain adjustment circuit diagram,
FIG. 6 is a circuit diagram showing an example of the linear A/D converter in FIG. 1, FIG. 7 is a circuit diagram showing another example of the logarithmic A/D converter similar to FIG. 3, and FIG. PCM showing a conventional example
FIG. 9, a block diagram of the encoder, is a conversion characteristic diagram based on the .mu.-Law law during conventional 4-bit A/D conversion. 1...PCM encoder, 2...analog input terminal, 3...sample/hold circuit (S
/H), 4...gain adjustment circuit, 5...
Logarithmic A/D converter, 6... Anti-logarithmic D/A converter, 7... Upper bit register, 8...
Linear A/D converter, 9...lower bit register, 10...conversion output register, 11...
...Digital output terminal, 12.13...Resistor string, 14.26...Comparator, 1
5...Multiplexer (MPX>, 16...
...8 bit output (DO~D7), 17.27...
...Sign output (OVRI, 0VR2), 18...Song...
Upper 3 bits output, 19...Capacitor array D/A
Conversion section, 20.21...Switch, 22. Old.
- Summing node, 23... operational amplifier, 24
．． 25・Old...Resistance string, 28...Lower 3 bits output, 29°30...Resistance ladder. Agent Patent Attorney Uchihara
Figure 1 for sound Figure 2 Figure 10 VRI: c Figure 5 Figure 9

Claims (1)

[Claims] 1. A logarithmic A/D converter that outputs the upper bits obtained by coarsely converting the analog input and the upper bits of the PCM code, and the upper bit output of the logarithmic A/D converter is input. an antilogarithmic D/A converter that converts the analog input into an analog signal; a gain adjustment circuit that takes a difference between a signal obtained by sampling and holding the analog input and an output of the antilogarithmic D/A converter;
A linear A/D converter that finely converts the differential output of the gain adjustment circuit and outputs the lower bits of the PCM code, and the upper bits obtained from the logarithmic A/D converter and the linear A/D converter. It is characterized by having an upper bit register and a lower bit register that respectively store the lower bits obtained from the above, and a conversion output register that combines the outputs of the upper bit register and the lower bit register to obtain a converted output. PCM encoder. 2. The logarithmic A/D converter includes a loaded resistor string or R-2R type resistor ladder that divides the reference voltage, and a comparator that compares the reference voltage divided by the plurality of resistors and the analog input voltage. and the inverse logarithm D, which switches the comparator output according to the signal polarity.
2. The PCM encoder according to claim 1, further comprising a multiplexing circuit for controlling the /A converter and means for creating the upper bits. 3. The anti-logarithmic D/A converter is a capacitive array D/A that is composed of a plurality of switches and a plurality of capacitive elements, and the plurality of switches are controlled by the output of the multiplexing circuit of the logarithmic A/D converter. The PCM encoder according to claim 1, further comprising a converter.