JPS62175018A - Ad converter - Google Patents

Abstract

PURPOSE:To execute successively the high resolution of a comparing type AD converter by providing with a comparator group to compare plural reference voltage levels and the signal from a computing element, an encoder to code the output and a digital multiplexer to add the output to a successive comparing logic. CONSTITUTION:For the constitution of a parallel type AD converting part, a reference value VR is applied to a resistance array to connect serially resistances R1-Rn, the reference value of respective levels divided by the resistance array is introduced to comparator groups C1-Cn, the output is introduced to an encoder 1, coded, and comes to be a digital signal s2 corresponding to a higher order 4-bit of an analog input Vi of the converting object. A DA converter 17 converts the 12-bit signal introduced from a successive comparing logic 19 to the analog signal and adds to a computing element 16. The computing element 16 operates the analog input Vi of the converting object introduced through a circuit 15 and a signal Vj introduced from the DA converter 17, and as the result, Vk is applied to respective comparators C1-Cn. A digital multiplexer 22 selects the output of the comparator equivalent to the highest level where the output comes to be '1' and continues to latch the condition.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Object of the Invention [Field of Industrial Application] The present invention relates to improving the conversion speed and resolution of an AD converter.

(Prior Art) The following are known as analog-to-digital converters (hereinafter simply referred to as AD converters).

(1) Parallel AD converter An example of the configuration of this parallel AD converter is shown in FIG.

The circuit of FIG. 6 uses, for example, a constant voltage as the reference value,
By dividing this voltage by a plurality of resistors R, a plurality of reference voltages are generated. Then, each voltage divided by the resistance is applied to the comparators C1, C2, . . . , respectively. Each comparator for each level of this! Compare the magnitude of the 3tF-voltage and the analog input voltage to be converted. Since different comparators operate depending on the magnitude of the analog input voltage, AD conversion can be performed by converting the output of each comparator into a digital signal by the decoder D.

(11) Successive approximation type AD converter An example of the configuration of this successive approximation type AD converter is shown in FIG. The circuit shown in FIG. 7 generates a digital signal using successive approximation logic, converts this into an analog signal using a DA converter, and compares the analog input to be converted with the signal from the DA converter using a comparator.

When the two signals match, the digital signal (a) output from the successive approximation logic can be said to be the same as the analog human horn, so the value at this time is used as the conversion output.

(Problem to be solved by the invention) However, the above-mentioned means have the following problems.

In the method (1), the number of comparators required is 2”-
1 (n is resolution), and it is difficult to achieve high resolution, and currently only 8 pi 1~Pi! degree.

The means (11) requires changing the output of the DA converter as appropriate and repeating the operation of comparing it with the input signal 0 times (n is resolution). Therefore, as the resolution increases, the conversion of 31 degrees decreases. Furthermore, since the conversion speed of a high-resolution DA converter is slow, increasing the resolution of a successive approximation type AD converter has the problem of significantly reducing the speed.

An object of the present invention is to provide a means for realizing high resolution of a successive approximation type AD converter without causing a significant speed reduction unlike the conventional method.

``Structure of the Invention'' [Means for Solving the Problems] In order to solve the above problems, the present invention uses a successive approximation logic (19) and the output of this successive approximation [1sik (19)]. In a successive approximation type AD converter that includes a DA converter (17) that converts into an analog signal, and an arithmetic unit that calculates the output of the DA converter (17) and the analog input Vi to be converted, a plurality of A group of comparators that compare the reference voltage level with the signal from the arithmetic unit, an encoder that encodes the output of this group of comparators, and an output of this comparator that selects one of the highest operating levels from the group of comparators. using successive approximation logic (1
9).

(Example) First, the outline of the present invention will be explained in detail.
Unit A is a combination of the comparator part of the successive approximation type AD converter shown in Fig. 7, and the comparator group of the parallel type AD converter.
This configuration is replaced with a multiplexer for selecting one output from the group of comparators. And top! A parallel type AD converter unit performs high-speed AD conversion of the bit I, while the lower m bits are converted into a successive approximation type ADtf.
Let it be converted in part i, and as a whole, FL = l
+m-bit decomposition (: Pi AD converter to Il-bit successive approximation type Δ1) This is achieved without a significant speed reduction compared to the conversion speed of only a converter.

Hereinafter, the present invention will be explained in more detail using the drawings.

FIG. 1 is a diagram showing an embodiment of an AD'IJ and a converter according to the present invention. In FIG. 1, an example of a configuration having a resolution of 10 bits will be used for explanation. In the figure, a portion 10 surrounded by a dotted line corresponds to a parallel AD converter. The parts other than this dotted line part 10 are successive approximation type △D'aI! It constitutes the i11 section. (8 or resistor R1 of the parallel ΔD converter 10
A reference value VR is added to a resistor array in which ~Rπ is connected in series. Then, the reference values of each level divided by this resistor array are introduced into the comparator group CT-CTL. The output of each comparator CI to Cm is introduced into the encoder 1, where it is converted into 2: analog human power to be converted,
The digital signal s2 corresponds to the upper 4 bits of . Furthermore, if the resolution of the converter is 16 bits, n
=16, and the accuracy of the resistor array (R+ to RTL) and comparator C+=Cu requires a resolution of 16 bits.

Reference numeral 17 denotes a 12-bit DA converter, which converts the 12-bit signal introduced from the successive approximation unit 19 into an analog signal and applies it to the arithmetic unit 16. This computing unit 1G computes the analog human power V to be converted introduced via the sample and hold circuit 15 and the signal ■ introduced from the DA converter 17, and calculates the result Vk to each of the comparators C+
-Add to CTL. In FIG. 1, the performance of the arithmetic unit 1e]! :
Then, Vk=Vt V; (1) Calculation is being performed. The above-mentioned DA converter 17 and successive approximation logic 1 are the same as those used in the conventional successive approximation type Al) converter shown in FIG.

Reference numeral 20 denotes a control logic, which receives a start signal and controls the encoder 1, sample hold circuit 15, and digital multiplexer 22.

The digital multi-level shifter 22 is a groove that can select the output of the comparator corresponding to the highest level of output 1'' and continue to latch that state. A specific example of this configuration is shown in FIG.

First, an outline of the operation of the AD converter shown in FIG. 1 configured as described above will be explained.

In step 1, the output of the DA converter 17 is set to O, and the parallel AD converter 10 converts the upper 4 bits of the analog human power Vt into a digital signal 194.

In step 2, among the comparators C7 to CTL whose output is "1", the comparator corresponding to the highest level (upper bit) is used to AD convert the lower 12 bits by a successive approximation method.

The operation will be explained in detail below. control logic 2
0 to △D conversion start signal (start signal...Figure 3 (:
) is input, the sample and hold circuit 15 operates as shown in FIG. .

On the other hand, in response to the start signal, the control logic 20 sends a signal to the successive approximation logic 19, and in response, the successive approximation logic 19 changes the 12-bit output to "0".
．． ..., 0°'. Therefore, Fig. 3 (Vl+ >
As shown, the output of the DA converter 17 becomes O.

the result,? A-bu 516ha Vi = (Vt O)
, that is, Vk-Vt is output to the comparator Ct-Cn. Then, the signal Vk -Vt from the arithmetic unit 16 is converted into an AD converter by the comparator C+=Cu and the resistor array (R+~RTL), and the upper 4 bits of the analog human input V are converted into AD by the same operation as explained in FIG. be done. Analog human power V
The relationship between i and the output of encoder 1 (upper 4 bits) is
The result is as shown in FIG. To explain this specifically,
Analog input V, is (0,0000v ~ 15.000
0 V), the upper digits 1, 2 .・
..., the encoder 1 outputs a digital value corresponding to 15v. And the voltage below the decimal point (part A in Figure 4)
The digital value corresponding to
Output by the converter.

In the digital multiplexer 22, for example, with the configuration shown in FIG. 2, the comparator Cχ corresponding to the eleventh highest level (higher bit) whose output is "1" is selected by Ex-OR gates EG+ to EGTL. For example, if the comparator CI + C2 is 0°' and C3, .
..., if Cu is '1'', the output of C3 can be selected.The output of comparator C3 is connected to the successive approximation logic 19 via the multiplexer 22.Then, this selection is flipped. Latch at 70 knobs F1 to Fm.This digital multiplexer ° latch pulse (
FIG. 3 (see liD) is output from control logic 20. Further, the encoder latch pulse shown in FIG. 3(N) is outputted from the control logic 20 to the encoder 1, and the upper 4 bits of the analog human input V+ are latched. In addition, during the period so far, the DA converter 17
The output of remains O.

Next, the successive approximation type AD converter is operated. in this case,
Assuming that the comparator C3 described above is selected by the digital multiplexer 22, the configuration 4 will be as shown in FIG. In this state, the successive approximation logic 19 outputs a signal in the order of the most significant bits among the 12 bits, performs DΔ conversion on this signal, and then observes whether the output of the comparator C3 becomes 1'' or 0''. and LS one after another
Determine each bit up to B.

To put this concretely, let's say that the analog input is V (-5
, 430v. It is assumed that the parallel AD converter 10 converts the upper digit 5■ of this analog input into a digital value. Therefore, the comparator C3 in FIG.
If 0v<vk, output II I II and V
It operates so that k< 5.000v.

In this state, the successive approximation logic 19 sequentially determines the value of the 12 bits starting from the most significant digit.

A value of "100...0" is output to the OA converter 17. In response to this, the D△ converter 17 converts and outputs, for example, 0,500V when the most significant digit of the 12 bits is "1".Therefore, the output Vk of the arithmetic unit 1G is Vk.
= 5.430 - 0.500 = 4.930v, so the output of comparator C3 becomes 0'', so the successive approximation logic 17 calculates that the most significant digit of 12 bits is ``O1''.
1 and learn that it must be 41().

Next, set the second digit to 1″. Hit, 010...O
'' is output to the DΔ converter 17.

In response to this, the DΔ converter 11 outputs 0.250v this time. Therefore, the output Vk of the g calculator 16 is -5,43
Since 0-0,250=5.180v, the output of comparator C3 is 1''. Therefore, the successive approximation logic 11 knows that the second digit is '1''.

Next, write the third digit as “1°”. In other words, “0110”
...outputs the value 0'' to the DA converter 17. In response, the D△゛ converter 17 outputs the value (0,250+0.125
) Output v. Thereafter, by the same operation as described above, L
Know the value up to SB.

As a result, Vk=5.000v, V==0.43
0vT'' system is stable.The output S3 of the successive approximation logic 11 is precisely the lower digit of the analog input Vt converted into digital data with 12 bits.

When the successive approximation operation is completed, a conversion completion signal <EOC) is output from one successive approximation logic.

In addition, in the following, AD conversion with a resolution of 16 bits is
Although lζ is divided into the upper 4 bits and the lower 12 bits, the upper and lower bits are not limited to this. For example, the upper 6 bits and the lower 10 bits may be used.

Further, the resolution is not limited to 16 bits, but may be, for example, 14 bits.

C. Effects of the present invention j As described above, according to the present invention, it is possible to convert an analog input into a digital signal using a high-resolution OL without significantly reducing the conversion speed.

[Brief explanation of drawings]

1 is a diagram showing an example of the configuration of an AD converter according to the present invention, FIG. 2 is a diagram showing an example of the configuration of a digital multiplexer, and FIG. 3 is a diagram showing an example of the configuration of a digital multiplexer.
The figure is a time chart, Figure 4 is a diagram showing the relationship between analog input and encoder output, Figure 5 is a diagram showing an example of the circuit state when the digital multiplexer is in operation, and Figures 6 and 7 are conventional It is a figure showing an example. 1...Encoder, R1-RTL...Resistance, C1~
CR... Comparator, 10... Parallel type ΔD converter, 15... V pull hold circuit, 1G... Arithmetic unit, 17... DA converter, 19... Successive approximation logic, 20 ...Control 1-Roll logic, 22...Digital multiplex. Figure 1, Figure 2, go to Figure 4, Digital output =: Analog input Vi, Figure S; ・: Figure 6, Figure 7, Figure 70

Claims (1)

[Claims] Successive approximation logic (19) and this successive approximation logic (
DA converter (19) that converts the output of
7) and an arithmetic unit that calculates the output of the DA converter (17) and the analog input V_i to be converted. A group of comparators that compare signals, an encoder that encodes the output of this group of comparators, and one of the highest operating levels from the group of comparators is selected, and the output of this comparator is processed by successive approximation logic (1
9).