JPS59196619A - Analog-digital converting circuit - Google Patents

Abstract

PURPOSE:To accelerate the A/D converting speed by comparing sequentially plural constant currents with bit weighting and an input analog signal and deciding every two most significant bits at the same time in A/D conversion. CONSTITUTION:An SAR (sequential comparison register) 44 controls current switches 46 and 47 so that the switch 46 is thrown to all of the A positions, i.e., 000000 and the switch 47 is thrown to all of the B positions, i.e., 111111 as the initial state when a full scale voltage is 10V and 5.7V is applied as the analog input. An output V7 of a current/voltage (I/V) converting circuit 49 is 0V and an output V6 of an I/V converting circuit 48 is 10V. Divided voltages V2-V4 of a resistor ladder are respectively 10V, 7.5V, 5V, 2.5V and 0V. When comparators 42-1-42-3 compare the voltages of V2-V4 with an analog input voltage, the comparator 42-1 outputs an L level and the comparator 42-3 outputs an H level and the result is fed to a decoder 43. The decoder 43 outputs 10 in this case (1st step). After the high-order 2-bit is decided as 10, the high-order bit of current switches 46, 48 is brought into 10, the comparator 42 compares the divided voltage of the resistor ladder again, and its output is fed to the decoder.

Description

[Detailed description of the invention] TECHNICAL FIELD The present invention relates to an analog-to-digital conversion circuit.

Conventionally, various analog-to-digital conversion methods (hereinafter abbreviated as A/D conversion) have been devised, such as a fully parallel comparison type, a successive approximation type, and an integral type.

Among them, the successive approximation type and fully parallel comparison type A/D conversion systems that are directly related to the present invention will be described below.

First, the successive approximation type conversion method will be explained.

The successive approximation conversion method uses successive approximation registers as shown in Figure 1.
Re5istor, hereinafter abbreviated as 8AR. ) 11, I
)/A converter 13 and a comparator 14. The following is an example of a 3-bit successive approximation type A/D converter. I will explain in detail. It is assumed that the full-scale rolling rolling is 10V and an analog input voltage of 1.7V is applied. The initial state of 5ARII is D/A
The converter 13 is set to output the MS BicHigh, 2nd O, and LSBKL (W signals. (It will be expressed in base numbers.) At this time, the D/A converter 13 outputs an analog output of 5V corresponding to the input of 100. On the other hand, since the analog input is 7V, the output of the comparator 14 is Hi
It becomes gh. (In the following, High (l″1.H,L
ow is abbreviated as L. ) When the H signal of the comparator 14 is input to the SAR 11, the 5AR 11 sets the 2nd to 1 while leaving the MSB at 1. That is, it is output to the next input code 110' of the D/A converter 13. Then, the D/A converter 13 outputs an analog output corresponding to 110, 5Vt-,
The comparator 14 compares the analog human cuff v with the output cuff of the D/A converter 13, 5V', and outputs the L signal=iSAH. When the L signal of the comparator 14 is input to 5AR11, 5ARII sets the 2nd to 0 and becomes LSB il and f.

That is, the next input code 101'? to the D/A converter 13? When outputting , the D/A converter 13 outputs an analog output of 6.25 Vt corresponding to 101, and the comparator 13 performs a complete comparison between the analog human cuff and the output of the p/A converter of 6.25 V. Outputs an H signal to the SAR.

5ARII outputs a signal tone of 101 to the output buffer 12, and at the same time outputs all control signals for turning on the output buffer 12t. In this way, a digital code 101 corresponding to the analog input cuff V is obtained. As can be seen from the above, the 3-bit successive approximation A/D converter requires three D/A conversions and voltage comparisons. In addition, in an n-bit successive approximation type A/D converter, n times of 1)/A conversion and voltage comparison are required, resulting in %5. A disadvantage is that the conversion time becomes slow in proportion to the resolution of A/D conversion.

Next, a fully parallel comparison type A/D converter will be explained. n
As shown in FIG. 2, the bit all-parallel comparison type A/D converter has a resistor ladder circuit 21.2 composed of 2n resistors.
It is composed of n-1 comparators 22 and decoders 23. The fully parallel comparison type A/D conversion method will be described below by taking a 3-bit fully parallel comparison type A/D converter as an example. It is assumed that the full-scale voltage is IOV (64) and that an analog input voltage of 7V is applied. 3-bit fully parallel comparison type A
/D converter shown in Figure 3. The voltage obtained by dividing the full scale voltage 10V by the resistor ladder 21 is also shown in FIG. By comparing the analog input cuff ■ and the voltage divided by the resistance ladder, the outputs of comparators 22-1 and 22-2 are H1.
Comparator 22-3.22-4゜22-5.22-6.22
-7 output becomes L. The output of this comparator is converted into a binary code by the decoder 23, and an output code of 101 is obtained. The all-parallel comparison type has the advantage that high-speed conversion can be performed regardless of the number of bits in the A/D converter because all bits are determined by one voltage comparison. However, in order to realize a high-resolution A/D converter, a large number of resistors and comparative costs are required. For example, a 10-bit fully parallel comparison input/D converter requires 1024 resistors and 1023 comparators, and has the disadvantage that it is difficult to achieve a high resolution of 10 bits or more. .

As mentioned above, in the conventional technology, successive approximation type A
The A/D converter has the disadvantage of slow conversion speed, and the all-parallel comparison type A/D converter has the disadvantage that it is difficult to achieve high resolution.

In view of the shortcomings of the conventional technology, the A/D conversion circuit according to the present invention can realize a conversion speed several times higher than that of the successive approximation type while achieving high resolution and precision equivalent to that of a successive approximation gA/D converter. It uses a high-speed, high-precision A/D conversion circuit.

Below, the A/D conversion circuit according to the present invention will be explained in detail using all drawings.

A block diagram of an A/D conversion circuit according to the present invention is shown in FIG.

This A/D conversion circuit is constructed as follows.

Bit weighting is performed by a constant current circuit 45 (for example, a constant current circuit configured by an R-2R ladder resistor network and a reference power supply) consisting of a constant current register group, and the constant current circuit F) D/
The converter is configured as follows. The current switch groups 45 and 47 of this D/A converter are each controlled by 5AR44.

Further, the output current taken out from the B terminal of the current switch group 46 is subjected to positive conversion by the current/voltage conversion circuit 49. Similarly, the output current taken out from the B terminal of the current switch group 47 is converted into voltage by the current/voltage conversion circuit 48. Further, a voltage addition circuit 50 is connected to the outputs of the voltage conversion circuits 48 and 49. In addition, the voltage addition circuit 50
A resistance ladder circuit 41 is connected with the voltage conversion circuit 49 at both ends. One input terminal of a comparator 42 is connected to each voltage division point of the resistor 2/circuit 41.

The other input terminal of comparator 42 is all connected to analog input terminal VIN. The output of the comparator group 42 is connected to the 5AR 44 through the decoder 43t. In the circuit of the present invention, the upper bits can be determined simultaneously in units of multiple bits.

Next, the operation sequence of the A/D converter circuit according to the present invention will be explained from the perspective of determining the upper two bits of a 6-bit A/D converter. FIG. 5 shows a circuit diagram when the 6-bit A/D conversion circuit completely determines the upper 2 bits at a time. In addition, the operating table 1. The full scale voltage is 10V, and the analog input is 5.
Consider gold if 7v is applied. In the first step, the current switch 46 is set to ooooooo and the current switch 47 is set to 111111 as the initial state.
It is controlled by many people. (Here, the state of the switch is 0
means that side A is selected, and 1 means that side B is selected6)
A current switch 47 is connected to the input of the current/voltage conversion circuit 48.
In addition to the current from the weighted current source circuit 45, the ILS
It is connected so that a current corresponding to B is always supplied. Therefore, in the initial state, the output v7 of the voltage conversion circuit 49 is QV.
, the output (6) of the voltage conversion circuit 48 becomes IOV. Also, the divided voltages of the resistance ladder ■, ~v5 are tov, 7, 5v, respectively.
, 5V.

It becomes Z5V, OV. Comparisons 542-1 to 42-3 are ■2
A comparison is made between the voltage of ~v4 and the analog input voltage of 5.7v. As a result, comparator 42-1, comparator 42-2.
3 outputs Ht- and sends it to the decoder 43. (In the following, L
It is expressed as 011 as ThO and HThl. )
The decoder 43 is 10,111 when the comparators 42-1 to 42-3 are 000, 00,001 and 01,011.
In this case, the output of the comparator is converted to 2 bits so that it becomes 11. In this case, the outputs of the comparators 42-1 to 42-3 are 01
Since it is 1, the output of the decoder 43 is 10. The operation of the first step is thus completed, and the upper two bits are determined to be 10. Next, in the second step, the current switch 1 is set to 100000 with the upper two bits being 10, and the current switch 47 is set to 10111 with the upper two bits t-10.
It is set to 1.

At this time, the voltages of ■ and ~v5 are each 7. Le V, 6.87
5V.

6.25ve 5.625V, set as 5v. The state of the comparator is determined by comparison with the analog input 5.7V.
01, and the output of the decoder becomes 01. With the above steps, the $2 step is completed, and the upper 4 bits are determined to be 1001. Next, in the third step, the current switch 46
The bit is set to 1001 and 9100100. Further, the current switch 47 is set to 9.100111 with the upper 4 bits being 1001. At this time V, ~V
5 (D1jL pressure c each k 6.25V, 6.09375
V, 5.93750V, 5.78125V, 5.625
It is set as V. The states of the comparators 42-1 to 42-3 are 000 by comparison with the analog input 5.7V, and the output of the decoder 43 is OO tonal. As described above, the third step is completed and 6-bit A/D conversion is completed. - Analog input voltage 5.7v was converted to tooiooo. As mentioned above, 6-bit A/D conversion was completed in just 3 steps. In conventional successive approximation type A/D conversion,
Since 6 steps are required for 6-bit conversion, the conversion speed is twice that of the successive approximation type A/D.

In addition, in the circuit for the fifth factor, if the resistor ladder circuit is configured with 8 resistors and 7 comparators are prepared, the upper 3 bits can be determined at the same time, and the conversion speed is faster than the conventional one. This is three times the successive approximation type.

In order to simultaneously determine the upper m bits of A/D conversion for $K,n bits, the circuit shown in FIG. 4 requires an n-bit constant current source circuit 45 and current switches 46, 47 and 21.
Resistance ladder circuit composed of one resistor 41.2rn
This can be realized by a circuit including a decoder 43 which converts the output of -1 comparator 42.2m-1 comparators into im bits. The conversion speed in this case is m times that of an n-bit successive approximation type A/D conversion circuit. For example, 12 bit A
When /D conversion is performed on the upper 4 bits at a time, a 12-bit weighted current source circuit, two sets of 12-bit electric travel switches, and a resistance ladder circuit consisting of 16 resistors are used.
It can be realized with 15 comparators and decoders, and can obtain a conversion speed four times that of the 12-bit successive approximation type. or,
A 12-bit fully parallel comparison type A/D converter requires 4096 resistors and 4095 comparators, which is very difficult to implement.

As can be seen from the above, the A/D conversion circuit of the present invention has a high resolution that is difficult to achieve with an all-parallel comparison type A/D conversion circuit, and is better than a successive comparison type A/D conversion circuit. is also particularly useful when high conversion speeds are desired.

[Brief explanation of the drawing]

1 and 2 are diagrams showing conventional circuits. FIG. 1 is a successive approximation type A/D conversion circuit diagram, and FIG. 2 is a fully parallel comparison type A/D conversion circuit diagram. FIG. 3 shows a 3-bit fully parallel comparison type A/D conversion circuit as one of the conventional examples. FIG. 4 is a block diagram of an A/D conversion circuit according to the present invention, and FIG. be. 1: Resistance ladder circuit Figure 1 3

Claims (1)

[Claims] A conversion circuit that obtains a digital value by successively comparing multiple pit-weighted constant currents with an input analog signal is characterized by simultaneously determining the upper bits, two bits, or more bits at a time. Analog-to-digital conversion circuit.