JPS62181528A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To obtain an analog-digital converter with high speed and high resolution by deciding a high-order sequentially by a comparator and a digital-analog converter, shifting the level of an output component of the digital-analog converter after the decision of the high-order bit and inputting the result to another high speed analog- digital converter. CONSTITUTION:To the most significant bit D15 of a sequence register 9, '1' is set, a digital data of a 16-bit DA converter 8 is set to '1,000', and its analog converting voltage (d) is compared with an analog input signal (a) by a comparator 7. When the signal (a) is larger than the output signal (d) of the converter 8, the level of the bit D15 remains '1', and when the signal (a) is smaller, the bit D15 is set to '0'. A level '1' is set to a bit D14 of the register 9, '0100' is set to the digital data of the converter 8 (when the bit D15 is set to '0'), as the result of comparison, when the signal (a) is larger than the output signal (d) of the converter 8, the bit D14 remains '1', and when the signal (a) is smaller, the bit D14 is set to '0'. The output voltage of the level shifter 6 is made coincident with the input range 20 of a high speed AD converter 11 of the next stage and low-order bits D11-D0 shown in figure 2e are obtained by giving a high speed AD converter start pulse (e) from the control circuit 10.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an analog-to-digital (hereinafter abbreviated as rADJ) conversion device used for computer input and measuring instruments.
In particular, it relates to a high-speed and high-resolution AD converter.

[Conventional technology]

FIG. 3 is a block diagram showing the configuration of a conventional successive approximation type AD converter, in which 1 is a comparator to which analog input signal a is input, 2 is a digital-to-analog (hereinafter abbreviated as rDAJ) converter, and 3 is a Let Do be the LSB and D be the MSB (
n+1) A sequence register for outputting a digital output signal of the focus; 4 is a control circuit to which an AD conversion start signal is input; and 5 is a clock circuit. The control circuit 4 and the clock circuit 5 operate the sequence register 3.

Next, the operation of the apparatus configured as described above will be explained. When the AD conversion start signal is generated, the sequence register 3 is first reset, and then.

Only the bit becomes logic "1", and the analog voltage corresponding to this is output from the DA converter 2, and is compared with the analog input signal a in the comparator 1, and if the analog input signal a is larger. is determined to be "1", and if analog input signal a is smaller, Dn is determined to be "0".

Once D is determined in this way, the next step is to determine Dn-+, and as in the case of D7, the sequence register 3
After setting the bit of Dll-, to "1", comparator 1 compares it, and if analog input signal a is larger,
, are determined to be "1", and if the analog input signal is smaller, Dn-+ is determined to be rOJ. In this way D
The logic of each bit of n""D o is determined. This D
The output signal of the sequence register 3 after the logic of each bit of ゎ to D0 is determined is the AD conversion data b.

[Problem that the invention seeks to solve]

Conventional AD converters are configured as described above, so when trying to achieve high resolution, it is necessary to perform DA conversion and level comparison using a comparator a number of times according to the number of resolution bits required, which reduces the conversion time. It had the drawback of being long.

The present invention has been made in view of these points, and its purpose is to use a low-resolution but high-speed AD converter, utilize its high-speed characteristics as is, and create a high-resolution DA converter. The object of the present invention is to obtain an AD converter that can increase resolution in combination with the present invention.

[Means for solving problems]

In order to achieve such an object, the present invention provides a sequence register in which the upper bits are set sequentially and set or reset depending on the result, and the output signal is used as the upper bit of analog-to-digital conversion, and the output signal of this sequence register is A comparator that compares the input digital-to-analog converter, the analog voltage output from this digital-to-analog converter, and the analog input signal, and the sequence register is set and reset, and then the analog input signal is converted to digital-to-analog. The device is equipped with a level shifter that shifts the level by an amount corresponding to the analog voltage output from the device, and an analog-to-digital converter with a small number of bits that converts this level-sick output signal from analog to digital.

[Effect]

The level shifter in the present invention acts to take the difference between the input analog input signal and the output signal of a high-precision digital-to-analog converter with fixed upper bits, and also performs amplification to convert the input signal into a high-speed analog-to-digital converter at the next stage. converts the lower bits correctly from analog to digital.

〔Example〕

An embodiment of an AD conversion device according to the present invention is shown in FIG. In FIG. 1, 6 is a level shifter that level-shifts the analog input signal a according to the output voltage d of the 16-bit converter 8, 7 is a comparator, 9 is a sequence register, and 10
is a control circuit that controls the sequence register 9 and the high-speed AD converter 11.

The operation of the apparatus configured as described above will be explained using the waveform diagram of FIG. 2. The control circuit 10 is first constructed as shown in FIG.
As shown in a), the most significant bit I)+s of the sequence register 9 is set to "1", and the digital data of the 16-bit DA converter 8 is rloo.

'', and the analog conversion voltage d is the analog input signal a.
and is compared by the comparator 7. The comparison time at that time is the second
This is time T1 shown in the figure. And as a result of this comparison,
If the analog input signal a is larger than the output signal d of the 16-bit DA converter 8, Dll remains at "1", and if the analog input signal a is smaller, it is set to "0". Second
The figure shows an example of "0" (see Figure 2 (a))
.

Next, as shown in FIG. 2 (bl), the sequence register 9
Set the DI4 bit to ``1'' and transfer the digital data from the 16-bit DA converter 8 to rolooJ (Dll is ``1'').
Similarly, the analog converted voltage d is compared with the analog input signal a by the comparator 7.

As a result of this comparison, if the analog input signal a is larger than the output signal d of the 16-bit DA converter 8, then D
I4 is left as "1", and if analog input signal a is smaller, it is set to "0". Figure 2 shows an example where the value is "1" (see Figure 2).

Similarly, as shown in FIG. 2 (cl, fd), D, 3. The data of D and 2 are determined sequentially. As a result, the data of 5 to DI2 are determined, the upper 4 bits of the 16-bit DA converter 8 are output (the lower 12 bits are all "0"), and the analog input signal a is level-shifted by the level shifter 6. , its level shifter 6
The output voltage should have a smaller fluctuation range than the analog input signal a (see Figure 2 (gl). ) The output signal d of the DA converter 8 approaches the analog input signal a, and the difference is 1/24 of the full scale.
This is due to the following. The output voltage of this level shifter 6 is made to match the input range 20 of the next-stage high-speed AD converter 11 (see Figure 2), and the high-speed AD converter start pulse e from the control circuit 10 (see Figure 2 (f)
), the lower bits D, ~Do shown in FIG. 2 can be obtained. In this way,
AD conversion data f not shown in FIG. 1 can be obtained. In addition, the conversion time of the high-speed AD converter is time T2 shown in FIG.
, and the AD conversion time is time To.

In the above embodiment, the 12-bit high-speed AD converter 1
Although the 16-bit AD converter is constructed by combining the 1 and 16-bit DA converters 8, the operation can also be achieved with other bit numbers. Then, the level shifter 6 part is used for the next high speed A.
Although it has been explained that the input range is matched to the input range of the D converter 11, an amplifier may be inserted between the level shifter 6 and the high-speed AD converter 11.

〔Effect of the invention〕

As explained above, the present invention sequentially determines the upper bits using a comparator and a digital-to-analog converter, and inputs the output of the digital-to-analog converter after determining the upper bits to another high-speed analog-to-digital converter after a level chic. By configuring the digital-to-analog converter to
When a high-speed analog-to-digital converter is 6 bits and a high-speed analog-to-digital converter is 12 bits, a successive approximation type analog-to-digital converter using only a 16-bit digital-to-analog converter and a comparator usually requires an analog-to-digital conversion time of (comparison time) x 16. Compared to this, (comparison time) x 4 + α (α is 12
bit-high speed analog-to-digital conversion time),
This has the effect of providing a high-speed, high-resolution analog-to-digital converter.

[Brief explanation of drawings]

Fig. 1 is a block system diagram showing an embodiment of an analog-to-digital conversion device according to the present invention, Fig. 2 is a waveform diagram for explaining the operation of the device in Fig. 1, and Fig. 3 is a conventional analog-to-digital conversion device. FIG. 2 is a block system diagram showing the device. 6... Level shifter, 7... Comparator, 8...
- 16-bit DA converter, 9... sequence register, 10... control circuit, 11... high speed AD converter.

Claims (1)

[Claims] A sequence register that is set sequentially from the higher bits and is set or reset depending on the result, and the output signal is used as the upper bit of analog-to-digital conversion, a digital-to-analog converter to which the output signal of this sequence register is input, and this digital-to-analog conversion a comparator that compares the analog voltage output from the converter with the analog input signal; and after the sequence register is set and reset, the analog input signal is leveled by the analog voltage output from the digital-to-analog converter. An analog-to-digital conversion device comprising: a level shifter that shifts; and an analog-to-digital converter with a small number of bits that converts an output signal of the level shifter from analog to digital at high speed.