GB2115998A - Apparatus and method for rapid analog-to-digital conversion - Google Patents

Abstract

An analog-to-digital converter develops an N-bit digital word over a period of N cycles of a sampling clock signal. As the sampled analog signal is clocked through a tapped analog delay line (112) and is recovered at N separate output taps (T1, T2, T3, T4) at successive delay times later, successive comparisons (C1, C2, C4, C8) each produce one digital bit, beginning with the most significant bit, during each clock signal cycle. The digital bits developed progress through shift registers (SR2, SR4, SR8) having numbers of stages selected so that an N-bit parallel digital word is produced at the shift register outputs when all N bits have been determined. A new digital sample is produced for each clock cycle. <IMAGE>

Description

SPECIFICATION Apparatus and method for rapid analog-to-digital conversion This invention relates to analog-to-digital converters and in particular to analog-to-digital converters in which the bits of the digital word are sequentially developed.

The rate at which analog signals can be converted into corresponding digital words is limited by the speed at which comparisons of signals can be made. Analog-to-digital converters (ADC) are presently available in which high-rate conversions are obtained by "flash conversion". In a flash converter, one comparator is employed for each possible output state and an equal number of analog comparison voltages must be developed. Thus, an N-bit ADC requires 2N-1 comparators and 2N-1 comparison voltages. For example, an eight-bit flash converter requires 255 comparators each of which compares the analog signal to a portion m/256 of the reference voltage (where m is an integer between 1 and 255, inclusive). Combinational digital logic circuits develop the resultant eight-bit digital word from the digital output levels of the 255 comparators.

Flash converters develop a new digital sample for each cycle of a sampling clock. Because they require so many comparators and comparison voltages, flash converters tend to require very large areas on an integrated circuit. This tends to make the integrated circuit more expensive and more difficult to produce.

Such flash ADC's can also require substantial amounts of electrical power to operate.

On the other hand, successive approximation ADCs require only one comparator and determine the digital word one bit at a time. As the bits are determined, they are applied to a digital-to-analog converter (DAC) in a feedback connection to develop the comparison voltage for the next bit. Successive approximation ADCs are much slower than flash converters because N clock cycles are required for each complete conversion, with the result that the conversion rate is only 1/N of the clock frequency.

Therefore, there is a need for an ADC which will require fewer comparators and comparison voltages yet will still produce a new digital sample for each cycle of the sampling clock.

Accordingly, the analog-to-digital conversion apparatus of the present invention comprises a sampling device for providing at outputs thereof samples of an analog signal delayed in response to a clocking signal.

A storing device receives bit signals produced by a plurality of comparators in response to the sampled analog signals and respective reference signals. The reference signals are developed in response to the stored bit signals. An output device develops the digital word from the bit signals developed by the comparators.

In the Drawing: Figures 1 and 5 are schematic diagrams partially in block diagram form of apparatus embodying the present invention; Figures 2 and 7 show illustrative signal waveforms useful in understanding the operation of the apparatus of Figures 1 and 5, respectively; Figure 3 is a schematic diagram of a portion of the apparatus of Figure 1; Figure 4 is a flow chart related to the operation of the apparatus of Figure 1; and Figure 6 is a diagram depicting the electron energy levels under a floating gate electrode in the apparatus of Figure 5.

In the exemplary embodiment of apparatus including the analog-to-digital converter (ADC) of the present invention shown in Figure 1, a four-bit analog to digital conversion is performed in a time period defined by four cycles of a sampling clock signal CS. During any clock cycle, a four-bit digital word is developed, at parallel output bit terminals B1 to B8, which represents the magnitude of the analog signal which was applied to analog video signal input terminal 110 four clock cycles prior in time.

Although four clock cycles are required to complete a digital to analog conversion, output digital samples are developed at the output terminals B1 to B8 at the repetition rate of the clock signal. This is because during any clock cycle four conversions are being processed - i.e. four separate comparisons are made in parallel to develop: the most significant bit (MSB) of the most recent analog value sample; the second MSB of the second most recent analog value sample; the third MSB of the third most recent analog value sample; and the least significant bit (LSB) of the fourth most recent analog value sample.

The detailed operation of the ADC of Figure 1 is described with reference to the signal waveforms illustrated in Figure 2. Sampling clock generator 114 develops clock signal CS having phase 4)1 shown in Figure 2b and phase 4)2 which is the inversion of phase (p1. Tapped analog delay line 112 is a metal-oxide-semi-conductor charge-transfer device with at least four output taps equally spaced one sample-clock time apart on the device. Delay line 112 samples the analog signal present at input terminal 110 during the time when clock signal 4)1 is high by charging a first internal node to the analog signal voltage.

When phase 4)1 becomes low and phase 4)2 becomes high, the charge on the first internal node is transferred to a second internal node.

Delay line 112 includes a plurality of such first and second internal nodes along which the charge is transferred in response to clock signal CS. Because each output tap receives the sampled analog signal from one of the first internal nodes when clock phase 4)1 is high and from a corresponding one of the second internal nodes when 4)2 is high, the sampled analog signal provided at each output tap is present during both halves of the clock cycle. The analog voltage sample "moves" through the taps T1 to T4 in response to successive cycles of clock signal CS.

As a result, the analog value during a first clock cycle is, in effect, sampled and held at first tap T1 during that clock cycle, at second tap T2 during the second cycle, at third tap T3 during the third clock cycle and so on. The exemplary analog signal shown in Figure 2a has a value "7" during clock cycle 2, a value "14" during clock cycle 3, and a value "0" during clock cycles 1 and 4 through 7. The sequence of sampled values corresponding to that analog signal is developed at tap T1, as shown by Figure 2c, and progresses along the delay line 112 to successive taps T2, T3 and T4, as shown by Figures 2d, 2e and 2f, respectively, on successive cycles of sampling clock CS.

The LSB of the digital sample has a weight of 20=1, the next bit a weight of 21=2 and soon up to the MSB which has a weight of 23=8. For convenience in the following description, comparators C, shift registers SR, output bit terminals B and digital-to-analog converters DAC are designated with a numerical suffix corresponding to the decimal weight of the bit which they are employed to develop. E.g., C8, SR-8, B8 and DAC-8 develop the MSB which has a weight of 8 in the exemplary 4 bit system herein described.

Four comparators C8, C4, C2 and C1, receive the sampled analog values from taps T1, T2, T3 and T4, respectively, of delay line 112 at their non-inverting input terminals. Comparator C8 determines the MSB, C4 the second MSB, C2 the third MSB, and C1 the LSB of the digital samples. Each comparator receives at its inverting input terminal a comparison voltage developed from a digital comparison word. For each comparator the digital word comprises a high level ("1") in the bit position to be determined, a low level ("0") for all lesser significant bit positions (if any), and the actual bit values ("1 " or "0") for all more significant bit positions (if any).As used herein, actual bit values are those values of the bits of a digital word which were developed during previous cycles of the sampling clock as part of the sequential conversion process.

To this end, the comparator output bit signals are stored in shift registers SR-8, SR-4 and SR-2 in response to clock signal CS. These bit signals are applied to the input terminals of respective shift registers: comparator C8 to three-stage shift register SR-8, C4 to two-stage shift register SR-4, and C2 to single-stage shift register SR2. No storage device is required for the LSB which is developed directly by comparator C1.

Each bit of the digital sample is developed during a subsequent clock interval in order of its decreasing significance - i.e. the MSB first, then the second MSB, and so on to the LSB. Correspondingly, the length of the shift register for each bit is increased by one stage in order of increasing bit significance - i.e. no shift register for B1 the LSB, a one-stage shift register for B2 the next higher significant bit and so on to a three-stage shift register for B8 the MSB. As a result, bits corresponding to the same analog value sample are always an equal number of shift register stages removed from the output terminal B8, B4, B2 and B1 so as to develop a four-bit parallel digital sample word thereat. Terminals B8, B4 and B2 connect to the output of the last shifting stage of the shift register associated therewith.

In other words, the number of clock cycles of digital delay introduced by the respective shift registers is selected so that the total number of clock cycles of delay introduced by the analog delay line 112 and by the shift registers SR is the same for each bit. Where I is an integer and 2' is the weight of the bit signal stored in a given shift register, that shift register has I shifting stages. Further, where J is an integer representing the number of clock cycles of delay associated with an output tap of delay line 112 the sum I + J for the delay line tap and shift register associated with any one bit is the same as the similar sum for any and all other bits.For example, the MSB is delayed by four clock cycles including one cycle in delay line 112 and three cycles in shift register SR-8; the LSB is delayed by four cycles in delay line 10 and has no shift register: i.e., the sum I + J equals four for the embodiment shown in Figure 1.

Comparison voltages applied to the inverting inputs of comparators C8, C4, C2 and C1 are developed by digital-to-analog converters DAC-8, DAC-4, DAC-2 and DAC-1, respectively. Each DAC receives actual bit values, "1 "s and "0"s, at its weighted input connections designated 8,4, 2 and 1 corresponding to the respective bit position weights. Each DAC receives a "1" at its input connection corresponding to the bit position for which it develops a comparison voltage, "0"s at its lower bit weight input connections, and actual bit values at its higher bitweight input connections. For example, DAC-2 develops the comparison voltage forthe second bit (weight 2). Thus, input connection "2" of DAC-2 receives a "1" level and input connection "1" receives a "0" level. Input connection "4" of DAC-2 receives the previously determined actual value of the 4weight bit from the next-to-last stage of shift register SR-4; input connection 8 receives the previously determined actual value of the weight bit from the next-to-last stage of SR-8. DAC-8, DAC-4 and DAC-1 are correspondingly connected.

The operation described above is further specifically delineated by Figure 2 and by Table I below which lists the digital signals present at various points in the apparatus of Figure 1.

TABLE I Clock Cycle 1 2 3 4 5 6 7 Comparator Bit Signals: C8 0 0 1 0 0 0 0 C4 0 0 1 1 0 0 0 C2 0 0 0 1 1 0 0 C1 0 0 0 0 1 0 0 Shift Register Stored Digital Words: SR-8 000 000 000 100 010 001 000 SR-4 00 00 00 10 11 01 00 SR-2 0 0 0 0 1 1 0 DAC Input Words: DAC-8 1000 1000 1000 1000 1000 1000 1000 DAC-4 0100 0100 0100 1100 0100 0100 0100 DAC-2 0010 0010 0010 0110 1110 0010 0010 DAC-1 0001 0001 0001 0001 0111 1111 0001 Output Word: B8,B4,B2,B1 0000 0000 0000 0000 0111 1110 0000 Comparators C8, C4, C2 and C1 respectively produce the output signals of Figures 2g, 2h, 2i and 2j in response to the analog samples of Figures 2c, 2d, 2e and 2f, respectively, for clock cycles 1 to 7.These comparator output signals cause shift registers SR-8, SR-4 and SR-2 to store the digital words listed in Table I, which in turn produce the DAC input words also listed therein. In result, the digital sample output words listed in Table I are produced comprising four bits in parallel. Figures 2k, 21, 2m and 2n show the waveforms at bit terminals B8, B4, B2 and B1 corresponding to the output words in Table I.

A general form of a DAC suitably employed as DAC-8, DAC-4, DAC-2 and DAC-1 is a conventional R-2R weighted resistive ladder shown in Figure 3. Where one or more of the lower weight bit inputs of a DAC is permanently connected to ground G to receive a "0" level signal, the lower portion of the R-2R ladder structure can be simplified. For example, where the structure of Figure 3 is employed as DAC-2, the R-weighted resistor closest to ground G and the two 2R-weighted resistors connected to the "1" input and ground G can be combined into an equivalent single resistor having a weight 2R. The greatest simplification is made for the DAC associated with the MSB which becomes a simple voltage divider employing two equal-valued resistors. DAC-1 associated with the LSB is not amenable to such simplification.

The flow chart of Figure 4 sets forth the steps in the operation of the ADC of Figure 1 described above. In a time interval defined by a cycle of the sampling clock, analog signal 200 is first sampled and held 202 and is compared 204 to an analog signal representative of the value of the MSB of the digital word. The bit resulting from that comparison is stored 206. In each subsequent time interval, the conversion process 202, 204 and so on begins again 208 for the now present magnitude of the analog signal while the conversion process 210, 212 and soon continues for each of the analog magnitudes previously sampled and held 202. Then, for each digital word not yet fully developed, an analog signal representative of the weighted sum 210 of the bits previously produced and stored and the next lesser significant bit of the digital word is developed.The previously held 202 analog sample is then compared 212 to the analog value representative of the weighted sum.

If all bits of a given digital word including the LSB have not yet been developed 214, the NO branch is followed. The resulting bit stored 216 and the sequence of steps of developing 210 and comparing 212 are repeated 220 for each digital word being developed. If all bits including the LSB have been developed 214, the YES branch is followed causing the digital word to be developed 218 from LSB and the bits previously developed and stored. The sequence repeats 220 beginning at the developing step 210 for each digital word being developed.

As indicated above, this sequence of steps is performed in each subsequent time interval. Thus, in any given time interval, the MSB of a digital word corresponding to the present analog magnitude is developed and the complete digital word whose LSB is developed is finally developed. In addition, other digital words are in various stages of development: in an N-bit ADC, N-2 other digital words are also being developed.

The embodiment of an ADC shown in Figure 5 employs pipe-lined data flow through paralleled charge transfer channels in a charge-coupled device (CCD) for implementing the successive-approximation conversion algorithm described above. The differential comparison of the representation of the input analog signal in a first charge transfer channel to a representation of quantized analog signal in a second charge transfer channel plus a distinct trial bit in a third charge transfer channel is facilitated using a floating-gate differential charge subtraction process. A battery of progressively shorter shift registers is used to convert the pipelined ADC digital output from the comparators to parallel-bit digital form.

For convenience, the following description of details of the charge transfer aspects of the ADC of Figure 5 is written following the convention that the semiconductor substrate in which charge transfer channels exist is oriented so that the gate electrodes overlie the channels. Figure 5 shows first, second, and final ones of "n" sections of a CCD analog-to-digital converter, where "n" equals the number of bits of resolution the ADC is to provide. To obtain both high resolution and high sampling rate, the Figure 5 ADC features pipe-lined data flow using CCD shift registers to synchronize outputs from the successive converter sections, floating-gate differential charge subtraction, and auto-zeroing high-speed sense amplifiers.

The floating-gate differential charge subtraction process, which will be described presently in greater detail, is facilitated by using complementary uni-phase clocks. Uni-phase clocking is provided to a CCD channel by applying a single phase of a rectangular-wave clock signal to alternate ones of its paired storage and transfer gates and by applying to the intervening ones of its paired storage and transfer gates a direct, reference potential VREF. It is convenient to make VREF substantially equal to the average value of the rectangular-wave clock signal to create potential conditions in each CCD channel resembling those in a standard two-phase clocking arrangement. Complementary uni-phase clocks are provided by making the respective rectangular-wave clock signals in two CCD channels anti-phase, so one is high in potential when the other is low and vice versa.

The floating gate is recurrently clamped to VREF as a dc restoration measure preparatory to auto-zeroing.

To facilitate the auto-zeroing, on alternate clock cycles, multiplexer 10 applies a zero level signal to a charge injection stage 12, and multiplexer 11 operates on following 4)2 clock cycles to apply a zero level signal to a charge injection stage 13. These zero level signals condition charge injection stages 12 and 13 to inject no charge into the charge transfer channels following them, for propagating empty energy wells through the charge transfer channels following them. Where Charge injection stages 12 and 13 are of fill-and-spill type, injection of charge can be inhibited by multiplexers 10 and 11 selecting a very negative voltage for application to stages 12 and 13.Or multiplexers 10 and 11 can be provided simply by seiectively inhibiting fill pulses on the source of the fill-and-spill charge injection stage.

On alternate +, cycles, when multiplexer 10 selects analog signal source 14, the analog signal voltage is accompanied by a VZERO reference component. VZERO iS that voltage at which charge injection stage 12 is at the limit of no longer injecting charge.

During the clock cycles intervening between the clock cycles in which auto-zeroing is performed, multiplexer 10 selects analog input signal voltage from source 14 for application to charge injection stage 12, and multiplexer 11 selects a standard voltage level from source 15 for application to charge injection stage 13. The standard voltage level is twice a direct voltage VONE, as referred to the voltage at the limit where charge injection stage 13 no longer injects charge. VONE corresponds to the value of voltage supplied from analog signal source 14, as referred to VZERO, which is to be that for which the most significant bit of ADC output is binary ONE while the less significant bits are all ZERO's.This standard voltage has to be somewhat smaller than the voltage which when applied to any ofthe charge injection stages 12 and 13 would be just under that voltage which would cause overflow of the first energy well in the ensuing charge transfer channel, smaller by at least VZERO It should not be much smaller, since comparator error in the comparison processes of analog-to-digital conversion is worsened.

Charge injection stage 12 injects negative charge packets alternatively of zero value and of variable amplitude Os + Q0 into an "analog signal" charge transfer channel 16 over which an n-numbered plurality of floating-gate sensor electrodes FGI, FG2, ...FGn are disposed. Q0 is the charge associated with VZERO input, and Os is the charge associated with the analog signal voltage in addition to ZERO. Charge transfer channel 16 is operated with uni-phase clocking, those gates not having VREF applied to them having the same clock phase 1 applied to them.

Charge transfer channel 16 is depicted in abstract form in Figure 5. The only gates shown, being shown as dashed lines, are the floating gates and the storage gates immediately before and after each floating gate.

This is done to indicate the relative timings of the uni-phase clocking along the various charge transfer channels indicated by respective straight lines.

The other charge transfer channels which underlie each of floating-gate sensor electrodes (e.g., charge transfer channels 19-2 and 20-2 underlying FG2) are operated with uni-phase clocking complementary to the uni-phase clocking of charge transfer channel 16. That is, those gates not having VREF applied to them have the same clock phase +2, opposite to clock phase 1, applied to them. This is done to implement the subtraction at each floating gate of potential response to the charges in these channels from the potential response to the charge in the analog signal charge transfer channel 16. During interspersed sensing intervals the voltages induced on these floating gates are sensed.Each voltage depends on the difference between the quantity of negative charge that had been transferred from the storage well under the floating gate via analog signal charge transfer channel 16 during an earlier portion of the + clock interval in which the sensing interval occurs, and the quantity of negative charge that had been concurrently transferred into storage wells under the floating gate via other charge transfer channels. This subtraction process resembles that described in U.S. Patent No. 4,104,543 entitled MULTICHANNEL CCD SIGNAL SUBTRACTION SYSTEM.

The charge transfer channels are preferably of the buried type, and they are dimensioned similarly under the floating gate electrodes.

Responsive to application of twice VONE, charge injection stage 13 injects negative charge packets of uniform amplitude QR into a charge transfer channel which is the input of a first (18-1) of a cascade connection 18 of charge splitters 18-1, 18-2,... 18-n, each of which divides the negative charge received at its input into equal halves appearing at its first and second outputs. Each of these charge splitters except for the nt-- that is, the last - has its first output connected to the input of the succeeding charge splitter. So, their second outputs supply progressively smaller negative charges with binary-weighted amplitudes QR12, QR/4 ...OR/2" to be used as the trial bits applied as respective inputs to "trial bit" charge transfer channels 19-1, 19-2,... 19-n which underlie floating gate sensor electrodes FG1, FG2,... FGn respectively.

Figure 5 shows a succession 20 of third, "partial sum" charge transfer channels 20-1, 20-2, ... 20-n underlying electrodes FG1, FG2, FG3. Charge transfer channel 20-1 has a charge packet of amplitude Qo which is zero-valued. Each succeeding one of these charge transfer channels 20-2 through 20-n receives input from the output of the preceding partial sum charge transfer channel. It also selectively receives input from the trial bit charge transfer channel passing under the same floating gate sensor electrode as does that preceding partial sum charge transfer channel.Input is received only if the negative charge packet in the trial bit charge transfer channel from the preceding ADC stage has not been drained off to a drain connection, as controlled by a respective one of gate structures G1, ...... Gns This draining off is the discarding of the bit presumed-to-be-ONE that occurs when the differential comparison process indicates that the already quantized analog signal and this bit exceeded the analog signal in charge transfer channel 16.

Figure 6 illustrates the charge subtraction process and is descriptive of the minimum electron energy levels in the three charge transfer channels underlying a unipotential floating gate electrode in any of the ADC stages. The minimum electron energy level under the unidirectional floating gate electrode is shown in heavy black and is associated with the most positive substrate potential present in a p-substrate device.

There is a step in each energy level due to a barrier implantation under the second level transfer gate, per conventional practice in CCD's using uni-phase or two-phase clocking. The relative minimum electron energy levels under the electrode flanking that under the floating gate electrode are shown in dashed form for each of the three channels underlying that electrode, at times immediately following four successive transitions in the 1 and 4)2 clocks. These transitions I, II, III, and IV occur in order of their ordinal numbering as can be seen by cross-reference to the Figure 7 timing diagram and describe a full cycle of analog-to-digital conversion including the auto-zeroing preceding the differential comparison step.Clock transition II is that most immediately preceding an auto-zeroing, and clock transition IV is that most immediately preceding a differential comparison to resolve one bit of the analog-to-digital conversion.

Returning attention to Figure 6, after transition I of the 4)i, 4)2 clocks, +1 is low or relatively negative, and 4)2 is high or relatively positive. With electrodes flanking the floating gate in the analog signal channel 16 negative respective to the floating gate electrode, owing to Q1 being low, the energy well under the floating gate electrode is filled with zero negative charge from the lifted energy well under the preceding gate electrode.At the same time the energy wells under the floating gate electrode in the other two channels are emptied of old non-zero negative charge packets, which flow to depressed energy wells under the succeeding gate electrodes to which high 4)2 clock potential is applied.

Thereafter, responsive to a QR pulse, the floating gate electrode is clamped to VREF potential. The path for the clamp current is through three capacitances in series; specifically, the oxide capacitance, the capacitance from semiconductor substrate surface to the buried channel, and the capacitance from the buried channel to substrate ground. The last capacitance is the smallest, owing to relatively great interplate spacing; and the displacement current flow during a clamp of the series connection of the three capacitances operates mainly to change the potential on this last capacitance. The charge on the much larger capacitances, associated with transfer of negative charge in the charge transfer channels, is essentially unaffected.

Subsequently on transition II of the " 4)2 clocks the electrodes flanking the floating gate electrode in the analogue signal channel 16 are high or relatively positive in potential, and those flanking the floating gate electrode over the other charge transfer channels are low or relatively negative in potential. The zero negative charge in the analog signal channel 16 empties into the energy well under the electrode after the floating gate electrode. There is no appreciable change in the floating gate electrode potential with transfer out of zero negative charge. At the same time in the other two charge transfer channels there is a transfer in of zero negative charge, which causes no appreciable change in the floating gate electrode potential. The floating gate electrode remains, then, at essential VREF during the subsequent auto-zeroing of the sense amplifier it serves as input to. The auto-zeroing of the sense amplifier will, then, be with reference to this essential VREF potential. Referring to the Figure 7 timing diagram, auto-zeroing takes place at times when FS and QZR clocks are simultaneously high.

Returning to Figure 6, transition lil of the +" 4)2 clocks follows. The electrodes flanking the floating gate electrode in the analog signal channel 16 are low or relatively negative, and a new negative charge packet Os flows into the energy well under the floating gate electrode to cause a negative change in the electrode potential. At the same time zero negative charge packets are transferred out from under the floating gate electrode through the other charge transfer channels because of the electrodes to which 4)2 clock is applied being high, or relatively positive, in potential. This transfer of zero charge causes no change in electrode potential.The floating gate electrode is then clamped to VREF responsive to QR pulse, and the displacement current adjusts the-quiescent potential between the buried channel and substrate. The potentials after the charge equilibration remain as the clamp is removed.

Following transition IV of the (p1, 4)2 clocks the high, relatively positive condition on the 1 electrode following the floating gate electrode allows transfer of charge Os from the energy well located in channel 16 under the floating gate electrode. This causes a positive component of potential change on the floating gate electrode. At the same time the energy wells located in the other charge transfer channels located under the floating gate electrode are filled with negative charge from the energy wells under the preceding electrodes to which low or relatively negative 4)2 potential is applied.This filling with negative charge of the wells located under the floating gate electrode in the other channels causes respective negative components of potential on the floating gate electrode. After completion of charge transfers, the 4)s clock goes high while FZR clock remains low and the sense amplifier senses the sum of the positive component of potential induced by charge being emptied from the energy well under the floating gate electrode in the analog signal charge transfer channel 16 and the negative components of potential induced by charge filling the energy wells under the floating gate electrode in the other charge transfer channels.

It is convenient at this point to refer to the Figure 7 timing diagram, in conjunction with Figure 5. The "high" conditions of the , and 4)2 clocks are associated with their equalling an operating voltage +VDD which is positive relative to VREF and VONE; and the "low" conditions of the 1 and 4)2 clocks are associated with their equalling a ground voltage which is negative relative to VREF and VzEflo.

The floating gate sensors FG1, Fug1,... FGn are recurrently clamped to VREF as noted in the text above concerning Figure 6. The clamps are to the floating gates FG1, FG2,... FGn are made through the channels of respective field effect transistors YETI, FET2,... FETn, respectively, responsive to a timing pulse QR applied to their gate electrodes. These timing pulses are applied during times the 1 clock phase is low and 4)2 clock phase is high. That is, the floating gate electrodes are high respective to the flanking phase electrodes in the analog signal charge transfer channel 16 and low respective to the flanking 4)2 phase electrodes in the other charge transfer channels under them.

Consider the case where auto-zeroing is to follow the clamping of the floating gate electrodes FG1, Fug1,...

FGn to VREF at the time when 4)R is high to clamp the electrodes. The negative charge packets under the floating gate electrodes and in analog signal channel 16 are zero-valued. This is responsive to multiplexer 10 having, at earlier times in the pipeline operation, applied signals to charge injection stage 12 inhibiting its injecting charge into channel 16.During the q),, 4)2 clock transition II, which occurs after 4)R goes low to release the clamps on the floating gate electrodes, there is therefore no charge to be transferred from under the floating gate electrode to wells under the electrodes immediately to right of them in analog signal channel 16, so that the floating gates will remain at VREF. During the q), 4)2 clock transition 11 the charge packets transferred to positions under the floating gates in the other charge transfer channels will be zero-valued, owing to multiplexers 11 having inhibited charge injection stage 13 from injecting charge into the pipeline connection of charge splitters.So there is no negative component induced in any of floating gate electrode potentials by negative charge in any of the charge transfer channels beneath the floating gate electrodes FG1, Fop,... FGn. Consequently the floating electrodes remain at VREF potential.

Auto-zeroing is performed on the 4)s pulse following clock transition II, the alternate 4)s pulses on which auto-zeroing in performed being labelled ZR in Figure 7. The off-side inputs of the differential comparator input stages of sense amplifiers SA1, SA2,... SAn i.e., those inputs not connected to respective ones of floating gate electrodes FG1, FG2,... FGn--are, then, adjusted so the comparators would toggle if the floating gate electrode potentials were to pass through the VREF level.

Consider now the case where evaluation of the negative charge packets descriptive of analog signal samples from source 14 is to follow the clamping of the floating gate electrodes FG1, FG2,... FGn to VF. The negative charge packets under these floating gates and in analog signal channel 16 are descriptive of multiplexer 10 having selected at successive times samples of analog input signal voltage for application to charge injection stage 12.Following the " 4)2 clock transition IV after QR goes low to release the clamp on the floating gate electrodes, the negative charge packets descriptive of these successive samples are transferred to successive electrodes in analog signal channel 16 to induce on the floating gate electrodes FG1, FG2,... FGn positive components of potential descriptive of successive analog signal samples.Following the same " 4)2 clock transition IV negative charge packets descriptive of successive binary-weighted fractions of OR are transferred under floating gate electrodes FG1, FG2,... FGn via charge transfer channels 19-1, 19-2,... 19-n; and negative packets of charge descriptive of partial sum from preceding conversion stages are transferred under floating gate electrodes FG1, Fop,... FGn via charge transfer channels 20-1,20-2, ... 20-n. These negative charge packets induce the negative components of the potentials on the floating gate electrodes.

The resultant potentials on the floating gate electrodes FG1, FG2,... FGn are then compared against VREF by sense amplifiers SA1, SA2, ... SAn respectively, to determine if their positive components responsive to analog signal samples exceed or fail to exceed their respective negative components. The linear combination of negative and positive components of floating gate voltage is highly accurate, and the high resolution of the Figure 5 ADC depends in large measure on this accuracy. Accuracies of better than 0.2% for a 20 nsec sensing time are anticipated from this subtraction process.

The successive-approximation algorithm which derives from a standard level the samples that give rise to the negative components of voltage on the floating gate sensor electrodes FG1, FG2,... FGn will now be described in detail with reference to Figure 5. The positive component of voltage on electrode FG1 when being operated as a floating gate sensor is attributable to charge packets of amplitude representative of the analog signal from source 14 injected by charge injection stage 12. The negative component of voltage on electrode FG1 when being operated as a floating gate sensor is attributable to negative charge packets of amplitude OR/2 being supplied from charge splitter 18-1.The response of comparison amplifiers SA1 to net FG1 electrode potential being negative is indicative that the amplitude of a negative charge packet sampling analog signal clocked out of a storage well under FG1 electrode via channel 16 on the fa clock transition preceding the sensing interval fails to exceed a negative charge packet of QR12 amplitude clocked into a storage well under FG1 electrode via channel 19-1 on the concurrent 4)2 clock transition preceding the sensing interval.This response is subjected to a digital delay DD1. The delayed response PSD1 then forward-biases gate G1 to drain off to a drain connection the negative charge packet at the output of charge transfer channel 19-1, rather than letting it be clocked forward into partial sum charge transfer channel 20-2 during a following clock cycle. (The initials "PSD" used in the alpha numeric descriptions PSD1, PSD2,...

PSDn of the signals supplied to gates G1, G2, ... Gn to control "dumping" of partial sum channel charge stand for "partial sum dump." PSDX is shown in solid line in the timing diagram of Figure 7; and PSD2 is superposed in dashed line on the same time axis.) In the case just described, in which the partial sum charge from 19-1 is dumped, on the following clock cycle charge transfer channel 19-2 moves a negative charge packet of amplitude QR/4 under floating gate sensor electrode FG2, but the charge transfer channel 20-2 moves no charge packet under FG2.The ZERO output from digital delay DD1 is forwarded by an (n-1 )-bit shift register SR-(n-1) to ADC output as its most significant bit (MSB)--i.e., the bit descriptive of whether binary weight representation of two raised to the (n-1) power is or is not a part of the quantized analog signal. SR-(n-1) is one of (n-1) shift registers successively one stage shorter in the successive sections of the ADC up to the single-stage shift register in the penultimate section (not shown) of the ADC. These shift registers convert pipe-lined ADC output to parallel-bit digital form. These shift registers are preferably CCD registers of surface channel type because of the simpler interfacing with MOS field effect transistor circuitry in the preceeding sense amplifiers.

On the other hand, consider the case where the delayed response of sense amplifier SA1 to net FG1 electrode potential is negative, indicative that the negative charge packet sampling analog input signal has an amplitude which exceeds OR/2. This response is forwarded to ADC output by shift register SR-(n-1) as a ONE most significant bit. The delayed response applied by digital delay DD1 to gate G1 forestalls draining off of charge from the output of charge transfer channel 19-1. So, this negative charge of QR/2 amplitude, not having been dumped, is clocked forward as input to partial sum charge transfer channel 20-2 during the following clock cycle.

Then, during the following clock cycle, floating gate FG2 will have had total negative charge of amplitude QR/4 or 3QR/4 moved under it for inducing the negative component of its sensed potential, depending on whether the most significant bit of the ADC process was determined to be a ZERO or a ONE. Subtractive combining of this component of potential, with that responsive to analog input signal during floating gate sensing, supplies sensing amplifier SA2 its input. Its response is a ONE or a ZERO depending on whether Qs does or does not exceed the amplitude of the negative charge inducing a negative component of potential on electrode FG2.This response is delayed by digital delay DD2 to provide a signal PDS2 that controls gate electrode G2 potential, for draining off negative charge at the output of reference level charge transfer channel 19-2 if the response is ZERO. If the response is a ONE, the negative charge packet is undisturbed and will be clocked forward during the following clock cycle as input to partial sum charge transfer channel 20-3 (not shown). The delayed response from digital delay DD2 is further delayed by (n-2)-bit shift register SR-(n-2) so the second-most significant bit of the pipe-lined ADC is provided in parallel with its most significant bit. This is the bit descriptive of whether binary weight representative of two raised to the (n-2) power is or is not contained in the quantized analog signal.

The successive approximation technique described repeats itself through each successive ADC-section.

The nth and final section of the ADC supplies the least significant hbit of the conversion directly from digital delay DDn. This is the bit descriptive of whether binary weight representative of 1 would or would not be contained in the quantized analog signal output. If quantized analog signal is not required as an output from the ADC, the output of charge transfer channel 19-n may be directly dumped to a drain connection, dispensing with gate structure Gn and the path to a final charge combining as at the input of a further charge transfer channel 20-(n+1).

The operation of this ADC differs from a conventional ADC using a successive-approximation algorithm in that comparisons to binary-weighted fractions of reference level are not made one at a time, but rather a plurality of comparisons n in number are simultaneously made on n successive signal samples. This allows a high conversion rate to be obtained.

Auto-zeroing on alternate samples clocked through the ADC causes the analog-to-digital conversion rate, or effective sample rate, to be one-half the rate of the clocking signals applied to the ADC charge transfer channels. An effective sampling rate of the analog input signal equal to the clocking rate is obtained by time-division-multiplexing two of the Figure 5 ADC's by operating their complementary uni-phase clocks in anti-phase respective to each other. However, the total conversion time for the n bits of ADC output exhibits a delay or latency time equal to n times the time required to obtain each bit of the conversion. E.G., in an bit CCD ADC with four stages per section, the latency time would be 1.6 ,usec, presuming a 20 MKz clock frequency and a 10 MHz sampling rate of analog signal from source 14.

It is important to note that the present invention is not limited to the four-bit resolution ADC described herein. Lesser or greater-bit resolution ADCs are readily realized by respectively decreasing or increasing the number of taps of delay line 112, and the numbers of comparators C, shift registers SR and digital-to-analog converters DAC employed. Thus, an N-bit ADC requires an N-tap analog delay line, N comparators and DACs, and N-1 shift registers, the longest of which has N-1 shifting stages.

Modifications to the above described embodiment are contemplated to be within the scope of the invention: for example, shift registers SR can be replaced by a read-write memory device in which the output bits developed by comparators C are stored. The stored bits are read at appropriate times during the conversion sequence and applied to respective input terminals of the respective DACs in the manner described herein.

In addition, utilization apparatus receiving the output digital word from output terminals B8, B4, B2, B1 of Figure 1 may require that the bit signal transitions thereat occur substantially simultaneously. To that end, a shift register SR-1 (not shown) is interposed between comparator C1 and terminal B1 to remove the delayed bit signal transition of the LSB caused by the propagation delays of DAC-1 and C1. SR-1 need only have one shifting stage. So that all bits of each output digital word continue to be developed during the same clock cycle, each other shift register SR-8, SR-4 and SR-2 is lengthened by one shifting stage. That additional shifting stage is interposed between the present last shifting stage and the corresponding output terminal, B8, B4 and B2.A similar modification can be made with respect to shift-registers SR-(n-1), SR-(n-2) and so on of Figure 5 in relation to terminal 2(no1), 2(n-2), ... 20.

In the embodiment of Figure 5, the clocking of negative charge packets under the floating gate electrodes is such that samples of the analog signal have samples of the analog signal as thusfar quantized and trial bit samples subtracted from them. Alternative embodiments are contemplated in which the clocking of the negative charge packets under the floating gates is such as to subtract samples of the analog signal from the summed samples of the analog signal as thusfar quantized and trial bit samples, an appropriate logical inversion being included in each of the sense amplifiers.

By way of further example, the linearity of charge injection stage 12 can be improved by the inclusion of "fat-zero" source 34, multiplexer 30 and charge injection stage 32 shown in Figure 5. In "fat-zero" operation, a charge packet of magnitude Qp is injected into charge transfer channel 20-1 during times when multiplexer 10 selects analog source 14 to compensate for the non-zero charge injected by stage 12 in response to ZERO.

Multiplexers 10 and 30 select the zero-level source at the same times.

Claims (14)

1. An analog to digital conversion apparatus for producing a digital word representative of the level of an analog signal, comprising: a source of a clocking signal; sampling means responsive to said analog signal and to said clocking signal for developing a plurality of successive delayed samples of said analog signal, the occurrence of said samples being successively delayed by a number of cycles of said clocking signal relative to its occurrence at the input of said sampling means; a plurality of comparators receiving at corresponding inputs thereof delayed samples of said analog signal from said sampling means to produce, at outputs of said plurality of comparators, signal bits for constituting said digital word; means for storing representations of the signal bits so produced;; means responsive to the representation of the signal bits so stored for developing a plurality of reference levels that are applied to corresponding inputs of said plurality of comparators, the developed reference levels, when compared with the corresponding delayed samples, producing said comparator output signal bits with values that establish the value of said digital word as representative of the level of the sampled analog signal; and means responsive to said signal bits for developing therefrom said digital word.

2. Apparatus as claimed in claim 1 wherein said means for storing comprises a plurality of shift registers each having a respective input to which the signal bits produced by one of said plurality of comparators are coupled and each said shift register receiving said clocking signal for shifting said signal bits.

3. Apparatus as in claim 2 wherein each said shift register includes I shifting stages, where I is an integer selected so that 2' is the weight of the signal bits of said digital word stored in that said shift registers

4. Apparatus as in claim 2 wherein each said shift register includes I shifting stages, where I is an integer selected so that the sum of I + J for each bit position of said digital word equals the same integer value, J being the number of clocking cycles of delay associated with the output sample of said sampling means corresponding to that said bit position.

5. Apparatus as in any preceding claim wherein said means for developing said plurality of reference levels comprises a plurality of digital-to-analog converting means, each associated with a one of said plurality of comparators.

6. Apparatus as in claim 5 wherein of said converting means that associated with a given comparator developing signal bits having a weight of 2' in said digital word has N input terminals signals applied to which have respective weights 2' in the converting means, where I is an integer in the range 0 313 I 3 N-1,said converting means further having: means for appling a logically true signal to said 2' weighted input terminal; means for applying a logically false signal to all said input terminals weighted less than 2', and means for applying the stored signal bits having weights greater than 2' to the ones of said input terminals having corresponding weights.

7. Apparatus as in Claim 1 wherein said sampling means comprises a charge transfer device channel including: means for supplying thereto respective charge packets on each successive clock cycle, said charge packets representing samples of said analog signal on evenly-numbered clock cycles and of a zero level on oddly-numbered clock cycles, and a plurality of gate electrodes proximate said channel to be responsive to said charge packets for providing said delayed analog signal samples.

8. Apparatus as in Claim 7 wherein said means for developing a plurality of reference levels comprises a second charge transfer device channel including: means for supplying thereto respective charge packets on each successive clock cycle, said charge packets representing a reference level on said evenly numbered clock cycles and a zero level on said oddly-numbered clock cycles, the respective reference levels being related in substantially binary weighting with progressively smaller reference levels being applied to the inputs of said plurality of comparators corresponding to progressively lesser significant bits of said digital word.

9. Apparatus as in Claim 8, wherein said plurality of gate electrodes are proximate said second channel to also be responsive to said charge packets representing said reference levels.

10. Apparatus as in Claim 9 wherein said means for storing comprises a third charge transfer channel including means responsive to said signal bits for supplying said charge packets representing said reference levels to said third channel.

11. A method of developing successive digital words from the correspondingly successive magnitudes of an analog signal, comprising the steps of: in a given time interval: (a) sampling the magnitude of said analog signal; (b) developing a first analog level representative of the position value of the most significant bit of the digital word; (c) comparing said sampled analog signal magnitude obtained in step (a) to said first analog level to develop the value of the most significant bit of the digital word representing the sampled analog signal magnitude referred to in step (a); (d) storing a representation of the bit so developed in step (c); and (e) repeating steps (a) through (d) for the analog signal magnitude occurring in said each subsequent time interval; and further performing the following steps: (f) developing, for each given one of said digital words not yet fully developed, an analog level representing the weighted sum of the representations of the bits stored in previous time intervals for each given one of said digital words and of the position value of the next lesser significant bit thereof not yet determined; (g) comparing, for each given one of said digital words not yet fully developed, the corresponding sampled analog signal magnitude to the analog level developed in step (f) to develop the value of said next lesser significant bit thereof; (h) if the next lesser significant bit developed in step (g) is not the least significant bit, then storing a representation of the bit so developed in step (g); and (i) if the next lesser significant bit developed in step (g) is the least significant bit, then developing said given one of said digital words from the least significant bit and from the other bits of said digital word that were developed in previous time intervals.

12. The method of Claim 11 wherein step (f) comprises, for each given one of said digital words not yet fully developed, the steps of: (j) developing a logically true signal in the bit position of a comparison digital word corresponding to the bit position of the said next lesser significant bit; (k) developing logically false signals in all bit positions of said comparison digital word of lesser significance than the bit position defined step (j); (I) applying the representation of the bits of said given one of said digital words not yet fully developed stored in previous time intervals to the corresponding bit positions of said comparison digital word, which bit positions are those of greater significance than the bit position referred to in step (j); and (m) converting said comparison digital word to said analog level.

13. The method of Claim 11 wherein: Step (d) includes the step of: (j) storing said first analog level as said representation of the bit developed in step (c) if said bit so developed in step (c) is a logically true signal; and wherein; Step (h) includes the step of: (k) combining, for each given one of said digital words not fully developed the analog levels developed from previous time intervals in which the bit developed was a logically true signal; and (I) storing said combined analog level to provide said weighted sum for the next subsequent time interval.

14. An analog-to-digital converter substantially as hereinbefore described with reference to Figure 1 or Figure 5 of the accompanying drawings.