SU1300635A1 - Analog-to-digital converter - Google Patents

Abstract

The invention relates to computing and can be used, in particular, in digital oscilloscopes. The invention allows to improve the noise immunity. This is achieved by introducing a comparator 1 and adder 12 to implement a complex analog-to-digital converter (ADC), in which the components of its small-sized parallel ADC 6, 9 have a quantization interval 2 times larger than in known ADCs. 2 Il. i (L SAE O SO CL II fug .;

Description

The invention relates to computing and can be used, in particular, in digital oscilloscopes.

The aim of the invention is to improve noise immunity.

Figure 1 shows the functional diagram of the device for 4 bits of the output code; Fig. 2 illustrates the distribution of quantization levels between low-level parallel analog-to-digital converters (MS).

The device contains an input signal bus I, a reference voltage bus 2, a common bus 3, a second current-limiting element 4 made on a resistor, second inputs 5 A1D11 small-sized parallel A1Sch 6, first inputs 7 ADC, second current-limiting element 8, made on a resistor, a small-sized parallel A1SCH 9, the first current-limiting element 10, executed on the resistor, comparator II, adder 12, each low-voltage parallel A1SCH 6, containing a voltage divider 13, implemented on the resistors, and a block 14 of comparators encoding th logic.

Consider the operation of a 4-bit A1SC device composed of two 3-bit ADCs.

Let it be necessary to produce a quantum input signal with a quantization interval & . A complete set of quantization levels, which transforms the input voltage into a 4-bit code with quantization intervals L, is shown on a scale of 1 of Fig. 2. The distribution of these levels between the dividers of small-sized A1Sh 6 and 9 is shown on the scales 2 and 4, respectively.

In Figure 2, it can be seen that when the quantization levels are distributed over wils, the level is equal to & (gakala 3), it is formed by the first resistor 10. To compare this level, a comparator P. is necessary.

In this example, the quantization level A1SCH 9 is shifted relative to the quantization levels of the ADC 6.

In a small-sized A1Sh 6, the input signal is quantized by levels of 2, 4, 6, 6 ,. .., 14l.

In the low-order A1SCH 9 - by the levels of 3l, 5l, 7l, ..., 15X. Thus, all levels of quantization provide 5

O

-5 O

0

50

Converting the input to a 4-bit code with a quantization interval &, is distributed between 6 and A1SCH 9 (with a comparator I 1) through one, so that the quantization intervals inside the small-bit A1SCH 6 and 9 are twice as long as the resulting quantization interval.

The choice of resistor values is as follows.

The first resistors 10 provide the offset of the scales of small-size ADCs. Since, in the device, the offset value (as shown) is a, a, and the quantization interval inside small-size ADCs is 2 L, the resistance of the first resistor 10 is 1/2 the R-half of the resistance of one resistor R from the voltage divider 13 of the small-size ADC (in total, there are 2 such resistors in the divider, K is the number of bits of the low-level ADC).

To ensure equality of conversion quanta within all components of small-size ADCs, the total resistances of all parallel resistor circuits (each such circuit contains a small-scale divider A1SC and the first and second resistors) connected between the reference voltage bus and the common bus should be the same.

The dividers of all small-sized А1Щ are the same; therefore, the total resistances of the first and second resistors in all circuits must also be the same.

Since the maximum value of the first resistor (as shown) is not

exceeds -r- R, then the sum of the resistance of the first and second resistors can be taken equal to R. Then in the device under consideration the magnitudes of the second resistors are t,

 R.

I. .

- The voltage U on the bus 2 of the reference voltage is chosen equal to (2 +1) -th. : P, where K is the number of bits of a small-size ADC; n is the number of small-sized ADCs; & - result interval of quantization.

This voltage is distributed as follows: part of the voltage p is applied to

and. - and ..

HRT 5-7

the divider of small-scale A1SCh, the second part of the voltage U, is equal to lp.

313

comes in additional resistors.

To ensure that the scales are matched, resistors 4.8 and 10 are chosen in the same accuracy class as the resistors P of the low-level ADC divider.

The output code of any parallel A1SC is the number of quantization levels represented by the binary code exceeded by the input signal. In the device, the quantization levels distributed between A1SCh 6 and 9 are not incremental, but after one, all the quantization levels exceeded by the input signal in all small-size ADCs and the comparator allow for the adder. Therefore, the outputs of all small-size ADCs and additional comparators are connected to the corresponding inputs of the adder. For example, when using the 1ZZMZ 1 adder, the outputs of the A / D converter 6 are connected to the first inputs of the three low-order bits of the adder (Fig. 1), the outputs of Aljjl 9 to the second inputs of the same

bits, the output of comparator 11 connects-25 or false triggering is comparated with the carry input.

The coding of the input signal is carried out simultaneously by all small-bit ACs.

For example, when encoding an input signal Ug with a magnitude of 7 l in ADC 6, 3 quantization levels will be exceeded (FIG. 2), and the code at the output of ADC 6 corresponds to the number 3.

In ADC 9, three levels are also exceeded and the code at the output of ADC 9 corresponds to the number 3; output comparato. ra 11 is a single signal. At the output of the adder (device output code corresponds to a number.

Thus, in the device, in contrast to the known quantization levels, separated from each other by the value of l, are formed not in the same, but in different small-size A1SCh; inside one small-size ADC, the adjacent quantization levels differ by 2a. The disturbance of magnitude l, arising from the slab of this small-size ADC, will require the interference with an amplitude of 2 U, i.e. 2 times the noise immunity of the proposed device 30 exceeds the noise immunity of the known devices.

Claims (1)

Invention Formula 35 Analog-to-digital converter containing two small-sized parallel analog-to-digital converters, the first input of the first small-sized parallel analog-to-digital converter is connected to the common bus directly, and the first input of the second small-sized parallel analog-to-digital converter through the corresponding first 45 limiting element, executed on the resistor, the second inputs of small-size parallel analog-to-digital converters through the corresponding second current-limiting no element A comparator inside of a small array of 50 you, made on resistors, under the A1C in the known device will cause a false triggering of the neighboring comparators. The same interference in the proposed device will not cause a false response. I Interference with amplitude & causes a false positive only for comparators with reference voltages. The third inputs of small-size parallel analog-digital converters are connected to the reference voltage bus; they are combined and are the input bus. 55 signal, characterized in that, in order to improve noise immunity, an adder and a comparator are introduced, the first input of which is the input signal bus, differing by the value of a, and in this device the reference voltages differing by this conversion quantum are formed not in one A1, but in the dividers of various small-size ADCs. Therefore, the interference that occurs when the comparator is triggered will be external to the rest of the small ADC, where the reference voltages are formed, which differ from the reference voltage of the activated comparator. Correct wiring of power circuits, filters in circuits, power and reference voltages applied to the microcircuit of each low-level ADC, allows you to limit the effect of interference from one low-level ADC, where the comparator operated, to other ADCs. In the dividers of each small-size ADC, the quantization levels are separated by a value of 2 liters and noise with an amplitude of l. not. enough to cause false positives The ditch of this small-size ADC will require an interference with an amplitude of 2 U, i.e. 2 times the noise immunity of the proposed device exceeds the noise immunity of the known devices. Invention Formula An analog-to-digital converter containing two small-sized parallel analog-to-digital converters, the first input of the first small-sized parallel analog-to-digital converter is connected to the common bus directly, and the first input of the second small-size parallel analog-to-digital converter is connected via a corresponding first current-limiting element to full on the resistor, the second inputs of small-sized parallel analog-to-digital converters through the corresponding second current-limiting devices Connected to the reference voltage bus, the third inputs of small-size parallel analog-to-digital converters are combined and are the input signal bus, characterized in that, in order to improve noise immunity, the adder and comparator are entered, the first input of which is the input signal bus, the second input combined with the first input of the second small-size parallel analog-to-digital converter, the outputs of the small-scale parallel analog-to-digital converters FIG. g Compiled by A.Titov Editor I.Segl nick Tehred A.Kravchuk Proofreader S.Shekmar at. . Order P60 / 56 Edition 902 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, F-E5, 4/5 Raushsk nab. Production and printing company, Uzhgorod, st. Project, 4 connected to the corresponding information inputs of the adder, the transfer input of which is connected to the output of the switch, and the outputs of the adder are output buses.