SU1305859A1 - Digital-to-analog converter - Google Patents

Abstract

The invention relates to automation and computing and can be used in the construction of precision information-to-analog converters. The goal is to improve the accuracy and simplify the digital-to-analog converter. The digital-analog converter contains an input bus 1, a resistive divider 2 of type K-2K, made of a t-bit section of 2 high-order bits and a (Nm) -discharge section of 2 lower bits, bit switches 3, first and second output buses 4 , 5, compensating switch 6, zero potential bus 7, power supply bus 8. An increase in the accuracy and the simplification of the converter is achieved due to the optimal non-binary weighting of the resistances of the bit switches in m most significant bits. 1 Il. with S SL 00 about SP 00 CL with

Description

The invention relates to automation and computing and can be used in the construction of precision information transformers from digital to analog.

The purpose of the invention is to improve the accuracy and simplify the digital-to-analog converter.

The drawing shows a functional diagram of a digital-to-analog converter (DAC).

The DAC contains an input bus 1, an N-bit resistive divider 2 of the type R-2R, made of a g-bit section of 2 high-order bits and (N-ra) - a bit section of 2 lower-order bit switches 3, first 4 and a second 5 output busses, a compensating switch 6, a zero potential bus 7 and a power supply bus 8.

The device works as follows.

The digital code is fed to the control inputs of the bit switches 3, which, depending on the digital code, switch the information outputs of the resistive divider 2 of the R-2R type to the first 4 or to the second 5

Implementing DACs with key resistances in m higher bits within a recurrence relation, or, for example, realizing optimal nonbinary weighting in terms of higher bits (4 bits, I t) and binary devices.

At the same time, non-binary weighing of B1 | iodn1 .1m tires. The input bus 1 receives an analog signal — voltage — weighting in the remaining hectares — t which is converted in accordance with the higher bits increases the accuracy with the digital code to the analog value of the current taken from the output buses 4 and 5. The resistance of the bit switches to younger ones Nm bit - 35 key resistances in bits of bits are chosen to be equal to each other and it allows to simplify the device: the resistance of the compensating key is reduced. Reduce the number of elements and related points. execute it without addition. When switching N-m low-order compensating transistors of a series of errors, there are 40 errors in the communication circuits of the resistive divider, which are caused by the inequality of resistance of the transducer. Especially significant

for ultra-precise transducers (N: 16–18 bits), when resistive divider and analog

the i-ro switch of the RJ bit and the equivalent resistance coil

switches in bits younger than 1st

R, where i 1,2, ..., N-m. This error is made separately; the number and, accordingly, differential nonlinearity in the transition to each i-th bit is proportional to

The execution of the bit in the DAC with residual resistances, the values of which are set in accordance with the recurrence ratio,

the difference between these resistances d. and increases according to the binary law as the weight of the discharge increases until the transition to the older one with unweighted resistances.

 Improving the accuracy of the conversion is achieved by aligning the distribution of errors due to

t, e, collateral in m

older bit DACs when moving to

for each older one, I will reduce by the binary law g, - and not the values of the resistances of the keys, i.e.

4. a, - / 2, for i (N-m-H) ,,,, N. This allows within a certain range of key resistances, for example

1 yRg - 2 RO 5

increase the number of bits with weighted resistances of keys, i, e.

, and thereby transfer the maximum error introduced by the keys to the area of bits with a lower weight.

Ensuring the reduction of n to the binary law corresponds to one of the boundaries of the recurrence relation, i.e. optimal non-binary weighing:

R

(3R, - Rn / 4.

U1) -,

The second boundary corresponds to the binary weighting of the key resistances in the higher order:

RUI R / 2 Implementing a DAC with key resistances in m higher bits within a recurrence ratio or, for example, realizing optimal nonbinary weighting in terms of higher bits (4 bits, I t) and binary weighting in the remaining hectares - t most significant bits dah increases the accuracy of key resistances in bits allows to simplify the device: Reduce the number of elements and connections, i.e. execute it without additional device.

At the same time, non-binary weighed weighing in the remaining hectares - t higher bits increases the accuracy of the resistance of the keys in the bits to simplify the device: Reduce the number of elements and connections, i.e. execute it without additional 45 keys are made separately,

The execution of the bit in the DAC with residual resistances, the values of which are set in accordance with the recurrence ratio,

50 provides an increase in conversion accuracy in comparison with the known device by 1.5-2 times,

Reducing the number of elements in the resistive divider circuit

55 allows to reduce the number of switching buses and the number of contact pads on separate integrated circuits (ICs) when creating ultra-precise converters and manufacturing resistive de313

separate and analog switches This helps to reduce the area of individual ICs, improving the reliability and manufacturability of the converter. When creating monolithic DACs, non-binary weighting allows an increase in the accuracy of conversion with a constant range of values of the resistances of the bit switches and thereby also reduces the area of the IC.

Claims (1)

Invention Formula A digital-to-analog converter containing a t-bit section of the higher bits of the resistive divider type R-2R, whose input is the input busbar, (Nm) -digit section of the lower bits of the resistive divider type R-2R, where N is the number of bits to be converted code, the output of which is connected via a compensating key to the zero potential terminal, the control input of the compensating key is connected to the bus and the power supply terminal, N bit switches, the analog inputs of which are connected to the corresponding information outputs with Ktsiy resistive divider type R-2R, the first outputs of the bit switches are combined and are the first output bus, the second outputs of the bit switches are combined and are the second output bus, the control inputs of the bit switches are the corresponding buses of the convertible code , bit switches m high order bits I.Nikolaychuk 1A65 / 55 Compiled by V. Pershikov Tehred A. Kravchuk To Under Circulation 902 VNIIPI USSR State Committee for Inventions and Discoveries 4/5, Moscow, Zh-35, Raushsk nab. 113035 Production and printing; Enterprise, Uzhgorod, Projecto st., 4 resistive-weighted, and the values of the resistive switches of the low-order bits (Nm), the compensating key and the low-order switch of the lower-order m higher-order bits are chosen to be equal to each other, in order to improve the accuracy and simplify the converter; This section of the higher-order bits of the resistive divider type R-2R is connected to the input of the (Nm) -discharge section of the lower p & res of the resistive divider type R-2R, while the values of the weighted resistances of the bit switches m starpth bit rows are selected in accordance with a recurrence relation "U. (3Ri - R) 4 l de R, R (N - m + l), ..., N, conversion bit number (i N for the most significant bit); bit switch impedance in i-M bit dej equivalent reduced resistance of bit switches in bits lower than i-ro R;) / 4 key. Corrector EtPofflKo Subscription