SU1474839A1 - Monitor of dynamic parameters of anlog-to-digital converter - Google Patents

Abstract

The invention relates to instrument engineering of measuring equipment and can be used to control the differential nonlinearity at a high frequency of the input signal of high-speed analog-digital converters, as well as to check the control during their mass production. The invention improves the control performance and expands the field of application due to the fact that a pulse shaper, a digital comparator, an RS trigger are entered into a device containing a frequency divider, a register, a delay element, a digital-to-analog converter, a clock generator, a sinusoidal voltage generator. phase comparator, reference code block, coincidence pulse generator, single pulse generator, code counter, two comparators, and a switch. At the same time, the ratio of the frequency of the clock generator 6 and the frequency of the sinusoidal voltage generator 1 F _C = F _J K + ΔF makes it possible to form a stroboscopic effect (beat). The frequency stability of the generators is ensured by automatic frequency tuning. By checking the number of times the output codes of the measured ADC 2 match, the code of the block of reference codes 12 determines the differential nonlinearity. Turning on the DAC 9 makes it possible to check the measured ADC 2 by analog methods. 2 yl

Description

The invention relates to instrument engineering of measuring equipment and can be applied to control differential nonlinearity at a high frequency of the input signal of high-speed analog-to-digital converters (A / D converters) of the parallel type, as well as to conduct control during their mass production.

The purpose of the invention is to increase the productivity of control and expand the scope.

Figure 1 shows the functional scheme, the device, figure 2 - the timing diagram of its work.

The device contains a sinusoidal voltage generator 1, adjustable ADC 2, 3 pulse shaper, switch 4, register 5, 6 clock pulse generator, frequency divider 7, digital comparator 8, digital-to-analog converter (DAC) 9, RS-trigger 10, phase comparator 11, a reference code block 12, a coincidence pulse shaper 13, a single pulse generator 14, a code counter 15, first 16 n second 17 reference sources. voltages, first 18 and second 19 comparators, first 20 and second 21 keys, first 22 and second 23 integrators, delay element 24.

The device works as follows.

one

Before starting work, the first and second output buses are connected to the corresponding inputs of the A / D converter 2, the outputs of which are connected to the input bus.

The generator 1 (FIG. 1) produces a sinusoidal voltage U3, frequency f-. (Fig. 2), which is fed to the first input of the ADC being turned 2. The second input through the shaper of 3 pulses receives pulses of frequency fc from the generator 6 of clock pulses. Digital codes from the output of the A / D converter 2 are fed to the inputs of register 5. Register 5 is clocked by synchronization pulses u53m, which are received from the clock generator through a frequency divider 7 to its second input. The clock frequency is fe f-, k + if, where k is an integer, Af is small compared to f "and is chosen from the condition bf" f., Where N is the ADC 2, h 20-100.

The frequency divider 7 is designed to match the speed of data processing by a digital comparator with 8 and DAC 9 with the speed of issuing ADC codes 2. The division factor is 1 kn, where n is any number. At the first input of the A / D converter 2, during each 1st clock pulse, the torque value of the input voltage Uj varies sinusoidally with a frequency kf. RS-trigger is entered for separate measurement on the rising and falling parts of the sinusoid.

5 Yu and phase comparator 11, which prohibits the issuance of clock pulses on the ADC 2 on the rising or falling parts of the sinusoid. During each 1st clock pulse, the instantaneous value of the input voltage varies monotonously — depending on (the state of switch 4 increases or decreases. To the first inputs of register 5, digital numbers come from the ADC 2.

Thus, at the output of register 5, when measuring ADC 2, successively changing digital codes are issued. The number of occurrences of each code is proportional to the differential nonlinearity and the density function of this form of the input voltage of the ADC. For a triangular form, this function is equal to one. The number of occurrences of each code is checked by a logic device consisting of a digital comparator 8, a block 12 of the reference code, a generator 13 of a coincidence pulse, a generator

0 14 single pulses and counter 15 codes. The digital codes from register 5 are fed to the first inputs of the digital comparator 8, and the second is supplied with a code from the block 12 of the reference code.

A pulse counter, for example, which counts the coincidence pulses, can serve as the reference code block 12, for example. If the codes match, digital comparator 8 outputs the level that is fed to the first input of the shaper 13 of the coincidence pulse. For synchronization, the sync pulses from the output of the delay element 24 are received at the second input of the imaging unit 13. The number of times a match is given by the input function of each value. To do this, you can use a pulse counter with a starting number that determines the number of times

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match. This number can be entered from a memory whose address is equal to the reference code. When a given number of times the level of coincidence appears at the output of the digital comparator 8, the coincidence pulse generator 13 produces a pulse, which changes the unit code of the reference code 12 by one. In the absence of a predetermined number of coincidence times, the generator of 14 single pulses produces a pulse, which, through the coincidence pulse generator 13, changes the code of the block 12 of the reference code by one. Counter 15 codes

reads the pulses of the generator 14 single pulses.

Thus, the number of codes whose quantization step width is less than the specified number is read. From register 5, the digital code also enters DAL 9. To compensate for the delay of register 5, the DAC 9 is controlled by clock pulses through delay element 24. Thus, it remains possible to monitor the operation of A1SCH 2 by analyzing the analog signal, for example, on an oscilloscope screen.

For amplitude stability and matching the input voltage levels with a voltage reference, an auto-tuning of the amplitude and bias is introduced. The voltage from the output of the generator 1 is fed to the first input of the first comparator 18, to the second input of which is supplied a constant voltage from the first source of the reference voltage. When the voltage value of the generator 1 exceeds the value specified by the source 16 of the reference voltage, the comparator 18 is triggered. The output level of the comparator 18 controls the key 20, the output voltage of which is integrated by the integrator 22, is fed to the second input of the generator 1 and reduces the amplitude. If the amplitude of the reference voltage does not exceed, it increases. Thus, the amplitude of the input voltage of the A / D converter is automatically set. The offset of the input voltage of the A / D converter 2 is controlled by a similar circuit made up of a voltage source 17, a comparator 19, a key 21, an integrator 23. In this case, the bias voltage is set, and baseline data is 0

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second reference voltage with a lower input voltage level.

The first and second inputs of the RS flip-flop 10 receive the output levels from the comparator 18 and the comparator 19, respectively. The output pulses of the RS flip-flop 10 are phase-locked to the input voltage U-j. They arrive at the first input of the phase comparator 11, the second input of which receives pulses from the divider 7. Thus, the phase comparator indicates the phase of the input voltage relative to the clock pulses (on the races of the thawing or decreasing part of the sinusoid). A synchronous double D-flip-flop can be used as a phase comparator, (the C-input of which receives pulses from frequency divider 7, and the D-input - pulses from RS-flip-flop 10.

The device is started by setting the start code in block 12 of the reference code, say 00 ... 00. Switch 4 in this case must be in the position corresponding to the measurement on the rising part of the sinusoid of the input voltage. The frequencies of the oscillators 6 and 1 are chosen close to the limit, but to satisfy the requirement fc f-jk + & f, and Df has a sign corresponding to an increase in the codes when measured on the rising part of the sinusoid. In the coincidence pulse shaper, let the number of coincidences be equal to n. When the pulse phase from frequency divider 7 coincides with the growing part of the sinusoid, phase comparator 11 opens shaper 3 and A / D converter 2 starts operation. The register records only the output pulses of the measured ADC 2 corresponding to the 1st clock pulses. Since the stability of the generators allows the selection of a very small value, in register 5, the code 00 ... 00 must be recorded several times and digital comparator 8 must output matching levels several times. If the number of times of coincidence is not less than g, then the generator of impulse of coincidence impulses produces a pulse for shifting the code in block 12 of the reference code. Then the following code 00 ... 01 is set and also repeats until the last code 11 ... 11.

b14

If, due to the large differential nonlinearity of the ADC, some code is less than m times at the output of register 5, then the output of the driver 13 will not match the impulse, and the reference code unit 12 will stop at this code. In this case, the pulse to the reference code block 12 will arrive after the end of the period 1 / & f through the coincidence pulse generator 13 from the single pulse generator 14, which outputs short pulses with a frequency uf. At the same time, this impulse will arrive at the counter of 15 codes. After completing the calibration of the ADC 2, the counter will show the number of codes whose quantization steps are less than the norm. The first time the lower limit of quantization steps is measured, the second time - the upper limit. In this case, the first time on the counter of 15 codes, not a single code should be registered, and the second time - all codes existing for this type of ADC. The device operates similarly on the descending part of the sinusoid of the input voltage for other initial and final codes. By setting any start and end codes, you can check a part of the ADC characteristic. When measuring an ADC with a DAC 9, the meter is connected to its output. For example, an oscillograph, a rms voltmeter with filters, or others can be used as a measuring instrument. On the screen of an oscillograph, one can visually observe the nonlinearity of the ADC characteristic. A RMS voltmeter with filters can measure the signal-to-noise ratio.

Claims (1)

Claims 45 40 A device for monitoring the dynamic parameters of analog-to-digital converters, comprising a frequency divider, a register, a delay element, a digital-to-analog converter, a clock generator, and a sinusoidal voltage generator, the output of which is first the output bus of the device, whose input pin is the information inputs of the register, the outputs of which are connected to the corresponding inputs of the digital-to-analog converter. 25 45 48396 The second input is connected to the output of the delay element, the input of which is combined with the control input of the register and connected to the output of the frequency divider, the input of which is connected to the output of the clock pulse generator, characterized in that, in order to increase the performance of monitoring and expanding the field of application, pulse generator, digital comparator, RS trigger, phase comparator, reference code block, coincidence pulse generator, single pulse generator, code counter, two comparators, two sources ka support voltage, two keys, two integrators, switch, upg The 20 input input of which is a mode selection bus, the output of the sinusoidal voltage generator is connected to the first inputs of the first and second comparators, the second inputs of which are connected to the outputs of the first and second reference voltage sources accordingly, the output of the first comparator is connected to the first input of the RS flip-flop and to the input of the first switch, the output of which is connected to the input of the first integrator, the output of which is connected to the first input of the sinusoidal voltage generator, the output of the second comparator is connected to the second input of the RS flip-flop and input the second key, the output of which is connected to the input of the second integrator, the output of which is connected to the second input of the generator of sinusoidal voltage, the output of the RS flip-flop is connected to the first input of the phase comparator, the second input to torogo connected to the output of the frequency divider, and first and second outputs are connected to first and second data switch inputs, the output of which is connected to the first input of the pulse shaper and the second input of which is connected to the output of clock generator 50 pulses and the output is the second output pin, the register outputs are connected to the corresponding first inputs of a digital comparator, the second inputs of which are connected to the first outputs of the reference code block, and the output is connected to the first input of the forms, a coincidence pulse generator, the second input of which is connected to vyhr30 55 the house of the delay element, and the output of the code counter and the third input with the input of the reference code block, the home of the pulse shaper coinciding with the second output connected from the bottom, the output of the digital-to-analog pre-generator of the generator impulse-5 generator is the third output cos, whose output is connected to - tire. Ut , .1 I I I I I I I I {ШЛ $ l $ кЬ Shhhh V / x 6 blocks Zghh pr koi pbyuk Fie.2