RU1780042C - Analog-to-digital low frequency phase meter - Google Patents

Abstract

Usage: phase-measuring technique, measuring the angle of phase shift between two harmonic oscillations in the low frequency region. SUMMARY OF THE INVENTION: The device comprises input shapers.

Description

(L

with

The invention relates to a faeo measuring technique and can be used to measure the angle of phase shift between two harmonic oscillations in the low frequency region.

Known digital low-frequency phase meter 1, containing a controlled voltage divider, which is a series connection of the output circuits of two code-resistance converters, while the output resistance of one of the converters is proportional to the phase shift p, and the other is proportional to 360 ° - (p. Under this condition, the output voltage of the divider, the output of which is supplied with a constant constant voltage, is proportional to the phase shift.

The disadvantage of this device is the presence of a large number of resistors and relays - the complexity of the design of the code-to-resistance converter, as well as the dependence of the reading of the reading device on the constant voltage UQ. whose instability increases the measurement error.

Closest to the claimed is a digital low-frequency phasometer 2, using the method of finding D by phasing the time intervals At and T into constant voltages using the integrator included in the ADC, storing the received voltages in the sample-storage units, followed by finding the ratio of these voltages in the ADC of dual integration.

Such a phase meter has disadvantages. It is characterized by a large time for measuring the phase shift due to the successive conversion of At and T to constant voltage using an integrator, and the presence of an additional error due to this. that conversions of At and T to constant voltages are carried out during two periods of the signal under investigation (the first and second integration cycles), the first cycle (At transformation) begins with the arrival of the first period of the studied signal, and the second cycle (T transformation) starts with the arrival of the second period, when the oscillation frequency of the signal under study changes from period to period, an additional error may occur. In addition, the phasemeter is characterized by static norpeujHOCTb. depending mainly on the input shift and

the integrator drift and compare its device (comparator).

The purpose of the invention is to increase the speed and increase the accuracy of measurement

phase shift.

The goal is achieved. that in the proposed phase meter, the transformations of .A t and T to voltages are dried out during one period of the signal under investigation. For

To reduce the static errors of the phase meter, its structure is changed as follows. that the accuracy of the integrator mainly determines the overall accuracy of the phase shift measurement.

Figure 1 shows the structural diagram

phase meter; Fig. 2 is a voltage diagram explaining the principle of operation of a phasometer.

The phasometer contains input drivers 1 and 2. RS-trigger 3. 1K-trigger 4. DC voltage source 5, AND element 6. OR element 7. Counting triggers 8 and 9. Electronic keys 10 and 11. Inverter 12. Time selectors 13 and 14. generator 15.

counting pulses, counters 16 and 17 pulses, integrator 18, non-inverting amplifier 19. voltage limiter 20, comparator 21, digital tax converter (DAC) 22. differentiating circuits 23 and 24.

The phasometer works as follows.

The forming devices 1 and 2 generate short pulses corresponding to the transition of the signals Ui and U2 through zero from negative to positive values. At the output of the RS-trigger 3, a pulse is generated, the duration of which At corresponds to the phase interval

L / 7 (phase shift) (figure 2. Ultrasound).

With the arrival of the start pulse (Fig. 2: START) at time tn, the triggers 4.8.9 are set to the zero state. counter 17 reset to zero. Short impulse.

shaper coming from the output of 2. at time ti puts trigger 4 in a single state. This is because at the time ti, the 1K trigger 4 is in counting mode, since at the I and K inputs

there is a unit, i.e. trigger inverting output signal 8 (Fig. 2. Us). At the output of trigger 4, a pulse is generated (Fig. 2, i), which opens the time selector 13 and is enabled at the input of counter 16

the passage of counting pulses of frequency fo from the output of the generator 15. On the leading edge of the pulse of the trigger 4 to the differentiator, the circuit 23 generates a pulse, resetting the counter 16. Thus. :,

the moment the count starts, the initial state of the counter 16 is zero. At time t2, an impulse is generated at the output of element And 6 (Fig. 2, Kb), which opens the key 10. At the input of the integrator 18, a positive voltage is supplied from the output of the source 5. The voltage at the output of the integrator begins to decrease linearly (Fig. 2 . Ui7). At time ta, trigger 4 is brought into a zero state (Fig. 2, U), trigger 8 is in a single state. The inputs 1 and K of the 1K trigger 4 receive a zero level and the signals at input G do not cause a change in the state of the triggers 4 and 8 until the next start of the START signal. At time t3, the time selector 13 is closed, the number of pulses N is fixed in the counter 16:

N fo (t3-ti) fo T. (1)

where T is the period of the signal under investigation.

At the same time, the electronic switch 10 is closed and by the time tk the voltage at the output of the injector 18

1

UHHT - Y / and dt - - for U (t3 -12)

12

 -VA ..

(2)

where and is the voltage of source 5:

d is the integrator time constant: (t3-12) is the integration time interval corresponding to the phase shift A.

At time xs, the trigger 9 also switches to the single state (Fig. 2. Ug) and a pulse appears at its output, opening the time selector 14, the passage of the counting pulses from the generator 15 is allowed to the input of the counter 17 (Fig. 2. Ui4). element And 6 switches to the zero state, the TO key is closed, an output is generated at the output of the inverter 12, which opens the key 11, The voltage from the output of the DAC 22 is supplied to the input of the integrator 18

Uuan Kn-N-Uorp. (3)

where Kp is a DAC conversion coefficient 22;

Uorp - output voltage limiter 20.

It should be noted that the gain of the amplifier 19 is chosen sufficiently large, therefore, almost immediately after the integration of U in the range xs -12, the amplifier 19 enters the saturation mode (Fig. 2, Uis). The signal transfer phases by the integrator and amplifier 19 are chosen so that The saturation value Uis always has the opposite polarity to and. Use of voltage limiter 20.

in the simplest version performed on a zener diode connected to the output of amplifier 19 through a ballast resistor, which, depending on N, is converted

voltage Unan, allows you to form a voltage that serves in the subsequent integration cycle as a reference. The output voltage of the integrator after being fed to its input begins to change

in the opposite direction and by time tx reaches 0: tx

UHHT- / Unan dt 0.

(4)

t3

Solving equation (4) with respect to (tx

ta). we get

t -13 ti - and At

UtsapKp N Jorp

 - - - -(5)

T

 Dot fo

At the end of the capacity discharge of the integrator, the amplifier 19 goes out of saturation and enters the active mode. The voltage drop at the output of the amplifier 19, resulting from balancing, triggers the comparator 21 (Fig. 2, U2o) and a short pulse is generated at the output of the differentiating circuit 24 (Fig. 2. U23), which switches the trigger 9 to zero

state (FIG. 2, Ug), the time selector is closed, the number of pulses is set in counter 17

NX fo (tx - t3). (6)

Given expression (6), equation (5) takes the form

At.

and

Nx 7 --K

   N

Kp Warp

where K -g -g -.- is the general coefficient of pre1chp Uorp

education.

Choosing a value of K 3.6 p. 2.3 .... you can get the count N directly in degrees.

It should be noted that electronic

the key 11 remains closed until the start of the next conversion cycle, the integrator 18 and amplifier 19 are covered by negative feedback (OOS) through the voltage limiter and the DAC. A large gain in the DC loop on a constant current contributes to 11 maintaining the voltage at the output of the integrator, equal to the shift at the input of amplifier 19 (in the absence of a shift at the input of the integrator) until the next cycle

transformations.

Based on the foregoing, it follows that the change in the structure of the conversion allows to provide the following advantages of the claimed device, given in comparison with the prototype.

Due to the fact that the conversion of time intervals Д t and Т to constant voltage occurs during the time interval Т, i.e. during one period, an error is excluded, the occurrence of which is possible due to a change in the frequency of the signal during the measurement, thus, the phase meter allows you to determine the instantaneous value of the phase shift.

The value of the static error due to the input shift and the drift of the integrator and the comparison device is reduced due to the introduction of the next OOS from the output of the amplifier 19 to the input of the integrator.

Claims (1)

SUMMARY OF THE INVENTION A digital digital low frequency phase meter comprising a pulse counter is provided. two shapers, two electronic keys, a counting pulse generator. RS flip-flop, reference voltage source, comparator, integrator, time selector, wherein the inputs of the drivers are the inputs of the phase meter, the output of the first driver is connected to the S-input. and the output of the second one is to the R-jumper of the RS-flip-flop, the output of the reference voltage source through the first key is connected to a point combining the integrator input and the output of the second electronic key, the output of the pulse generator is connected to the input of the temporary selector. the output of which is connected to the counter input, characterized in that, in order to increase the speed and increase the accuracy of measuring the phase shift, a 1K trigger, the first and second counting triggers, an OR element are introduced into it. element And, second В | eemenny selector, in three counter. Digital-to-analog converter, voltage limiter, non-inverting amplifier, inverter, first and second differentiating circuits, the C-input 1 of the Trigger being connected to the output of the second shaper, output combines the C-outputs of the first and second countable triggers. inputs, the second temporary selector, the first differentiating chain and the second input of the element And, the first input of which connected to the output of the RS flip-flop, and the output with the second input of the first electronic key and the inverter input, the output of which is connected to the first input of the second electronic key, the input of the non-inverting amplifier is connected to the output of the integrator, and the output is connected to the inputs of the voltage limiter and comparator, the output of the limiter is connected to the input of the reference voltage of the digital-to-analog converter, the output of which is connected to the second input of the second electronic key, the output of the comparator is connected through the second differentiating circuit to the second the course of the element OR. the output of which is connected to the R-input of the second counting trigger, the output of which is connected to the second input of the first time selector, the inverting output of the first counting trigger is connected to the 1st and K-inputs of the 1K-trigger. the second input of the second time selector is connected to the output of the counter pulse generator, and the output to the input of the second pulse counter, the output bus is connected to the input bus of the digital-to-analog converter. the output of the first differentiating circuit is connected to the reset input of the second counter. The R-inputs of the 1K trigger, the first counting trigger, the first counter and the first input of the OR element are combined with the third input phase meter, input start.