JP3398402B2 - Bus monitor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a bus monitor device for monitoring a bus and collecting data on the bus. In recent years, control devices using a microprocessor (hereinafter, MPU) have become widespread in various fields.
Many of these controllers collect various types of data and perform complex control.When monitoring the control state, rather than logging all data and analyzing the control state, the transition of the data of interest Monitoring is often more efficient. For this reason, a method of monitoring only data at a specific address from among data on a bus accessed by a microprocessor (hereinafter referred to as an MPU) can be considered. Alternatively, there is a type in which 4-byte data is handled as one set of data. For example, 4-byte data of interest is updated (bus access is performed four times).
If there is a timing to capture that data on the way,
There is a possibility that a part of the acquired 4-byte data remains unupdated. For this reason, in a bus monitor device that monitors a bus of an MPU and takes in specific data, it is necessary to guarantee continuity of data over a plurality of bytes. [0004] There are a logic analyzer, an ICE (In Circuit Emulator) and the like for monitoring a bus of an MPU. Of these, the method using a logic analyzer is M
A logic analyzer is connected to the bus of the PU, the data on the bus is logged to the memory in the logic analyzer, and the contents of this memory are read out and displayed in hexadecimal or waveform to analyze the control state. However, since all data output on the bus is logged in chronological order according to the control order, the amount of data to be logged is limited depending on the memory capacity, and data of interest is extracted from the data. Has a problem that it takes time. [0005] On the other hand, the ICE replaces a circuit provided with a means for collecting data with the same operation as that of the MPU of the apparatus by using the MPU and logs data output on the bus. Like the analyzer, there is a problem that only the data of interest cannot be monitored in real time. SUMMARY OF THE INVENTION A logic analyzer,
Data collection by the ICE is inconvenient for monitoring a control device that performs complicated operations because all data is collected in time series. For this reason, it has been considered to take in only the data of the designated address from the data output on the bus of the MPU. FIG. 5 Problem (No. 1) The explanatory diagram shows a configuration diagram of one example, and the operation is as follows. That is, in the bus monitor device 52 of FIG.
If the address of the data to be monitored is set in the address setting register 42 in advance, a comparator 46 outputs a match signal when the address matches the address output from the MPU 41 of the device under test 40 to the address bus. The data currently output to the data bus is latched in the data register 47 by the coincidence signal. Since the data at this address is repeatedly output, and the value changes along with the control and is overwritten in the data register 47, the transfer unit 51 stores the contents of the data register 47 in the memory in synchronization with a sampling clock of a certain period. Write to 52. A plurality of data capture units each including one set of the address setting register, the comparator and the data register are provided. By setting an address in each of the address setting registers 42 to 45, a desired value is set in the data registers 47 to 50. The data is latched and recorded in the memory 52 by the transfer unit 51. When using such a bus monitor, the following problems are encountered. In other words, the recent MPU 41
Depending on the type or instruction, as shown in FIGS. 6 (a), (b), and (c), 4 bits in 8 bits parallel, 2 bytes continuous, 16 bits parallel, 2 bytes continuous, 8 bits parallel. If the timing of writing to the memory 52 collides with the middle of a series of data (t1) as shown in FIG. 6 (c), an accurate data bus monitoring result can be obtained. Absent. That is, at time t1, 1000H to 1002
The 3-byte data up to address H is the data that has been updated this time, but the fourth byte is the data that has been updated during the previous access. For this reason, after detecting the data output at the address 1000H, which is the first byte, it waits for the detection of the second byte, and in the same way, waits for the detection of the third and fourth bytes and transfers it to the memory 52. However, in this method, if there is no access to the address 1001H for some reason (for example, an operator setting error), the transfer to the memory 52 cannot be performed forever. As described above, when fetching a series of data continuously output by a plurality of bus accesses, it is necessary to guarantee data continuity. In view of the above problems, an object of the present invention is to provide a bus monitor device which takes in a series of data output by a plurality of accesses while ensuring continuity. In the principle diagram of the present invention shown in FIG. 1, reference numeral 61 denotes a plurality of data acquisition units, and a series of data output in time series on a bus by a plurality of bus accesses. Capture each. Reference numeral 60 denotes a timing control unit which controls the capture of data captured by the data capture unit 61. Each data capturing section 61 includes an address setting register 8 in which address data is set, a comparator 9 for comparing the set address data with address data output on the bus, and a comparator 9. 9, a data register 10 for capturing the data output on the bus when the match signal is output, an access number setting register 7 for setting the number of accesses from the captured data to the final data in a series of data, , A busy signal generator 5 that outputs a busy signal for an access time corresponding to the number of accesses set from the time of capturing data to the data register 10, and a timing controller 60 captures a series of the data. When a busy signal is being output from any of the predetermined data capturing units 61, data is retrieved from the data register 10 of the data capturing unit 61. To prohibit the Mukoto. In each data capturing section 61, the address data corresponding to the data to be captured is set in the address setting register 8, and the access number setting register 7 stores the data from the captured data to the final data in the series of data. The bus access count is set. For example, in the case of FIG. 6C, that is, when a series of data (4 bytes) is output by four bus accesses, four sets of data capturing units 61 are used, and each address setting register 8 sequentially stores 1000H to 1003H are set, and 4 in the access count setting register 7 in descending order.
The number of times of access until the last data is accessed is set as 3, 2, or 1. This allows each data capture unit
The data of the set address is captured by the data register 10 of 61, and a busy signal is output from the busy signal generating section 5 of each data capturing section 61 from the captured access time to the end of the last data access. Is done. The timing control unit 60 monitors the busy signals, and if any one of the four busy signals output from the data capturing units 61 has been output, each data capturing unit 61 4 sets of data registers in unit 61
Prohibit importing from 10. As described above, while the series of integrated data is being accessed, the fetch from the latched data register 10 is prohibited, so that the continuity of the data is guaranteed. Further, since the busy signal is released when the access for the number of times set in the access number setting register is completed, even if an operator makes a mistake in setting, there is no need to wait forever for capturing the next series of data. FIG. 2 is a block diagram of one embodiment, FIG. 3 is a block diagram of a BSY signal generator of one embodiment, and FIG. 4 is an operation time chart. The bus monitor is configured to capture (latch) any specified plurality of data from the data output on the bus. In the present embodiment, FIG.
A case in which a series of 4-byte data indicated by is latched. In FIG. 2, a first byte data capturing unit 1, a second byte data capturing unit 2, a third byte data capturing unit 3, and a fourth byte data capturing unit 4 (corresponding to the data capturing unit 61 in FIG. 1). ) Are named corresponding to the order of bytes to be latched among the 4-byte data in this embodiment, and have the same configuration. Therefore, depending on the values set in the address setting register 8 and the access number setting register 7, 4-byte data, two sets of 2-byte data,
Of course, any continuous or single data such as four different sets of byte data can be latched. In the following description, the portions of the second to fourth byte data capturing units 2 to 4 that are not shown use the reference numerals of the first byte data capturing unit 1. In the first byte data capturing section 1, reference numeral 8 denotes an address setting register, and address data input from a keyboard or the like (not shown) is set by the microprocessor MPU15. A comparator 9 compares the address data output to the address bus with the address data set in the address setting register 8, and outputs a match signal "1" when they match. Reference numeral 10 denotes a first register (corresponding to the data register in FIG. 1), which latches data output on the data bus in accordance with the coincidence signal output from the comparator 9. With the above configuration, every time the same address data as the address data set in the address setting register 8 is output on the bus, the data on the data bus at that time is overwritten on the first register 10 (latch). ) Is done. In this embodiment, if the address setting registers 8 of the first to fourth byte data capturing units 1 to 4 are set as, for example, addresses 1000H, 1001H, 1002H, and 1003H, In the first registers 10 to 13 of the first to fourth byte capturing units 1 to 4, data of addresses 1000H to 1003H accessed by the MPU (not shown) and output on the bus are latched. Reference numeral 7 denotes an access count setting register, which indicates the number of accesses from the access cycle in which data is latched by its own data capturing section to the last byte data (here, the fourth byte) of a series of target data from the keyboard. Is set. That is, the first to fourth byte data capturing units 1
As described above, when the addresses are set in ascending order in the address setting registers 8 to 4, the access number setting registers 7 respectively store 4, 3, 2, 1 (actually, Is set).
Reference numeral 5 denotes a BSY signal generating unit which generates a busy (BSY) signal for the access time set in the address setting register 7 from the data access captured by the data capturing unit. Reference numeral 10a denotes a second register. As will be described later, the timing control unit 60 (the NOR circuit 17, the AND circuit 18,
21, D-FFs 19, 20, 22 and an inverter 23), the contents of the first register 10 are transferred by the set signal output from the AND circuit 21. The content of the second register 10a is, for example, the MP signal after the set signal.
The data is read by U15 and stored in the memory 6. First register 10-13 to second register
The transfer to 10a to 13a is performed at a timing when a series of data (4-byte data) is not accessed. Therefore, for example, in the case where the set signal is output at time t1 in FIG. 6C, the set signal is delayed until time t2. FIG. 3 shows an example of the configuration of the BSY signal generator 5. Where D-FF (D TYPE flip-flop)
31 to D-FF 34 constitute the shift register 6, and the coincidence signal "1" is shifted by the address strobe.
Reference numeral 25 denotes a decoder which is configured to obtain 0 to 3 outputs with respect to the inputs of A and B as shown in the illustrated table. When the address data set in the address setting register 8 matches the data on the address bus, a match signal is output from the comparator 9 (high level "1").
Will be). When the match signal is output ("1"), JK-F
The Q output of the F35 (BSY signal, see FIG. 4) becomes "1" in synchronization with the 50 ns constant clock. Here, assuming that [A, B] of the access number setting register 7 is set to [0, 0], the BSY signal is output during one cycle of the address strobe. That is, normally, of the three inputs of the NAND circuit 26, the match signal (the fourth byte match signal in FIG. 4) is "0", the output of the decoder 25 is "1", and * Q is "1". However, when the match signal becomes “1”, the output of the NAND circuit 26 changes from “1” to “0”.
And * Q becomes "0" at the fall of the address stove, so that the output of the NAND circuit 26 becomes "1" again. Since the outputs of the decoders 25 of the NAND circuits 27 to 29 are "0", the outputs of the NAND circuits 27 to 29 are always "1". As a result, the AND circuit 30 outputs "0" with a time width corresponding to the Q output of the D-FF 26.
Is output and JK-FF 35 is cleared. This result JK-FF
Is "0". That is, when [0, 0] is set in the access count setting register 8 and the address of the fourth byte is set in the address setting register 8, the fourth byte BSY signal of FIG. 4 is generated. Similarly, when [0, 1] is set in the access count setting register 7, the Q output of the D-FF 31 becomes "1" after counting one address strobe, and the D output at the next address strobe becomes "1". -Q output of FF32 is changed from "0" to "1"
And the * Q output changes from "1" to "0", at which point JK-FF 35 is cleared. As a result, the BSY signal is output during two cycles of the address strobe. In the present embodiment, it is the BSY signal of the third byte in FIG. In this way, [1,0],
By setting [1,1], respectively, the address strobe for three cycles (the second byte BSY signal in FIG. 4) and the four cycles of the BSY signal (the first byte BSY in FIG. 4)
Signal) respectively. As a result, 4-byte data, for example, consecutive addresses 1000H, 1001H, 1002H,
When latching the data of 1003H, the addresses 1000H, 1001H, and 10H are respectively stored in the address setting registers 8 of the first to fourth byte data capturing units 1 to 4.
02H, 1003H, and [1,1], [1,0], [0,1],
[0,0] is set. Thereby, for example, the command MOVE. When L DO, 1000H (for microprocessor 68008) is issued, address 100
Data is output together with the address in the order of 0H, 1001H, 1002H, and 1003H, and is sequentially latched in the first registers 10 to 13 (for example, at the rising edge of the data strobe in FIG. 4). The fourth byte BSY signal will be output. During the period when the BSY signal is being output,
When 4 bytes of BSY signal is output because 4-byte data is being latched in the first registers 10 to 13 and cannot be guaranteed as one lump. Is the second register 10
Prohibits (delays) set signal output to a to 13a. Then, after all the BSY signals are released, a set signal is output, and thereafter, the set signal is transferred to the memory 16 or displayed on a display unit (not shown). That is, the second register 10
When any of the first to fourth byte BSY signals is output when the sampling clock (inherited from the original set signal, access to 1000H to 1003H) that instructs transfer to a to 13a is output Waits for the output of the set signal until all the BSY signals are released. The following is a description of the timing controller (timing controller 60 in FIG. 1). 17 is a NOR circuit, in which the BSY signal is all "
When the sampling clock is input, the D-FF 22 sets the Q output to "1", but when the NOR circuit 17 becomes "1", the AND circuit outputs "1". "1" is output. This "1" output is output as "1" to the AND circuit 21 with a delay of a constant clock (50 nS) × 2 hours by the D-FF 19 and D-FF20. As a result, the D-FF 22 is cleared, that is, the sampling clock is output from the AND circuit 21 after the first to fourth byte BSY signals are all "0" and delayed by two constant clocks. This signal is output as a set signal and transfers data from the first register 10 to the second register 10a to the second register 10a to 13a.
Since four bytes of data are simultaneously set in a outside the access period as a unit, data continuity is guaranteed. In the above embodiment, the data is temporarily transferred to the second registers 10a to 13a by the set signal.
Needless to say, the contents of the first registers 10 to 13 may be directly read out and transferred to the memory 16 by U15. As described above, the bus monitor of the present invention is configured so that a series of data output on the bus is latched in a register by addressing, and a series of data is accessed. During this time, the data latched in the register is prohibited from being taken in, so that there is an effect of guaranteeing the continuity of a series of data divided and accessed over a plurality of bytes.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a principle diagram of the present invention; FIG. 2 is a configuration diagram of one embodiment; FIG. 3 is a configuration diagram of a BSY signal generation unit of one embodiment; FIG. 4 is an operation time chart; FIG. 5 is an explanatory diagram of a problem (No. 1). FIG. 6 is an explanatory diagram of a problem (No. 2). [Explanation of symbols] 1 First byte data capturing unit 2 Second byte data capturing unit 3 Third byte data capturing unit 4 Fourth Byte data capturing unit 5 BSY signal generating unit 6 Shift register 7 Access count setting register 8 Address setting register 9 Comparator 10-13 First register 10a-13a Second register 15 Microprocessor MPU 16 Memory 17 NOR circuit 18 AND circuit 19, 20 D
-FF 21 AND circuit 22 DF
F23 Inverter 25 Decoder 26-29 NAND circuit 30 AND circuit 31-34 D-FF circuit 35 JK-
FF 40 Device under test 41 Microprocessor MPU 42-45 Address setting register 46 Comparator 47-50 Register 51 Transfer unit 52 Data memory 60 Timing control unit 61 Data acquisition unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G06F 13/00 301 G06F 11/30 320 G06F 11/34

Claims (1)

(57) Claims 1. A plurality of data capturing units (61) each capturing a series of data output on the bus by a plurality of bus accesses, and a plurality of data capturing units (61) captured by the data capturing unit. A bus monitor device having a timing control unit (60) for controlling the capture of data, wherein each data capture unit (61) includes an address setting register (8) in which address data is set, and a A comparator (9) for comparing the address data with the address data output on the bus; and a data register (10) for capturing the data output on the bus when the match signal is output from the comparator. ), An access number setting register (7) for setting the number of accesses from the data to be captured to the final data in the series of data, and the access number set from the time of capturing the data in the data register. Busy signal generating section for outputting a busy signal during the number of times of access time (5)
The timing control unit (60) captures the data assigned to itself out of the series of data output on the bus, and captures the series of data. When a busy signal is output from any of the predetermined data capturing units (61), it is characterized in that it is prohibited to capture data from the data register of the predetermined data capturing unit. Bus monitor device.