JPS6216691Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprocessor analyzer that can temporally correlate and analyze two or more series of operations that operate asynchronously.

In recent years, with the spread of microprocessors (hereinafter simply referred to as μP),
Many P-applied devices are being produced. The μP analyzer is used to find and analyze defects in the software and hardware of such μP application equipment. Some such μP analyzers are capable of simultaneously sampling the operation of the μP and the operation of peripheral circuits. In this case, the operation of μP and the operation of the peripheral circuits may or may not be synchronized. However, when the operation of the μP and the operation of the peripheral circuits are asynchronous with each other, in the conventional device, since the memories of both series are independent, information regarding the temporal connection between the two series cannot be obtained.

FIG. 1 is a diagram showing sample states of two series of data in a conventional device. In the same figure, S ₁ is μP
_S2 shows the operation sequence of the peripheral circuit.
TP ₁ and TP ₂ indicate the trigger points of the series S ₁ and S ₂ , respectively. In the case of series S ₁ , program data is traced after a certain fixed time delay from TP ₁ . The shaded area A is the trace area. For series S ₂ ,
Program data within a certain time width before and after TP ₂ is traced. The shaded area B is the trace area. In this way, in the μP analyzer that can analyze two series of program data, a trigger point can be set for each series. However, as described above, there is no temporal connection between trace areas A and B. That is, information regarding the timing of occurrence of the trigger point cannot be obtained.

The present invention was developed in view of these points, and includes providing a memory for each series to store two or more series of digital data that operate asynchronously, and storing the memory address for at least one series. By providing an address counter for data acquisition, temporal information between each series can also be stored at the time of data acquisition, thereby realizing a μP analyzer with powerful data analysis ability. Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a diagram showing the operating principle of the device of the present invention. In the figure, S ₁ is the first series, and S ₂ is the second series. Moreover, the horizontal axis is a time series. Here, the S ₁ series can be considered as a series related to the operation of the μP described above, and the S ₂ series can be considered as a series related to the operation of the peripheral circuit. The triangular symbol above each series indicates a trigger point. As shown in the figure,
The operations of the _S1 series and the _S2 series are asynchronous. Therefore,
As mentioned above, if each series is sampled independently, the captured data will be completely independent for each series, and no temporal information will be obtained. Therefore, as shown in the figure, when sampling is performed at the trigger point TP ₃ at an arbitrary time T ₁ on the S ₁ series, the address of the S ₂ series is also stored at the same time. In this way, the memory of the S ₁ series has S ₂
The address at the time of sampling the series is stored. Therefore, there is a temporal connection between the S ₁ series data and the S ₂ series data. That is,
It becomes possible to temporally link and analyze the data of the S ₁ series and the data of the S ₂ series.

FIG. 3 is an electrical connection diagram showing one embodiment of the memory storage section of the device of the present invention. In the same figure, 1
is a memory that stores the first series of sampling data. DB ₁ is a data bus that carries data to the memory. CP ₁ is a data write pulse to memory 1. 2 is a memory that stores the second series of sampling data. DB ₂ is
This is a data bus that carries data to the memory.
CP ₂ is a data write pulse to memory 2. 3 is an address counter that counts the write pulses. The output of the counter is input to the memory 1 as data. The operation of the circuit configured in this way will be explained below.

The output of the counter 3 is input to the memory 1 along with the first series of data. Therefore, when the write pulse CP ₁ is input to the memory 1, the data on the data bus DB ₁ and the output of the counter 3 are stored in the memory. By the way, the output of counter 3 is the second
is the count value of the series of write pulses CP ₂ . Therefore, the output of the counter 3 indicates the address of the second series of memory 2. That is, when data is sampled at the first series of trigger points, the memory 1 stores not only the data but also the memory address of the second series at the time of sampling.

As a result of storing the memory addresses of the second series in the memory of the first series in this manner, it is possible to recall the data at the corresponding point in time of the second series as needed when analyzing the data of the first series. Therefore, data analysis ability is greatly improved. In the above explanation, 2
Although the case of series has been explained, it goes without saying that it is not necessary to limit the number of series to two series. The present invention can be similarly applied to three or more series. In this case, it is necessary to increase the number of counters according to the number of series. For example, if the system is configured as a four-line system, three counters will be required. These counter outputs are then input to the first series of memories 1, and are simultaneously written into the memory by the write pulse _CP1 .

As explained above in detail, according to the present invention, a memory for storing two or more series of digital data that operates asynchronously is provided for each series, and an address counter that stores the address of the memory for at least one series is provided. By providing this, it is possible to realize a μP analyzer that can also store temporal information between each series at the time of data acquisition, and has a powerful data analysis ability.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the operation of the conventional device, and FIG. 2 is a diagram showing the operating principle of the device of the present invention. FIG. 3 is an electrical connection diagram showing one embodiment of the memory storage section of the device of the present invention. 1, 2...Memory, 3...Address counter.

Claims (1)

[Scope of utility model registration request] In a microprocessor analyzer that reads two or more series of digital data that operate asynchronously into a memory provided for each series and analyzes the data, an address counter for storing the address of the memory is provided for at least one of the series. 1. A microprocessor analyzer, characterized in that the contents of the address counter are simultaneously stored when sampling digital data in different series.