JPH07111353B2 - Moving average device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to an apparatus for analyzing various time-series signals including an abnormal signal value, and a signal value of an analysis section having a constant time width with respect to a certain time of the time-series signal. In an apparatus that performs analysis using, the time-series signal of the period during which analysis is permitted is integrated at each time, the integrated value is stored in two memories at each time, and the analysis section of each time is used as a read address of the memory. The time average data corresponding to is read out, two integrated value data are read out, and the moving average value is output by performing an operation on the data.

TECHNICAL FIELD The present invention relates to a moving average device in a device that analyzes various time-series signals.

Examples of time-series signal analysis devices include ultrasonic diagnostic devices, radars, and various other measuring devices.

[Prior Art] Various time-series signal analyzers include, as a signal analysis method, an average value of data in a certain analysis section such as a moving average, which is used as a function of time.

For example, as shown in FIG. 5A, the time series signal y
The sample value of (t) for each minute time is obtained, and the moving average for the time t to be analyzed is calculated using the values of the start point and the end point of the time interval width T centered on the time t. . In other words, the signal value from t ₁ to t ₂ is added (integrated) to the time T around T / 2 hours with respect to t in FIG.
The moving average is obtained by dividing by.

In this case, since the analysis section length is constant, it was relatively easy to obtain the moving average at each time.

However, when a component such as noise that is unnecessary for analysis appears in the time-series signal, there is an increasing demand for analysis without using the signal value of the time when such a signal is included.

As a response to this, as shown in (b) of FIG. 5, a binary analysis permission signal that takes a value of “0” when the unnecessary signal component is included and takes a value of 1 when it is not included There is a method in which a moving average that is obtained from the original time-series signal by preprocessing and that is not affected by noise or the like is obtained from the analysis permission signal and the original time-series signal. The calculation will be described with reference to (c) of FIG. 5. Since only the value of the time-series signal y in the period in which the analysis permission signal w is 1 is calculated as the moving average, Create an intermittent signal from (a) and (b). Then, for each time, the average value of the section before and after T / 2 hours is obtained, but for that purpose, the period in which the analysis permission signal is 0 cannot be included in the time of T / 2. This is because if the period is included, the number of data varies and the calculation result varies unnaturally greatly depending on the time position.

As a result, when the moving average for time t in Fig. 5 (c) is calculated, the time t ₁ before T / 2 time is the starting point of the calculation, and the signal waveform during the time T / 2 after that is the starting point. The value becomes 0 after t / 4 hours (t ₃ ) from t, and the signal data from the time when the signal next rises (t ₄ ) to t ₂ after T / 4 hours should be the calculation target. The number of data becomes constant at.

Although no known conventional example is known as a device for performing such calculation of an analysis section and moving average calculation based on the section data, the configuration shown in FIGS. 4 (a) and 4 (b) is used. Conceivable.

In FIGS. 4 (a) and 4 (b), 30 is a counting circuit, 31 is a memory, and 32 is an MPU (microprocessor unit).

First, the counting circuit 30 shown in FIG. 4 (a) counts the clock signal CLK and supplies the address input of the memory 31 with the data corresponding to each moment as its output. Therefore, memory 31
Indicates that the analysis permission signal shown in Fig. 4 (b) at 1,
The state of 0 is sequentially stored at each address (time position).
Next, as shown in FIG. 4B, the start time t ₁ and the end time t ₂ of the analysis section corresponding to the output time t are obtained using the MPU 32. In that case, the analysis permission signal is examined from the time t toward the direction of the positive time and the direction of the negative time, and the time when the sum of the times when the value of the analysis permission signal is 1 is T / 2 is searched. Then, the moving average of the above time-series signal is calculated.

[Problems to be solved by the invention]

As described above, in the conventional method, at least T times of memory access and addition processing are required to determine the analysis interval for each output time. Therefore, if the data length is N, at least N × T times. Memory access and addition are required.
Further, although the moving average is calculated for the time-series signal when the analysis permission signal is 1 after the calculation of the analysis section, the time required for these processes becomes large and the problem that real-time processing is difficult occurs. there were.

[Means for solving problems]

The present invention provides an apparatus for analyzing various time-series signals including abnormal signal values, in an apparatus for performing analysis using signal values in an analysis section having a constant time width for a certain time of the time-series signal, The time series signal of the period for which is permitted is integrated for each time, the integrated value is stored in each of the two memories at each time, and the time data corresponding to the analysis section of each time is given as the read address of the memory. The data of the integrated value is read, and the moving average value is output by performing an operation on the data.

The principle configuration of the present invention is shown in FIGS. 1 (a) and 1 (c).
And FIG. 1 (b) and FIG. 1 (d) are diagrams for explaining the respective operations.

In FIGS. 1A and 1C, 10 is a multiplication circuit for multiplying the time series signal y by the analysis permission signal w, 11 is an integration circuit, 112 is a register, 13 and 14 are the memory 4 and The memories 5 and 15 represent a counting circuit that counts the clock signal CLK, and 16 represents the time of the start point of the analysis section T for each analysis time t.
An analysis interval calculation circuit that outputs t ₁ and the end time t ₂ in real time (this circuit relates to the invention of another application on the same day as the present invention, the contents of which will be described later), 17 is the output of the memory 4 Represents an arithmetic circuit for calculating the difference between the numerical value of 1 and the numerical value of the output of the memory 5, and 18 represents a division circuit for dividing the output of the circuit 17 by the value of the time T.

[Operation] In FIG. 1 (a), the multiplication circuit 10 receives the time series signal y and the analysis permission signal w from terminals 100 and 110 as shown in (c) and (b) of FIG. 1 (b). Multiplication is performed, and the multiplication result at each time is given to the addition circuit 111 in the integration circuit 11 each time, and is added to the output of the register 112 that holds the addition result up to the previous time to perform integration. The output of the integrating circuit 11 is sequentially stored in the two memories 4 and 5 by using the count value of the counting circuit 15 that counts the clock signal (a value representing time) as an address. As a result, the memories 4 and 5 are shown in FIG.
As shown in (A) of, the integrated value of the signals w and y is stored at each address.

After the data is stored in the memories 4 and 5, the data is read by the configuration of FIG. 1 (c).

That is, for each time t, the analysis section calculation circuit 16 determines the time t ₁ and t of T / 2 hours before and after the time when the analysis permission signal is 1.
Output ₂ Then, the integrated values at the times t ₁ and t ₂ are output from the memories 4 and 5 as shown in (a) of FIG. When the difference between these two outputs is calculated in the arithmetic circuit 17,
The resulting numerical value is a value obtained by adding the areas of the hatched portions indicated by A, B, and C in FIG. 1 (d).

Next, the output of the arithmetic circuit 17 is divided by the value of the time width (T) of the analysis section in the division circuit 18 to obtain the moving average.

[Embodiment] FIG. 2 shows the configuration of an embodiment of the present invention.

In the figure, 20 is a multiplication circuit for multiplying the time-series signal y and the analysis permission signal w, 21 is an integration circuit composed of an addition circuit 211 and a register 212, 23 and 24 are memory 4 and memories 5 and 25, respectively. Represents a counting circuit that counts the clock signal CLK, 2
6 to 29 and the circuits associated therewith constitute the analysis interval calculation circuit of FIG. 1 (c), 26 is a counting circuit for integrating the time when the analysis permission signal is 1, 27 is the data of the circuit 26 of the counting circuit. Memories 1, 28, and 29 that store each time output as an address represent memories 2 and 3 that store the time output of the counting circuit 25 as data and the output of the counting circuit 26 as an address, and 40 is a positive / negative code conversion. A circuit, 41 is a timing control circuit for generating a clock signal 220, a clear signal 230 and a read / write signal (R / W) for each of the memories 1 to 5, 42 is an arithmetic circuit, 43 and 44 are addition circuits, and 45 to 48 are Represents a switching circuit.

First, the time series signal y and the analysis permission signal w of the terminals 200 and 210
An operation of inputting, processing a signal, and accumulating data in association with time will be described.

At the time of data storage operation, a write control signal is supplied to the memories 1 to 5 from the timing control circuit 41, the switching circuits 45 to 48 are set to the illustrated state, and the adding circuits 43 and 44 are added.
The input value from the switching circuit 48 is “0”.

The analysis permission signal w is multiplied by the multiplication circuit 20, the integration circuit 21 sequentially performs integration, and the content thereof is stored in the memories 4 and 5 as the address (time data) of the counting circuit 25 at each time. This is as described in the description of FIG. 1 (a) and FIG. 1 (b).

Simultaneously with this operation, the analysis section calculation circuit also operates, which will be described with reference to FIG.

When a binary analysis permission signal of 1,0 as shown in (b) of FIG. 3 is input to the counting circuit 26, the counting circuit 26 receives it at the ENABLE terminal, and only when the signal value is 1, the clock signal 220 The input is received and counting (integration of time) is performed, and the counting circuit 25 sequentially counts the clock signal 220 and outputs time data from its output line 250.

On the other hand, in the memory 1, the memory 2, and the memory 3, data is written every time (each clock), and the memory 1
Is stored with the output of the counting circuit 26 as a data input and the output of the counting circuit 25 as an address.
Is stored as a data input, and the output of the counting circuit 26 is stored as an address.

In this way, as shown in FIG.
The data is stored in 3 respectively.

Next, the operation of reading the accumulated data and calculating the moving average in real time will be described.

In this case, the memories 1 to 5 receive the read control signal from the timing control circuit 41, the switching circuits 45 to 48 are set at the positions opposite to those shown in the drawing, and the adding circuits 43 and 44 are fed from the switching circuit 48 respectively by minus. Receives T / 2 and the value of T / 2 as one input.

First, the operation of the analysis section calculation circuit will be described. The output of the counting circuit 25 for counting the clock signal 220 (representing the time t)
Is used as an address to read the data in the memory 1. As shown in (c) of FIG. 3, the output data of the memory 1 is the count value of the time when the analysis permission signal is 1 for the address of t, and the data of this time t corresponds to T / 2 time. When the data to be supplied is supplied from the switching circuit 48, the value corresponding to the time T / 2 is added to the value of the time t in the adding circuit 44, and the result is used as an address to access the memory 3 and the result is shown in FIG. As shown, the time data representing t ₂ is output from the output terminal 280.

At the same time, the address at time t is added by the adder circuit 43 and the data corresponding to the negative sign T / 2 time is added by the code conversion circuit 40, and the result is read as the address of the memory 2 and the third value is read. Time data representing t ₁ is output from the output terminal 290 as shown in (c) of the figure.

When the time data representing the analysis intervals from the memories 2 and 3 are received as addresses in the memories 4 and 5, respectively, and read out, the integrated values at the times t ₁ and t ₂ are output. c) and FIG. 1 (d) have already been described.

Then, the integrated value at time t ₁ is calculated from the integrated value at time t ₂ by an arithmetic circuit.
As described in FIGS. 1 (c) and 1 (d), it is possible to obtain the moving average by subtracting at 42 and dividing the result by T (analysis section) in a division circuit not shown. is there.

[Effects of the Invention] As described above, according to the present invention, for a time-series signal including a signal section unsuitable for analysis, calculation of a moving average of an analysis section in which the number of valid data is constant can be substantially performed. It can be obtained in time, and higher speed can be achieved as compared with the conventional example.

[Brief description of drawings]

1 (a) to 1 (d) are views for explaining the principle configuration and operation of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is a configuration diagram of the embodiment. FIG. 4 is an explanatory diagram of the operation of the analysis section calculation circuit, FIG. 4 is a configuration diagram of a conventional example, and FIG. 5 is an explanatory diagram of the principle of moving average calculation of time series signals. 1 (a) and 1 (c) 10: Multiplying circuit 11: Integrating circuit 13, 14: Memory 4, Memory 5 15: Clock signal counting circuit 16: Analysis interval calculation circuit 17: Arithmetic circuit 18: Division circuit

Claims (1)

[Claims] 1. A moving average in a device for analyzing a time-series signal (y) including a time section in which analysis is prohibited by using signal function values of a predetermined time section (T) before and after each analysis target time. A device, which is an analysis permission signal (w) obtained from the time series signal (y)
Means (10) for multiplying the time series signal (y) with the time series signal (y), means (11) for integrating the output of the multiplication means, and time counting means (15)
And the first and second memories (13, 13) for storing the output of the time counting means as an address and the output of the integrating means as data.
14) and means for calculating time data at the start and end points of the analysis section (1
6) is further provided, and the start point and end point data of the analysis section calculation means are given and read as addresses of the first and second memories, respectively, and the difference between the outputs of the first and second memories is detected and moved. A moving average device comprising an arithmetic circuit (17, 18) for outputting an average value.