JPH06124245A - Bus monitoring device - Google Patents

Abstract

PURPOSE:To guarantee the continuity of data in the case of fetching the series of the data outputted on a bus by the plural times of access. CONSTITUTION:Plural data acquiring parts 61 for respectively acquiring the series of the data outputted on the bus and a timing control part 60 for performing the fetching control of the data acquired by the data acquiring parts 61 are provided. The respective data acquiring parts 61 compares an address set at an address setting register 8 with the address outputted on the bus, acquires the data on the bus to a data register 10 at the time of coincidence and also outputs busy signals during the period of time from data acquiring time to the access completion of the series of the data based on the contents of an access time setting register 7. The timing control part 60 prohibits data fetching from the data acquiring parts 61 when any of the plural data acquiring parts 61 for acquiring the series of the data outputs the busy signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improved bus monitor device for monitoring a bus and collecting data on the bus.

In recent years, control devices using a microprocessor (hereinafter referred to as MPU) have become widespread in various fields.
Many of these control devices collect various types of data and perform complex control.When monitoring the control status, rather than logging all data and analyzing the control status, the transition of the data of interest Often it is more efficient to monitor. For this reason, a method of fetching and monitoring only the data of a specific address from the data on the bus accessed by the microprocessor (hereinafter referred to as MPU) is conceivable. Alternatively, there is one that handles 4-byte data as one aggregated data, and for example, the 4-byte data of interest is updated (4 bus accesses are performed).
If there is a timing to take in the data in the middle,
It is possible that part of the captured 4-byte data will remain unupdated.

Therefore, in a bus monitor device that monitors the MPU bus and fetches specific data, it is necessary to guarantee the continuity of data over a plurality of bytes.

[0004]

2. Description of the Related Art Logic monitors, ICEs (In Circuit Emulators), etc. are used to monitor the bus of an MPU. Of these, the method using the logic analyzer is M
The control state is analyzed by connecting a logic analyzer to the PU bus, logging the data on the bus to the memory in the logic analyzer, and reading the contents of this memory and displaying in hexadecimal or waveform. However, since all the data output on the bus according to the control order is logged in time series, the amount of data to be logged is limited depending on the memory capacity, and the more interesting data is extracted from this data. Has the problem that it takes time and effort.

On the other hand, the ICE replaces a circuit that has the same operation as that of the MPU of the apparatus and has a means for collecting data with the MPU and logs the data output on the bus. Similar to the analyzer, there is a problem that only the focused data cannot be monitored in real time.

[0006]

[Problems to be Solved by the Invention] Logic analyzer,
Data collection by ICE is inconvenient for monitoring a control device that performs complicated operations because all data is collected in time series.

Therefore, it has been considered to fetch only the data of the designated address from the data output on the bus of the MPU. FIG. 5 is a schematic diagram showing an example of the problem (No. 1) and its operation is as follows.

That is, in the bus monitor device 52 of FIG.
When the address of the data to be monitored is set in the address setting register 42 in advance, when the address and the address output from the MPU 41 of the device under test 40 to the address bus match, the comparator 46 outputs a match signal, The data output to the data bus at that time is latched in the data register 47 by the coincidence signal. The data of this address is repeatedly output, and its value changes with control and is overwritten in the data register 47. Therefore, the transfer unit 51 stores the contents of the data register 47 in synchronization with the sampling clock of a certain fixed cycle. Write in 52.

A plurality of sets of data capturing units, each of which includes the address setting register, the comparator, and the data register, are provided. By setting an address in each of the address setting registers 42 to 45, desired data registers 47 to 50 are set. The data is latched and recorded in the memory 52 by the transfer unit 51.

When using such a bus monitor, the following problems are encountered. In other words, the recent MPU41
Depending on the type or instruction, as shown in FIGS. 6 (a), (b), and (c), 8-bit parallel, 2-byte continuous, 16-bit parallel, 2-byte continuous, 8-bit parallel, 4 It may be output as consecutive bytes, and if the timing of writing to the memory 52 hits the middle (t1) of a series of data as shown in Fig. 6 (c), accurate data bus monitoring results can be obtained. Absent. That is, at time t1, 1000H to 1002
The 3-byte data up to address H is the data updated this time, but the 4th byte is the data that has been updated at the time of the previous access.

Therefore, after detecting the data output at address 1000H, which is the first byte, the second byte is waited for, and similarly, the third byte and the fourth byte are waited for before being transferred to the memory 52. However, in this method, if there is no access to the address 1001H for some reason (for example, an operator setting error), the transfer to the memory 52 cannot be performed permanently. As described above, in the case of fetching a series of data continuously output by a plurality of bus accesses, it is necessary to guarantee the continuity of the data.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a bus monitor device that captures a series of data output by a plurality of accesses while ensuring continuity.

[0013]

In the principle diagram of the present invention shown in FIG. 1, a plurality of data capturing units 61 capture a series of data output on a bus in a time series by a plurality of bus accesses. . A timing control unit 60 controls the capture of the data captured by the data capturing unit 61.

Each data capturing section 61 includes an address setting register 8 in which address data is set, a comparator 9 for comparing the set address data with the address data output on the bus, and a comparator. A data register 10 for capturing the data output on the bus when the coincidence signal is output from 9, and an access count setting register 7 for setting the access count from the capture data to the final data in the series of data. , A busy signal generator 5 for outputting a busy signal and an access time corresponding to the set number of accesses from the time of capturing data to the data register 10, and the timing controller 60 captures a series of the data. When the busy signal is output from any of the predetermined data capturing units 61, the data is acquired from the data register 10 of the data capturing unit 61. To prohibit the Mukoto.

[0015]

In each data capturing section 61, the address data corresponding to the data to be captured is set in the address setting register 8, and the access count setting register 7 is set in the access count setting register 7 from the capture data to the final data in the series of data. Is set. For example, in the case of FIG. 6C, that is, when a series of data (4 bytes) is output by four times of bus access, four sets of the data capturing units 61 are used, and the address setting registers 8 are sequentially set to 1000H to 1003H is set, and the access count setting register 7 is set to 4 in descending order.
As in 3, 2, 1 the number of accesses until the final data bus access is set. As a result, each data capture unit
The data of the set address is captured in the data register 10 of 61, and the busy signal generator 5 of each data capturing unit 61 outputs a busy signal from the time of the captured access to the end of the access of the final data. To be done.

The timing control unit 60 monitors the busy signal, and if any one of the busy signals output from the four sets of data capturing units 61 is output, the data capturing unit 60 captures each data. 4 sets of data registers in part 61
The import from 10 is prohibited.

As described above, since the fetching from the data register 10 for latching is prohibited while the series of collected data is being accessed, the continuity of the data is guaranteed. Further, since the busy signal is released when the access for the number of times set in the access number setting register is completed, even if the operator makes a setting error, it is not necessary to permanently wait for a series of data to be generated next.

[0018]

FIG. 2 is a block diagram of one embodiment, FIG. 3 is a block diagram of a BSY signal generator of one embodiment, and FIG. 4 is an operation time chart.

This bus monitor is configured to capture (latch) a plurality of designated arbitrary data from the data output on the bus. In this embodiment, FIG. 6C is used.
The case of latching a series of 4-byte data shown in is shown.

In FIG. 2, the first byte data capturing section 1, the second byte data capturing section 2, the third byte data capturing section 3, the fourth byte data capturing section 4 (which corresponds to the data capturing section 61 in FIG. 1). ) Are named corresponding to the order of bytes to be latched in the 4-byte data in this embodiment, and have the same configuration. Therefore, depending on the values set in the address setting register 8 and the access count setting register 7, 4 byte data, 2 sets of 2 byte data,
Of course, it is possible to latch arbitrary continuous or independent data such as four sets of different byte data.

In the following description, the reference numerals of the first byte data capturing unit 1 are used for the portions of the second to fourth byte data capturing units 2 to 4 not shown. In the first byte data capturing unit 1, 8 is an address setting register, and address data input from a keyboard (not shown) or the like is set by the microprocessor MPU15. A comparator 9 compares the address data output to the address bus with the address data set in the address setting register 8 and outputs a match signal "1" when they match. Reference numeral 10 is a first register (corresponding to the data register in FIG. 1), which latches the data output on the data bus by the coincidence signal output from the comparator 9.

With the above configuration, every time the same address data as the address data set in the address setting register 8 is output on the bus, the data on the data bus at that point is overwritten (latch). ) Will be done.

In the present embodiment, if the address setting registers 8 of the first to fourth byte data capturing units 1 to 4 are set, for example, at addresses 1000H, 1001H, 1002H, 1003H, The data at addresses 1000H to 1003H accessed by an MPU (not shown) and output on the bus are latched in the first registers 10 to 13 of the first to fourth byte capturing units 1 to 4, respectively.

Reference numeral 7 is an access count setting register, which indicates the number of accesses from the keyboard to the last byte data (here, the 4th byte) of a series of target data from the access cycle in which the data is latched by its own data capturing section. Is set. That is, the first to fourth byte data capturing unit 1
As described above, when the addresses are set in ascending order in the address setting registers 8 to 4, the access count setting registers 7 are set to 4, 3, 2, 1 (actually, the values described below Is set).
A BSY signal generator 5 generates a busy (BSY) signal for the number of access times set in the address setting register 7 from the data access captured by the data capturing unit.

Reference numeral 10a is a second register, and as will be described later, a timing controller 60 (a NOR circuit 17, an AND circuit 18,
The contents of the first register 10 are transferred by a set signal output from the AND circuit 21 out of (21, D-FF 19, 20, 22, inverter 23, etc.). Then, the contents of the second register 10a are changed to MP
It is read by U15 and stored in the memory 6.

From the first register 10 to the second register
The transfer to 10a to 13a is performed at a timing when a series of data (4 bytes of data) is not accessed. Therefore, for example, in the case where the set signal is output at time t1 in FIG. 6C, the set signal is delayed until time t2.

FIG. 3 shows an example of the configuration of the BSY signal generator 5. Where D-FF (D TYPE flip-flop)
31 to D-FF 34 compose the shift register 6, and the coincidence signal "1" is shifted by the address strobe.
Reference numeral 25 denotes a decoder, which is configured to obtain outputs 0 to 3 for inputs A and B as shown in the table.

Now, when the address data set in the address setting register 8 and the data on the address bus match, a match signal is output from the comparator 9 (high level "1").
Will be). When the match signal is output ("1"), JK-F
The Q output of the F 35 (BSY signal, see FIG. 4) becomes "1" in synchronization with the constant clock of 50 nS.

If [A, B] of the access count setting register 7 is set to [0, 0], the BSY signal is output during one cycle of the address strobe. That is, normally, among the three inputs of the NAND circuit 26, the match signal (the fourth byte match signal in the case of FIG. 4) is "0", the output of the decoder 25 is "1", and * Q is "1". However, when the match signal becomes "1", the output of the NAND circuit 26 changes from "1" to "0".
Then, since * Q becomes "0" at the fall of the address stove, the output of the NAND circuit 26 becomes "1" again. In the NAND circuits 27 to 29, the output of the decoder 25 is "0", so the outputs of the NAND circuits 27 to 29 are always "1". As a result, the AND circuit 30 outputs "0" in the time width corresponding to the Q output of D-FF 26.
Is output and JK-FF 35 is cleared. This result JK-FF
Q output of will be "0". That is, when [0, 0] is set in the access count setting register 8 and the address of the fourth byte is set in the address setting register 8, the fourth byte BSY signal of FIG. 4 is generated.

Similarly, when [0, 1] is set in the access count setting register 7, the Q output of D-FF 31 becomes "1" after counting one address strobe, and D is output at the next address strobe. -Q output of FF 32 is from "0" to "1"
And, * Q output changes from "1" to "0", at which point JK-FF 35 is cleared. As a result, the BSY signal for two cycles of the address strobe is output. In this embodiment, it is the BSY signal of the third byte in FIG. In this way, [1,0],
By setting [1, 1] respectively, address strobes for three cycles (second byte BSY signal of FIG. 4) and four cycles of BSY signal (first byte BSY of FIG. 4) are set.
Signals) respectively.

As a result of the above, 4-byte data, for example, consecutive addresses 1000H, 1001H, 1002H,
When latching the data of 1003H, the addresses 1000H, 1001H, 10 are stored in the address setting registers 8 of the first to fourth byte data capturing units 1 to 4, respectively.
02H and 1003H are set, and [1,1], [1,0], [0,1], and
Set [0,0]. Thereby, for example, the instruction MOVE. When L DO, 1000H (for microprocessor 68008) is issued, the address 100
Data is output together with the address in the order of 0H, 1001H, 1002H, 1003H, is sequentially latched in the first registers 10 to 13 (for example, the rising edge of the data strobe in FIG. 4), and the first to the first signals shown in FIG. The fourth byte BSY signal will be output.

While the BSY signal is being output,
When 4 bytes of BSY signal are output because it is a period during which 4 bytes of data are being latched in the first registers 10 to 13 and cannot be guaranteed as one block. Is the second register 10
Disable (delay) set signal output to a to 13a. Then, after all the BSY signals have been released, a set signal is output and then transferred to the memory 16 or displayed on a display unit (not shown). That is, the second register 10
When any of the 1st to 4th byte BSY signals is output when the sampling clock (the original set signal, which is asynchronous with the access to 1000H to 1003H) that instructs transfer to a to 13a is output Waits for the output of the set signal until all BSY signals are released. The following is a description of the timing control unit (timing control unit 60 in FIG. 1).

Reference numeral 17 is a NOR circuit, and the BSY signal is all "".
When it is 0, it outputs "1". When the sampling clock is input, the D-FF 22 sets the Q output to "1", but when the NOR circuit 17 becomes "1", the AND circuit outputs "1". 1 "is output, and this" 1 "output is delayed by a constant clock (50nS) x 2 hours by D-FF 19, D-FF 20 and outputs" 1 "to the AND circuit 21, and the inverter 23 outputs" 0 ". Then, the D-FF 22 is cleared, that is, the sampling clock is output from the AND circuit 21 after the first to fourth byte BSY signals are all "0" and after a delay of two constant clocks. This signal is output as a set signal and transfers data from the first register 10-13 to the second register 10a-13a.

In this way, the second registers 10a-13
Since 4 bytes of data are simultaneously set in a as a unit outside the access period, data continuity is guaranteed.

In the above embodiment, the MP signal is temporarily transferred to the second registers 10a to 13a by the set signal.
Of course, the contents of the first registers 10 to 13 may be directly read by U15 and transferred to the memory 16.

[0036]

As described above, the bus monitor of the present invention is configured to latch a series of data output on the bus in a register by addressing, and while the series of data is accessed. Since it is configured to prohibit the fetching of the data latched in this register, there is an effect of guaranteeing the continuity of a series of data that is divided and accessed over a plurality of bytes.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment.

FIG. 3 is a configuration diagram of a BSY signal generator according to an embodiment.

[Fig. 4] Operation time chart

[Fig. 5] Explanatory diagram of problem (1)

FIG. 6 is a diagram for explaining the problem (No. 2)

[Explanation of symbols]

1 1st byte data capturing section 2 2nd byte data capturing section 3 3rd byte data capturing section 4 4th byte data capturing section 5 BSY signal generating section 6 Shift register 7 Access count setting register 8 Address setting register 9 Comparator 10 ~ 13 First register 10a to 13a Second register 15 Microprocessor MPU 16 Memory 17 NOR circuit 18 AND circuit 19, 20 D
-FF 21 AND circuit 22 DF
F 23 Inverter 25 Decoder 26 to 29 NAND circuit 30 AND circuit 31 to 34 D-FF circuit 35 JK-
FF 40 Device under test 41 Microprocessor MPU 42 to 45 Address setting register 46 Comparator 47 to 50 register 51 Transfer unit 52 Data memory 60 Timing control unit 61 Data capturing unit

Claims (1)

[Claims] 1. A plurality of data capturing units (61) for capturing a series of data output on a bus by a plurality of bus accesses, and timing control for controlling the capture of the data captured by the data capturing units. A bus monitor device having a unit (60), wherein each data capturing unit (61) outputs an address setting register (8) to which address data is set, and the set address data and the bus. A comparator (9) for comparing with address data, a data register (10) for capturing the data output on the bus at the time when a match signal is output from the comparator, and a data register in the series of data Access count setting register (7) that sets the number of accesses from the data to be captured to the final data, and the access time for the set number of access from the time of data capture to the data register Busy signal generating section that outputs between busy signal (5)
And capturing the data assigned to itself in the series of data output on the bus in the data register, the timing control section (60) capturing the series of data. When a busy signal is output from any one of the predetermined data acquisition units (61), the acquisition of data from the data register of the predetermined data acquisition unit is prohibited. Bus monitor device.