JPH0137696B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a signal storage device that stores input signals in a storage circuit in response to a clock signal.

[Background of the invention]

Signal storage devices include waveform storage devices (also known as transient digitizers, transient recorders, waveform digitizers, or digital oscilloscopes) and logic analyzers. The waveform storage device converts an analog input signal into a digital signal by an analog-to-digital (A/D) converter,
This digital signal is stored in a digital storage circuit in synchronization with a clock signal, and the stored digital signal is converted into an analog signal by a digital-to-analog (D/A) converter. Note that there is also a type of waveform storage device that stores an analog input signal in an analog storage circuit such as a CCD in synchronization with a clock signal. In addition, a logic analyzer stores logic (digital) signals in a digital storage circuit in synchronization with a clock signal, and in principle it is a waveform storage device, except for the A/D converter and D/A converter. is similar to These signal storage devices are very convenient because they can store or measure input signals even before the trigger signal is generated.

By the way, while measuring the entire input signal using these signal storage devices, there are cases where it is desired to measure in detail a portion of interest where a trigger signal is generated (for example, a portion where a transient occurs). In this case, if the clock frequency is lowered, the entire input signal can be stored in a storage circuit with limited storage capacity, but the portion of interest cannot be measured in detail. Furthermore, if the clock frequency is increased, the part of interest can be measured in detail, but measuring the entire waveform requires a very large storage capacity.

[Prior art and its problems]

In order to solve such problems, several proposals have been made in the past. One of these prior art is JP-A-57-33363 (or JP-A-58-224498).
Disclosed in the official gazette. If the signal storage device is a waveform storage device, this prior art stores the input signal I in the first storage circuit in response to the low frequency clock signal L, as shown in FIG. 1, and stores the input signal I in response to the high frequency clock signal H. I is stored in the second storage circuit. and,
The write mode of the first and second memory circuits is stopped by counting a predetermined number of clocks from the trigger time T2 (or T4) detected by the trigger circuit, and the input signal is input to the first memory circuit between time points T0 and T7. The whole is roughly memorized, and the second memory circuit is stored at time T.
The part of interest (transient) of the input signal between T1 and T6 is described in detail. Therefore, not only the entire input signal can be measured, but also the transients of the input signal can be measured in detail. However, if a transient in the input signal occurs between successive pulses of the low frequency clock signal L, the first storage circuit does not store any of this transient. Therefore, the first
Even if the input signal stored in the storage circuit is reproduced (read), it is difficult to determine which part of the entire input signal the transient corresponds to. Also, if the frequency of the clock signal L is increased to a certain extent, at least a part of the transient can be stored in the first storage circuit, but in order to store the entire input signal, the first storage circuit must have a large capacity. It won't happen.

Another conventional technique is disclosed in Japanese Patent Application Laid-Open No. 54-60543 (or Japanese Patent Application Laid-Open No. 55-154415), and the trigger time T2 is as shown in C1 (or C2) in FIG.
(or T4), the clock signal frequency is switched and the input signal is stored in the storage circuit. Therefore, it is possible to roughly measure the period before (or after) the trigger point, and also to measure the transient in detail. Furthermore, the relationship between the entire input signal and transients can be easily determined. However, if the clock signal is C1, the beginning of the transient cannot be measured, and if the clock signal is C2, the end of the transient cannot be measured.

The same problem arises when the prior art described above is applied to a logic analyzer instead of a waveform storage device.

[Purpose of the invention]

Therefore, one of the objects of the present invention is to provide a signal storage device which improves the drawbacks of the prior art mentioned above.

Another object of the present invention is to provide a signal storage device that can measure the entire input signal roughly and the entire part of interest of the input signal in detail, and can easily determine the relationship between the whole input signal and the part of interest. be.

[Summary of the invention]

The signal storage device of the present invention includes a switch that switches from a first clock signal to a second clock signal having a frequency different from the first clock signal when a trigger signal is generated, and a first write control circuit that controls the clock signal from the switch. The first one stores (writes) the input signal before and after the trigger signal is generated according to the signal.
The device includes a storage circuit, and a second storage circuit that stores an input signal in accordance with the higher frequency clock signal of the first and second clock signals. Under the control of the second write control circuit, this second memory circuit
If the frequency of the clock signal is lower than the second clock signal, the input signal immediately before the trigger signal is generated is stored, and the frequency of the first clock signal is lower than the second clock signal.
If it is higher than the clock signal, the input signal immediately after the trigger signal was generated is stored. Therefore, the first
The storage of the input signal in the storage circuit is similar to the second conventional technique described above, but the beginning or end of the part of interest of the input signal that is not stored in detail in the first storage circuit is stored in the second storage circuit in detail. remembered. Therefore, the entire input signal can be roughly measured and the entire portion of interest of the input signal can be measured in detail, and the relationship between the entire input signal and the portion of interest can be easily determined.

[Embodiments of the invention]

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 2 shows a block diagram of a first embodiment of the present invention, in which the signal storage device is a waveform storage device. An analog input signal at an input terminal 10 is supplied to an A/D converter 12 to convert it into a digital signal, and this analog input signal is supplied to a trigger circuit 14 to generate a trigger signal. The trigger circuit 14, as shown in FIG. It consists of a type flip-flop 20. Thus, trigger circuit 14 generates a trigger signal that changes from a "low" level to a "high" level when the input signal exceeds the trigger level. Note that flip-flop 20 is reset at the beginning of write mode.
The digital output signal of the A/D converter 12 is supplied to the first storage circuit 22 and the second storage circuit 24. These first and second storage circuits 22 and 24 are, for example, random access memories (RAM). The digital signals read from the first and second storage circuits 22 and 24 are supplied to a D/A converter 28 via a multiplexer (MUX) and converted back into analog signals, which are then applied to vertical deflection means of a display 30 such as a CRT. supply

The clock generator 32 includes, for example, a reference clock generator 34, which is a crystal oscillator, as shown in FIG.
, a frequency divider 36 that divides the output signal of this generator 34 to generate a plurality of divided outputs, and this frequency divider 3
MUX38 that selects one from 6 output signals.
and 40. In addition, MUX38 and 4
0 may be controlled by an external control signal, or a mechanical switch may be used instead of the MUX. The output end of MUX38 is terminal H, and MUX
The output end of 40 is terminal L, and the frequency of the clock signal at terminal H is usually higher than that of the clock signal at terminal L. The high frequency clock signal from the terminal H of the clock generator 32 is supplied to the A/D converter 12, the electronic switch 42 which is a switching means, and the second write control circuit 44, and the low frequency clock signal from the terminal L is supplied to the switch 42. supply to. The clock signal selected by the switch 42 is used by the first write control circuit 46.
and the write/read W/R control circuit 48. The switching operation of the switch 42 is controlled by a trigger signal from the trigger circuit 14, and this trigger signal is supplied to the first and second write control circuits 46 and 44 and the W/R control circuit 48.

The W/R control circuit 48 is a circuit for controlling the write mode and read mode of the signal storage device. For example, as shown in FIG. ) A programmable counter 50 that receives a trigger signal from the trigger circuit 14 at terminal E.
and a logic circuit 54 which receives the carry-out signal of the counter 50 and the logic level selected by the switch 52. Thus, when switch 52 selects write mode W, counter 50 is enabled after the trigger signal is generated and starts counting the clock signals from switch 42, and when it has counted the set number of clock pulses, it outputs a carry-out signal. occurs. This carri
W/R from logic circuit 54 by out signal
Change the control signal from "high" level to "low" level. Furthermore, when the switch 52 selects the read mode R, the W/R control signal is always at a "low" level. This W/R control signal
It controls the write and read modes of the memory circuits 22 and 24 as well as the selection operations of the MUXs 56 and 58, and further controls the first and second write control circuits 4.
6 and 44 as well as the read control circuit 60.

The first write control circuit 46 is a circuit that generates a write address signal for the first memory circuit 22. For example, as shown in FIG. The counter 62 receives the W/R control signal from the /R control circuit 48, and the latch circuit 64 latches the counted output of the counter 62 in response to a trigger signal. That is, the counter 62 counts the clock signal only during the write mode period, and supplies the count output to the MUX 56 as an address signal. Further, the latch circuit 64 latches the address signal at the time when the trigger signal is generated, and the read control circuit 64
supply to. On the other hand, the second write control circuit 44 is a circuit that generates a write address signal for the second memory circuit 24, and as shown in FIG.
A counter 66 which receives a high frequency clock signal from the clock generator 32 and a trigger signal at its inverting enable terminal, and a latch circuit 68 which latches the count output of this counter 66 in response to the trigger signal.
It is equipped with. The counter 66 counts the high frequency clock signals until a trigger signal is generated, generates an address signal, and sends this address signal to the MUX 58.
supply to. Note that the counter 66 stops counting when the trigger signal is generated. Further, the latch circuit 68 latches the address signal at the time when the trigger signal is generated and supplies it to the read control circuit 60. Note that the maximum count values of the counters 62 and 66 are determined by the capacities of the memory circuits 22 and 24, respectively.

The read control circuit 60 is connected to the first and second storage circuits 2
Issues a read address signal for 2 and 24,
It controls the selection operation of the MUX 26, and also generates a digital signal for horizontal sweeping and supplies it to the D/A converter 70. This D/A converter 70 generates a horizontal sweep signal (staircase wave) and supplies it to the horizontal deflection means of the display 30. For example, the read control circuit 60
The configuration is as shown in the figure. The arithmetic circuit 72 is, for example, a microprocessor system, and receives the W/R control signal from the W/R control circuit 48, and also receives the W/R control signal from the W/R control circuit 48.
It receives address signals at the trigger time from the second write control circuits 46 and 44 and performs various operations. This operation result is supplied to latch circuits 74 and 76, and address counters 78 and 80
Preset to. A clock generator 82 generates a read clock signal, and a counter 84 counts the clock signal to generate a digital signal for sweep. Note that the maximum count value of the counter 84 approximately corresponds to the sum of the capacities of the memory circuits 22 and 24. This digital signal is transferred to the D/A converter 70 and the arithmetic circuit 72.
supply to. Digital comparator 86 is latch circuit 7
4 and the counter 84, and if these output signals match, the D-type flip-flop 8
Clock 8. Similarly, digital comparator 90
compares the output signals of latch circuit 76 and counter 84 and clocks D-type flip-flop 92 if the output signals match. Flip-flops 88 and 92 receive a ``high'' level at their D terminals and therefore latch a ``high'' level in response to the output signals of comparators 86 and 90, respectively. Flip-flops 88 and 92 are also reset at the beginning of the read mode. Exclusive-OR gate 94 receives the Q outputs of flip-flops 88 and 92. AND gate 98 is inverter 9
6 receives the output signal of exclusive-OR gate 94 and passes the read clock signal from clock generator 82 to clock terminal C of counter 78. AND gate 100 also receives the output signal of exclusive-OR gate 94 and passes the read clock signal to clock terminal C of counter 80.
The output signal of exclusive OR gate 94 is MUX 26
The count outputs of counters 78 and 80 serve as read address signals for first and second memory circuits 22 and 24, respectively. Note that the maximum count values of counters 78 and 80 are the same as those of counters 62 and 66, respectively.
is the same as

Next, the write operation shown in FIG. 2 will be explained with reference to the timing diagram shown in FIG. A clock generator 32 generates a high frequency clock signal H and a low frequency clock signal L at terminals H and L, respectively, and the switch 4
2 selects terminal L. In addition, the input signal 10
Since the input signal is supplied to the A/D converter 12, the A/D converter 12 samples the input signal in accordance with the high frequency clock signal H and converts it into a digital signal. Since the W/R control circuit 48 is in write mode, its W/R control signal is at a "high"level;
First and second storage circuits 22 and 24 are in write mode, and MUXes 56 and 58 select first and second write control circuits 46 and 44, respectively.
The first write control circuit 46 uses a low frequency clock signal L.
A low-speed address signal is generated according to the first
The storage circuit 22 sequentially stores the digital values of the input signals when the low frequency clock signal L is generated in accordance with this low speed address signal. Further, the second write control circuit 44 generates a high-speed address signal in response to the high-frequency clock signal H, and the second memory circuit 24 stores the digital value of the input signal when the high-frequency clock signal H is generated as the high-speed address signal. The information is stored sequentially according to the information. It should be noted that both the first storage circuit 22, which performs storage using a low-speed address signal, and the second storage circuit 24, which performs storage using a high-speed address signal, receive a common A/D converter output digital signal.

At time T2, when the trigger circuit 14 detects the trigger level of the input signal, a trigger signal is generated, that is, the output signal of the trigger circuit 14 changes from a "low" level to a "high" level. Then, the switch 42 switches and selects the terminal H, so the first
Write control circuit 46 generates address signals in response to the high frequency clock signal. Therefore, the first storage circuit 22 continues to store the digital value of the input signal when the high frequency clock signal H is generated. In addition,
The latch circuit 64 of the first write control circuit 46 latches the address signal for the first storage circuit at the trigger time T2. On the other hand, since the counter 66 stops counting upon generation of the trigger signal, the second write control circuit 44 does not generate a new address signal after the trigger time T2. Therefore, the second storage circuit 24 does not store a new digital signal from the A/D converter 12, but stores the digital value of the input signal before the trigger time T2. The amount to be stored is determined by the storage capacity of the second storage circuit 24, and for example, at time T1.
and T3, the digital value of the input signal when the high frequency clock signal H is generated is stored. Since the second memory circuit 24 is an auxiliary to the first memory circuit 22, its memory capacity may be small. Further, the latch circuit 68 of the second write control circuit 44 latches the address signal for the second storage circuit at the trigger time T2.

In this case, the output clock signal of switch 42 becomes C1 in FIG. The trigger signal also enables the counter 50 of the W/R control circuit 48 to count the clock signal C1 after the trigger time T2. After counting a preset number of clock pulses, the W/R control signal is inverted and
The first write control circuit 46 stops generating the address signal, and the first storage circuit 22 also stops the write mode. Therefore, the first storage circuit 22 stores the digital value of the input signal when the clock signal C1 is generated, for example, between time points T0 and T6. It should be noted that the first part of the part of interest of the input signal (the part between time points T1 and T2) is not stored in detail in the first storage circuit 22, but this part is stored in detail in the second storage circuit 24. sea bream. Also,
It should also be noted that the first storage circuit 22 roughly stores the entire input signal and stores the portion of interest in detail. Note that the trigger time T2 is the high speed clock signal H.
If the counters 50 and 6 are not synchronized with each other, the counters 50 and 6
2 is doing the counting.

When the W/R control signal from the W/R control circuit 48 becomes a "low" level due to the read mode, the first and second storage circuits 22 and 24 enter the read state, and the MUXs 56 and 58 receive the address from the read control circuit 60. Select signal. In this read mode, the read control circuit 60 and the MUX 26
reads signals corresponding to time points T0 and T1 sequentially from the first memory circuit 22, then sequentially reads signals corresponding to time points T1 and T2 from the second memory circuit 24, and then sequentially reads signals corresponding to time points T2 and T6. The signals may be read out sequentially from the first storage circuit 22. That is, the signal portion stored in the first memory circuit 22 and corresponding to the time points T1 and T2 may be replaced in the second memory circuit 24.

The operation in this read mode will be further explained with reference to FIG. When the first and second memory circuits 22 and 24 write to the final address, they return to the initial address,
Since the data is sequentially written again toward the final address, and the storage capacities of the first and second storage circuits are different, the addresses at the time of the trigger are independent of each other. Further, the addresses of the first (ie, oldest) digital signals stored in the first and second storage circuits 22 and 24 are also independent from each other. Then,
At the beginning of the read mode, the arithmetic circuit 72
From the address at the trigger time from the first write control circuit 46, the setting value of the counter 50 of the W/R control circuit 48, and the storage capacity (final address) of the first storage circuit 22, the first The address of the digital value (corresponding to time T0) is calculated and preset in the counter 78. In addition, the arithmetic circuit 72
is the address next to the address at the trigger time from the second write control circuit 44, and the address of the first digital value in the second storage circuit 24 (corresponding to time T1).
and presets the counter 80. Further, the arithmetic circuit 72 calculates the number of pulses of the low frequency clock signal L between time points T0 and T1 from the periods of the high frequency and low frequency clock signals, the capacity of the second memory circuit 24, the address at the trigger time, etc., and applies the same to the latch circuit 74. This pulse number and time points T1 and T
The sum of the number of pulses of the high frequency clock signal H between the two is determined and latched in the latch circuit 76. The arithmetic circuit 72 also determines the number of pulses of the low frequency clock signal L between times T1 and T2.

The count value of the counter 84 is 0 (corresponding to time T0)
Then, the arithmetic circuit 72 converts the flip-flop 8
8 and 92. Thus, the output signal of exclusive-OR gate 94 is at a "low" level, gate 98 is on, and gate 100 is off. Therefore, the counter 78 counts the read clock signal in synchronization with the counter 84 and sequentially reads digital signals from the first storage circuit 22. In addition,
At this time, the output signal of the gate 94 causes the MUX26 to
selects the first memory circuit. When comparator 86 detects the address corresponding to time T1, the output signal of flip-flop 88 is inverted to a high level and the output signal of exclusive-OR gate 94 is also inverted to a high level. Therefore, MUX 26 selects second memory circuit 24, gate 98 is turned off, and counter 78 stops counting. On the other hand, the gate 100 is turned on, and the counter 80 counts the read clock signal in synchronization with the counter 84.
Digital signals are sequentially read from the second storage circuit 24. The arithmetic circuit 72 also operates the counter 7 by the number of pulses of the low frequency clock signal between time points T1 and T2.
Proceed with the counting details in step 8. When comparator 90 detects the address corresponding to trigger time T2 (actually time T3), the output signal of flip-flop 92 is inverted to a "high" level and exclusive-OR gate 9
The output signal of 4 is inverted to a "low" level. Therefore, MUX 26 selects the first storage circuit, gate 100 is turned off, and counter 80 stops counting. Meanwhile, the gate 98 is turned on again, and the counter 78 restarts counting from the address corresponding to time T3. When the counters 78 and 84 have counted up to the address corresponding to time T6, they return to the initial state and repeat the above-described operation. Therefore, time T
The input signal portions corresponding between 0 and T1 and between times T2, T3 and T6 can be read from the first storage circuit 22, and the input signal portions corresponding between times T1 and T2 and T3 can be read from the second storage circuit 24. .

In addition, in the above explanation, at the time of triggering,
Although switch 42 switches the clock signal from a low frequency to a high frequency, switch 42 may switch from a high frequency clock signal to a low frequency clock signal, for example, with a negative trigger slope and time T4 as the trigger time. That is, the clock signal from switch 42 may be C2 in FIG.
In this case, the first write control circuit 46 may be left as is, but the second write control circuit 44 may stop the address signal after a predetermined period of time has passed after the trigger signal is generated, or stop the write mode of the second memory circuit 24. good. Therefore, for example, the first memory circuit 2
2 stores the digital value of the input signal when the clock signal C2 is generated between times T1 and T7, and the second storage circuit 24 stores the digital value of the input signal when the high frequency clock signal H is generated between the times T4 and T6. Stores the digital value of the input signal. Arithmetic circuit 72 also counts the addresses of counter 84 corresponding to times T4 and T6, and latches these counts in latch circuits 74 and 76, respectively. Other operations are similar to those for the clock signal C1 described above.

By the way, as shown in FIG. 9, the signal storage device may want to continuously store a plurality of transients occurring at an interval. In such cases, it would be very convenient to be able to measure a plurality of transients as a whole, as well as to measure each transient part in detail. A second embodiment of the present invention that allows such measurements is shown in FIG. This embodiment is substantially similar to the embodiment of FIG. 2, so like blocks are designated with like reference numerals. Hereinafter, blocks different from those in FIG. 2 will be explained. The trigger circuit 14-1 supplies the output of the comparator 18 to a monostable multivibrator, as shown in FIG.
Therefore, the trigger circuit 14-1 generates a trigger signal with a predetermined pulse width each time the input signal exceeds the trigger level. In addition, the switch control circuit 102
controls the switch 42 to select the high frequency clock signal for a predetermined period each time a trigger signal is generated. This switch control circuit 102 is
For example, as shown in FIG. 12, the clock terminal C receives a clock signal from the switch 42, the reset terminal R receives a trigger signal, and a predetermined number of clock signals are input.
A counter 106 that generates an output signal when counting pulses, a D-type flip-flop 108 that receives a "high" level at its D terminal, receives the output signal of the counter 106 at its reset terminal R, and receives a trigger signal at its clock terminal C. It consists of That is, when the trigger signal is generated, flip-flop 108 is triggered and the Q output goes high, and counter 106 is reset to count a new clock signal. counter 10
6 resets the flip-flop 108 after a predetermined number of counts, so its Q output is "low".
Change in level. Therefore, switch control circuit 1
The output signal of 02 is at the "high" level only for a predetermined period after the trigger signal is generated.

In this embodiment, since the second storage circuit 24 stores portions of a plurality of transients immediately before trigger generation, the storage area of the second storage circuit 24 is divided into a plurality of sections. Therefore, the second write control circuit 44-1 is configured as shown in FIG. 13, for example. That is, counter 110 receives a trigger signal at clock terminal C and a W/R control signal at enable terminal E. Further, the counter 112 receives a high frequency clock signal at a clock terminal C, and receives a W/R control signal at an enable terminal E. counter 110
The count output of the counter 112 is assigned to the upper bits of the address signal, and the count output of the counter 112 is assigned to the lower bits of the address signal. Since the counter 110 changes its count value for each trigger signal and is responsible for the upper bits of the address signal, it specifies the divided storage area. Further, since the counter 112 changes its count value for each high-frequency clock signal and is in charge of the lower bits of the address signal, it specifies an address within a designated divided storage area. The latch circuit 114 is
Multiple address signals can be latched, and the address signals are latched one after another each time a trigger signal occurs.

Next, referring to the timing diagram of FIG.
The operation of the illustrated embodiment will be explained. When the write mode begins, MUXs 56 and 58 are connected to control circuit 4, respectively.
6 and 44-1, and the switch 42 selects the low frequency clock signal L, so the first memory circuit 2
2 stores the digital value of the input signal when the low frequency clock signal L is generated. The first storage area of the second storage circuit 24 stores the digital value of the input signal when the high frequency clock signal H is generated.
When the first trigger signal is generated at time T2, the switch 42 selects the high frequency clock signal H, and the first storage circuit 22 stores the input signal in accordance with this clock signal H. On the other hand, the second write control circuit 44-1 specifies the second storage area of the second storage circuit 24 using the first trigger signal. Therefore, in the first storage area, before the trigger time T2, the digital value of the input signal is stored as much as the storage capacity of this storage area (corresponding to, for example, between times T1 and T2). Further, the latch circuits of the write control circuits 46 and 44-1 are activated at the trigger time T2.
latches each address signal. At time T3, a predetermined period of time has elapsed from trigger time T2, switch 42 selects low frequency clock signal L.
Therefore, the clock signal from switch 42 is
It will look like Figure C.

Furthermore, when the second trigger signal is generated at time T5, the switch 42 selects the high frequency clock signal H, as in the case of the first trigger signal, and the second write control circuit 44-1 selects the high frequency clock signal H. The third storage area of the circuit 24 is designated. Therefore, the second
The second storage area of the storage circuit 24 stores time points T4 and T.
The digital values of input signals between 5 are stored. The latch circuits of the first and second write control circuits 46 and 44-1 latch their respective address signals at trigger time T5. Hereafter, the same operation is repeated. On the other hand, the W/R control circuit 48-1 is, for example, provided with a latch circuit (for example, a D-type flip-flop) for latching a trigger signal before the enable terminal E of the counter 50 shown in FIG. Then,
The W/R control circuit 48-1 starts counting the clock signals from the first trigger time T2, and when the predetermined number of counts is completed (for example, time T10), the writing in the first and second memory circuits 22 and 24 is performed. Stop the mode. Therefore, the first memory circuit 22 stores the time T
The digital value of the input signal when the clock signal C is generated between 0 and T10 is stored. Further, the first, second, and third storage areas of the second storage circuit 24 are stored between time points T1 and T2, and between time points T4 and T5, respectively.
The digital value of the input signal at the time when the high frequency clock signal H is generated between T7 and T8 is stored.

In read mode, MUX 56 and 58
selects the read address signal from the read control circuit 60, and selects the read address signal from the read control circuit 60 between time points T0 and T1 and between time points T2 and T.
4, between time points T5 and T7, time points T8 and T10
Between time points T1 and T2, between time points T4 and T5,
It is sufficient to read the signal corresponding to the time between time T7 and time T8 from the second storage circuit 24. In order to control this read operation, the read control circuit 60 may have the configuration shown in FIG. (for address specification). Further, the arithmetic circuit 72 operates at time T0,
First memory circuit 22 corresponding to T2, T5 and T8
counter 78 during the read operation.
It is also necessary to sequentially preset the counter 80 during the read operation by determining the addresses of the second memory circuit 24 corresponding to times T1, T4 and T7. Furthermore, the arithmetic circuit 72 determines the addresses of the counter 84 corresponding to time points T1, T4, and T7, and sequentially latches them in the latch circuit 74 during the read operation.
It is necessary to find the address of the counter 84 corresponding to the address and sequentially latch it in the latch circuit 76 during the read operation. Note that since the read operation may be performed at a low speed, the arithmetic circuit 72 can perform a preset operation or a latch operation during the read operation. Other operations are similar to those in the first embodiment.

Although the foregoing describes only preferred embodiments of the invention, those skilled in the art will appreciate that various modifications can be made without departing from the spirit of the invention. For example, although the signal storage circuit in the above embodiment is a waveform storage circuit, it may also be applied to a logic analyzer. In this case, the A/D converter and the D/A converter may be removed and the trigger circuit may be a word recognizer (detects a predetermined digital word from the input digital signal). Further, an external trigger signal and an external clock signal may be used, or a shift register may be used in the storage circuit. Furthermore, in the case of a waveform storage device, a dedicated A/D converter may be provided for each of the first and second storage circuits. Furthermore, if the stored contents of the first storage circuit are used to measure the time between two points including the trigger point in the reproduced signal, the measurement accuracy will decrease due to the uncertain time in the clock frequency switching part. An uncertain time can be measured based on the storage contents of the second storage circuit, and measurement accuracy can be improved.

〔Effect of the invention〕

As described above, according to the signal storage device of the present invention, since the input signal is stored in the first storage circuit by switching the clock frequency according to the trigger signal, the entire input signal can be stored roughly (as a low frequency clock signal). death,
The part of interest in the input signal can be memorized in detail (using a high-frequency clock signal). That is, since the entire input signal and the portion of interest are stored in the same storage circuit, the relationship between the entire input signal and the portion of interest can be reliably determined. Furthermore, when switching the clock signal, the part of interest in the input signal that is roughly stored in the first memory circuit is stored in fine detail in the second memory circuit, so that the entire part of interest can be measured in detail. Furthermore, when reading the memory content of the first memory circuit, only the part where the memory content temporally corresponds to the memory content of the second memory circuit is replaced by the memory content of the second memory circuit instead of the first memory circuit. , the entire input signal stored in the first and second storage circuits can be easily confirmed.

[Brief explanation of drawings]

FIG. 1 is a timing diagram for explaining the operation of the conventional signal storage device and the present invention, FIG. 2 is a block diagram of a preferred embodiment of the present invention, and FIG. 3 is a diagram of the trigger circuit used in FIG. 4 is a block diagram showing an example of the clock generator used in FIG. 2, FIG. 5 is a block diagram showing an example of the W/R control circuit used in FIG. 2, and FIG. 6 is a block diagram showing an example of the W/R control circuit used in FIG. FIG. 7 is a block diagram showing an example of the first write control circuit used in FIG. 2, FIG. 7 is a block diagram showing an example of the second write control circuit used in FIG. 2, and FIG. 8 is a read control circuit used in FIG. 2. Block diagram showing an example of
The figure is a timing diagram for explaining the operation of another embodiment of the present invention, Figure 10 is a block diagram of another preferred embodiment of the present invention, and Figure 11 is a circuit diagram of a trigger circuit used in Figure 10. , FIG. 12 is a block diagram of the switch control circuit used in FIG. 10, and FIG. 13 is a block diagram of the second write control circuit used in FIG. In the figure, 22 is the first memory circuit, 24 is the second memory circuit, and 24 is the second memory circuit.
42 is a switch, 44 and 44-1 are second write control circuits, 46 is a first write control circuit, and 60 is a read control circuit.

Claims (1)

[Claims] 1. A switch for switching from a first clock signal to a second clock signal having a higher frequency than the first clock signal when a trigger signal is generated; a first memory circuit; a first write control circuit that causes the first storage circuit to store the input signal before and after the trigger signal is generated, and latches the address of the first storage circuit at the time when the trigger signal is generated; a memory circuit; in response to the second clock signal, the input signal immediately before the trigger signal is generated is stored in the second memory circuit, and the address of the second memory circuit at the time when the trigger signal is generated is stored; a second write control circuit that latches; and reads the memory contents of the first memory circuit;
According to the address latched in the first write control circuit and the address latched in the second write control circuit, the memory contents of the first memory circuit temporally correspond to the memory contents of the second memory circuit. Only the portion is connected to the second memory circuit instead of the first memory circuit.
A signal storage device comprising a readout control circuit that reads out stored contents of a storage circuit. 2. When a trigger signal is generated, a switch for switching from the first clock signal to a second clock signal having a lower frequency than the first clock signal; a first storage circuit; a first write control circuit that causes the first memory circuit to store the input signal before and after the trigger signal is generated, and latches an address in the first memory circuit at the time when the trigger signal is generated; a second memory circuit; a second write control for storing the input signal immediately after the trigger signal is generated in the second memory circuit in response to the one clock signal, and latching the address of the second memory circuit at the time the trigger signal is generated; reading out the memory contents of the circuit and the first memory circuit;
According to the address latched in the first write control circuit and the address latched in the second write control circuit, the memory contents of the first memory circuit temporally correspond to the memory contents of the second memory circuit. Only the portion is connected to the second memory circuit instead of the first memory circuit.
A signal storage device comprising a readout control circuit that reads out stored contents of a storage circuit.