SU1660053A1 - Device for ambiguous answer retrieval from associative memories - Google Patents

Description

The invention relates to computing and can be used when reading information from associative mass storage devices.

The aim of the invention is to increase the speed of the device. The device contains a control trigger, the first input of which is the input of the read permission of the device, and the output is connected to the first input of the element I. The second input of which is the clock input of the device, and the output is connected to the clock input of the first block of the polling of the outputs of the response of the cells of the associative memory The polling unit, starting with the second one, is connected to the clock output of the previous polling unit, the clock output of the last polling unit is connected to the second input of the control trigger. The purpose of the invention is achieved by the fact. that a sample of each word with a multi-valued response requires only a clock pulse, and the frequency of clock pulses is determined only by the temporal characteristics of the polling unit circuit and does not depend on the number and location of the selected cells of the associative memory. 1 il.

The invention relates to computing and can be used when reading information from associative mass storage devices.

The aim of the invention is to increase the speed of the device.

The drawing shows a diagram of the device for extracting a multi-valued response from the associative memory.

The device contains a control trigger 1, the element And 2, the outputs 3 of the code of the address of the answer, M blocks 4 polling the outputs of the response of the cells of the associative memory. Each

block 4 contains the trigger 5, the element OR 6, the element And 7, the element NOT 8. the element And 9 and the element NOT 10. The drawing also indicates the outputs 11 of the response of the cells of the associative memory, the inputs 12 of the excitation of the polling units, the inputs 13 clock pulses of the polling unit, outputs 14 clock pulses of polling units, inputs 15 of the initial installation of polling blocks, bit outputs of 16 polling blocks, device read permission input 17, device clock input 18, device clock output 19, logical unit input 20.

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The device works as follows.

The zero state of the controlling trigger 1 is the initial one.

The operation of the device begins by outputting 11 potential signals from the associative memory cells to the corresponding inputs of 12 polling blocks 4 and, after this, a read signal to the input 17 of the device that sets the triggers

5 to the initial state via the tires 15ι -15m, and the controlling trigger 1 to the working (single) state, thanks to which the element AND 2 opens to the first input and the clock pulses from the input 18 begin to flow into the device. If at the input 12ι of the first block 4ι of the poll there is a response of the first cell of the associative memory (i.e. state "1"), then the first clock pulse received at input 13ι from element 14 2 through the open element I 9 will pass to the dynamic C input trigger 5 and the bit output 16ι of block 4c but will be absent at the output of 14ι clock pulses of this polling block (since the outputs of the element are NOT 10 and the trigger 5 has zero signals, a zero signal from the output of the element OR

6 closes the element And 7 and through the element NOT 8 opens the element And 9).

Consequently, at the 3ι output there will be an excited (single) state, and at the remaining outputs it will be zero, so that at the outputs of 3 devices during the first clock pulse there is an address of the first selected cell of the associative memory. At the end of the first clock pulse (at its trailing edge), the trigger 5 of block 4ι is set to one.

The second clock pulse received at input 131 of block 4ι passes to output 14ι and does not pass to output 16t, since the presence of a single signal at the output of the element OR 6, due to the single state of trigger 5, leads to the opening of the element AND 7 and through the element HE 8 - to close the element and 9.

If there is no response at the input 12ι of the first cell of the associative memory, then the clock pulse received at the input 13t of block 4c passes to output 14ι and does not pass to output 16t due to the presence of an input signal from the element OR 6 unit from the element NOT 10.

Thus, the next clock pulse freely passes through those blocks 4 polls, which correspond to the unselected cells of the associative memory, and reads the outputs of the 3 addresses of the next selected cell at the outputs, resulting in sequential sampling of the addresses of N selected cells of the associative memory.

(M + 1) -th pulse, having passed all blocks 4, appears at the output 19 of the device and sets the control trigger 1 to its original state, thereby stopping the flow of clock pulses into the device. A clock pulse at output 19 can be used as a readout signal for a similar device when increasing the number of associative memory cells.

Claims (1)

Claim A device for extracting a multi-valued response from an associative memory containing a group of polling blocks, each of which includes a trigger, the output of which is connected to the first input of the element OR, the element of NOT, the output of which is connected to the first input of the first element And, the output of which is connected to the information output of the polling unit , the information inputs of the polling units are the response outputs of the cells of the device associative memory, and the information outputs of the polling units are the outputs of the device response code, characterized in that There is a speed increase, a control trigger and an element are entered into the device, each polling block additionally contains a second element NOT and a second element AND, the first input of the control trigger is the input of the read permission of the device and connected to the reset input of the trigger blocks of the polling, whose information inputs are input the logical unit of the device, the output of the control trigger is connected to the first input of the element I, the second input of which is the clock input of the device and the output is connected to the clock input the first polling unit, the clock input of each subsequent polling unit, starting from the second, is connected to the clock output of the previous polling unit, the clock output of the last polling unit is the clock output of the device and connected to the second input of the control trigger, in each polling unit the second input of the I) 1I element connected to the output of the second element NOT, the input of which is connected to the information input of the polling unit, the second input of the first element I is connected to the clock input of the polling unit and the first input of the second element 14, the second input to orogo connected to the output of the OR gate and to the input of the first NOT member and an output connected to the clock output interrogation unit, the output of the first AND element is connected to the clock triggers. 1660053