SU1660053A1 - DEVICE FOR EXTRACTING MULTIPLE-SURVEY RESPONSE FROM ASSOCIATIVE MEMORY ¢ 7) - Google Patents

Description

The invention relates to computing technology and can be used for reading information from high-capacity associative storage devices.

The aim of the invention is to increase the operating speed of a device. The device comprises a control trigger, the first input of which is the read enable input of the device, and the output is connected to the first input of an AND element. The second input of which is the clock input of the device, and the output is connected to the clock input of the first block for polling the response outputs of associative memory cells. The clock input of each subsequent polling block, starting with the second, is connected to the clock output of the previous polling block, and the clock output of the last polling block is connected to the second input of the control trigger. The aim of the invention is achieved in that only a clock pulse is required to select each of the words in a multi-valued response, wherein the frequency of the clock pulses is determined only by the timing characteristics of the polling block circuit and does not depend on the number and location of the selected associative memory cells. 1 Fig.

The invention relates to computing technology and can be used for reading information from high-capacity associative storage devices.

The aim of the invention is to increase the performance of the device.

The figure shows a diagram of a device for extracting a multi-valued answer from associative memory.

The device contains a control trigger 1, an AND element 2, outputs 3 of the response address code, M blocks 4 for polling the response outputs of the associative memory cells. Each

Block 4 contains a trigger 5, an OR element 6, an AND element 7, a NOT element 8, an AND element 9, and a NOT element 10. The drawing also shows outputs 11 of the associative memory cell response, inputs 12 of the polling block excitation, inputs 13 of the polling block clock pulses, outputs 14 of the polling block clock pulses, inputs 15 of the initial setup of the polling blocks, bit outputs 16 of the polling blocks, input 17 of the device read enable, input 18 of the device clock pulses, clock output 19 of the device, input 20 of the logical one.

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The device works as follows.

The zero state of control trigger 1 is the initial state.

The operation of the device begins by supplying potential response signals from the associative memory cells to the corresponding inputs 12 of the polling blocks 4 via outputs 11 and, following this, a reading signal to input 17 of the device that sets the triggers

5 to the initial state via buses 15ι -15m, and the control trigger 1 to the working (single) state, due to which the AND element 2 at the first input opens and clock pulses from input 18 begin to arrive at the device. If there is a response from the first associative memory cell at input 12ι of the first polling block 4ι (i.e., state "1"), then the first clock pulse arriving at input 13ι from element 14 2 through the open AND element 9 will pass to the dynamic C-input of trigger 5 and to the bit output 16ι of block 4c, but will be absent from the output 14ι of clock pulses of this polling block (since there are zero signals at the outputs of the NOT element 10 and trigger 5, a zero signal from the output of the OR element

6 closes the AND element 7 and through the NOT element 8 opens the AND element 9).

Consequently, output 3ι will be in an excited (one) state, while the other outputs will be in a zero state. This means that the address of the first selected associative memory cell is present at outputs 3 of the device during the first clock pulse. At the end of the first clock pulse (at its falling edge), trigger 5 of block 4ι is set to the one state.

The second clock pulse, received at input 131 of block 4ι, goes to output 14ι and does not go to output 16t, since the presence of a single signal at the output of element OR 6, caused by the single state of trigger 5, leads to the opening of element AND 7 and, through element NOT 8, to the closing of element AND 9.

If there is no response from the first associative memory cell at input 12ι, then the clock pulse received at input 13t of block 4c passes to output 14ι and does not pass to output 16t due to the presence of a single signal from the NOT element 10 at the input of element OR 6.

Thus, the next clock pulse freely passes through those polling blocks 4, which correspond to the unselected cells of the associative memory, and carries out reading at the outputs 3 of the address of the next selected cell, as a result of which, successively, clock after clock, the selection of the address array of N selected cells of the associative memory occurs.

The (M+1)th pulse, having passed through all 4 blocks, appears at output 19 of the device and sets control trigger 1 to its initial state, thereby stopping the flow of clock pulses to the device. The clock pulse at output 19 can be used as a read signal for a similar device when increasing the number of associative memory cells.

Claims (1)

Claim A device for extracting a multi-valued response from an associative memory containing a group of polling blocks, each of which includes a trigger, the output of which is connected to the first input of the element OR, the element of NOT, the output of which is connected to the first input of the first element And, the output of which is connected to the information output of the polling unit , the information inputs of the polling units are the response outputs of the cells of the device associative memory, and the information outputs of the polling units are the outputs of the device response code, characterized in that There is a speed increase, a control trigger and an element are entered into the device, each polling block additionally contains a second element NOT and a second element AND, the first input of the control trigger is the input of the read permission of the device and connected to the reset input of the trigger blocks of the polling, whose information inputs are input the logical unit of the device, the output of the control trigger is connected to the first input of the element I, the second input of which is the clock input of the device and the output is connected to the clock input the first polling unit, the clock input of each subsequent polling unit, starting from the second, is connected to the clock output of the previous polling unit, the clock output of the last polling unit is the clock output of the device and connected to the second input of the control trigger, in each polling unit the second input of the I) 1I element connected to the output of the second element NOT, the input of which is connected to the information input of the polling unit, the second input of the first element I is connected to the clock input of the polling unit and the first input of the second element 14, the second input to orogo connected to the output of the OR gate and to the input of the first NOT member and an output connected to the clock output interrogation unit, the output of the first AND element is connected to the clock triggers. 1660053