SU1314388A1 - Device for checking internal memory blocks - Google Patents

Abstract

The invention relates to computing and can be used for offline testing and adjustment of RAM blocks. The purpose of the invention is to increase the speed of the device. The device for controlling memory blocks contains a generator of 1 clock pulses, a distributor of 2 pulses, a counter of 3 addresses, a block of 9 depessers, triggers 5 and 12, a counter of 7 pulses, a decoder 8, a shift register 13, elements 6 11 and 14, element OR 10, the operation of the device is based on writing test information into block 4 of memory, which provides for reading a certain number of units at the output of a working RAM block. The test is organized in such a way that if any malfunction occurs in block 4, the number of units and its output increases or decreases. The number of units at the output of the block is counted, a potential malfunction signal is generated. 1 il. with S (L I VyhoZ CO 4 SAE 00 00

Description

The invention relates to computing and can be used to autonomously check and adjust RAM blocks.

The purpose of the invention is to increase the speed of the device. The figure shows the functional diagram of the device for control. memory blocks.

The device contains a clock pulse generator 1, a pulse distributor 2, an address counter 3 and is connected to a controlled memory unit 4. The device also contains the first trigger 5, the first element I. 6 ,. counter 7 pulses, decoder 8, block 9 decoders, the element OR 10, the second element And P., the second trigger 12, the register 13-shift and the third element And 14.

Generator 1 is a self-oscillating pulse sequence generator. The generation frequency is selected taking into account the maximum permissible frequency of changing the address in block 4.

The distributor 2 pulses can be performed, for example, according to the scheme of the digital frequency divider pulses by three. At the same time, at the entrance of the counter 3 addresses a sequence of allocated first pulses is connected. At the other output of the distributor 2, a sequence of selected second pulses is formed.

The decoder 8 selects one of the states of the counter 7 and can be performed, for example, on a multi-input element I. Block 9 decoders

It is a set of decodes each time in a mofrator, similar to decoder B.

The device works as follows.

In the initial state, in the absence of the Start command, the two-bit register 13 is held on the setting input in the zero state. Element I 14 is closed and there is no signal at the output of the device that the counter overflows to the 3 address, i.e. once per full cycle of consecutive access to all memory cells of block 4. A full cycle 5 of operation of the address 3 counter, at which the forward output of the trigger 5 has a month. This is the enabling potential, is a write cycle. In the write loop, element 6 is open. Impulses zannosti. The memory cells of co.controlled 50 that come from the second output of the RAM 4 are located on the distributor 2, which passes to the input

in arbitrary state.

The generator 1 generates a continuous sequence of clock pulses. The pulse distributor 2 divides the frequency of the clock pulses into three. The sequence of first pulses formed at the output of the distributor 2

to the input of the counter 3 addresses; The sequence of second pulses formed at the second output of distributor 2 comes to the inputs of elements 6 and 11 and gates the signals received 1x to the other inputs of these elements.

Counter 3 of the address has the number of digits equal to the number of address inputs of the block 4. By counting the pulses coming from the output of the distributor 2, the counter 3 of the address generates binary numbers from 0 to 2-1 at its outputs. memory cells of block 4.

Block 9 decoders contains n decoders and decrypts binary ones.

Numbers containing only one unit in their categories. For example, with a four-bit counter 3 address, these binary numbers are 0001, 0010, 0100, - 1000. The signals from the outputs of the decoders of block 9 are combined on the OR 10 element and are sent as test signals to the information input of the 4 RAM in the memory cell. Thus, for this example, in the memory cells with addresses 0001, 0010, 0100 ,. 1000 is written in the write cycle, one unit, in the rest of the memory cells - zero.

The write and read modes in the device are switched by trigger 5, to the input of which pulses are output from the high-order output of the counter 3 addresses. At the same time, trigger 5 is change.

overflow counter 3 addresses, i.e. once per full cycle of consecutive access to all memory cells of block 4. A full cycle 5 of operation of the address 3 counter, at which the forward output of the trigger 5 has a month. This is the enabling potential, is a write cycle. In the write loop, element 6 is open. Impulses over55

records of block 4. The units coming from the output of the element OR 10 are recorded in the memory cells with the specified addresses. At the end of the write cycle, the trigger 5 changes its state. At the same time, element 6 is closed and element 11 is opened. Counter 7 in recording mode has zeroed

with the installation input pulses from the output element And 6.

In the read cycle, at the output of an operable 4. memory block, n units recorded in the cycle appear. Counter 7 counts these units. To ensure its normal operation, the signals from the output of block 4 are gated on the And 1 G element by recording pulses. The number of bits of counter 7 is chosen equal to the nearest integer number, larger than 1 + Iog2.

At the end of the read cycle, trigger 5 is again triggered. At this point, counter 7 is set to state in its counting process. it is set to the state corresponding to the signal at its information input. If the decoder 8 is open at this moment, the trigger 12 is set to a state in which there is no fault signal on its inverse output. In any other state of the counter 7, an error signal appears on the inverse of the output of the trigger 12, which is stored in the trigger 12 until the next positive voltage drop, i.e. before the start of the next recording cycle.

Thus, to control the RAM block 4, it is sufficient to carry out one cycle of recording test signals and one read cycle. To eliminate the appearance of a false alarm at the device output, which may occur when the device is turned on or when changing the tested RAM block 4, The device performs additional gating of the fault signal.

After switching on the device or changing block 4, the device receives the Start command via the setup input of the register 13, and the register 13 stops holding in the zeroed state. When a tacit input of the register of 13 voltage drops, formed by the trigger 5, is applied, the register 3 begins to be filled with units. Second by sche

five

0

five

0

five

0

five

0

This voltage drop causes the second bit of the register 13 to be triggered. In this case, the And 14 element is opened, the fault signal is allowed to the output of the device.

Since between two voltage drops occurring at the output of the trigger 5, one read cycle and one write cycle are enclosed, by the time element 14 is opened, the control of unit 4 is over. This prevents the occurrence of a false alarm at the device output.

The device with possible malfunctioning of the monitored block 4 of the RAM operates as follows.

In the event that one or more address circuits are broken in block 4 of the RAM, the number of units at the output of block 4 appearing in the read cycle increases. For example, when item 4, units are recorded in block 4, when counter 3 states address 0001, Q010, OiOO, 1000, Let there be an open circuit in the low-order connection (in the drawing on the right) of the address bit. In this case, an arbitrary potential is established in this circuit, for example O. Then the recording takes place in a memory cell with addresses 0000, 0010 0100, 1.000.

In the read cycle, the least significant bit of the address also preserves the state O. Therefore, the units at the output of block 4 appear at the counter 3 states of the address 0000, 0001, 0010, 0011 0100, 010, 1000, Ш01, Thus, at the output element AND 1 appears twice as many pulses as it does when the unit 4 is in good condition. At the end of the cycle, the readout at the output of the decoder 8 is O. The trigger 12 is set to a state indicating a malfunction of the unit 4. At high; device appears to malfunction. I

With the test signal selected in the device, the number of units, arising 1x at the output of block 4 in the read cycle, will increase rfb compared to normal for any fault in the connection circuits of the address signals, i.e. both at breaks, and at closing x. When the device is operated, the circuits are also controlled.

51314388

x informational records, the output of the rejection of the work on the signal is 5

possible re7. in the process of counting about the output of the elder one is connected to the input About the response of the old man 7 element And 11 pulses of interruption

best of all at the same time, by way of time, at least half of the second;

Claims (1)

Invention Formula Device for controlling RAM blocks, containing a clock pulse generator, pulse distributor, address counter, OR element, first trigger, AND elements, pulse counter and decoder, the output of the clock generator being connected to the pulse distributor input whose first output is connected to the counting the input of the address counter; the second output of the pulse distributor is connected to the first input of the first AND element whose output is the device's write output; the outputs of the address counter bits are with the address output device, wherein .chto in order povsh1eni operating speed of the device introduced into it Editor I. Casard Compiled by V.Rudakov Tehred B.Kadar Cor Pod 2215/52 Circulation 590 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 the decoder block, the second trigger and the shift register, and the decoder block inputs are connected. To the outputs of the address counter, the output of the OR element is an information output of the device, the first input of the second And element is an information input of the device, the second input of the second And element is connected to the second the output of the pulse distributor, the third and fourth inputs of the second element I are connected respectively to the inverted output of the first trigger and the output of the higher-level pulse counter, the output of the second element I is connected to the The current input of the pulse counter, the setup input of which is connected to the output of the first element And, the direct output of the first trigger is connected to the second input of the first element And the clock inputs of the shift register and the second trigger, the output of the shift register is connected to the first input of the third element And, the second input which is connected to the inverse output of the second trigger, the outputs of the bits of the pulse counter are connected to the inputs of the decoder, the output of which is connected to the information input of the second trigger, the control input of the shift register are input trigger device vghod third AND gate is a control output of the apparatus, the block decoders outputs connected to inputs of OR element. Proofreader S.Lyzhova Subscription