SU1327086A1 - Information input device - Google Patents

Description

The invention relates to a computational technique, in particular, can be used to enter information into a computer.

The purpose of the invention is to increase the reliability of information input.

FIG. 1 shows a block diagram of the proposed device; FIG. 2 shows a table in which the contents of the memory cells are shown; in fig. 3 - time diagram of the device operation at the closure of one of the switching, keyboard elements; in fig. four

temporary diagram of operation of the device 15 first address input of the memory block 8

with the closure of two or more switching elements of the keyboard.

The device contains 1 pulse generator, first 2 and second 3 counters, decoder 4, first element 5 OR, keyboard 6, multiplexer 7, memory block 8, register 9, initial setup circuit 10, element 11 AND and second element 12 I.PI .

The device operates as follows of the second counter 3. On the fourth and fifth

at once.

In the initial state, all switching elements of the keyboard 6 are open. When the power is turned on, the initial setup circuit 10 generates a pulse of the initial setup (NI), which enters the reset input of register 9, zeroes it. Signals arriving at the second input of element 11 And and the second inverting input of element 12 OR from the second and third outputs of register 9, respectively, form the output of the second element 12 OR level 1, by which counter 3 is set to zero.

Two-phase generator 1 pulses synchronizes the operation of the device and generates clock pulses TI 1 and TI 2, shifted relative to each other.

The part of the device to which the first counter 2, the decoder 4, multiplexer 7, determines the state of the switching elements of the keyboard 6. The first counter 2 performs the recalculation of TI pulses 1. The outputs of the first counter 2 are the output buses of the device and are also connected to the inputs of the decoder 4 and the multiplexer 7. When the switching elements are closed, the corresponding outputs of the delfrarator 4 are connected to the corresponding inputs of the multiplexer 7 and if the codes of the first counter 2 coincide with the codes of the deputy

The whip switching elements of the keyboard 6 at the output of the multiplexer 7 appear as a level 1 signal.

The part of the device into which the second counter 3 enters, the first element 5 OR, the memory block 8, the register 9, the element 11 AND, the second element 12 OR, generates the control signals for recording and errors in accordance with the states of the switching elements of the keyboard 6 and the internal states of the device. The signal about the state of the switching elements goes to

from the output of the multiplexer 7. From the output of the first element 5 OR, the second input of the memory block 8 receives a signal about the low-order bits of the second counter 3. When the state is zero. of these bits, the second input of the memory block 8 receives a signal at the level O, the third input of the memory block 8 receives a signal from the higher second

inputs come from the first and second outputs of register 9. The presence of these signals is determined by level 1.

The inputs to the memory block are addressable. Each address corresponds to its own cell. The contents of the memory cells determine the operation of the entire device and are listed in the table in FIG. 2 ..

In the initial state, after the expiration of the initial setup pulse, the zero-cell address is set at the inputs of the memory block 8. The contents of this cell are read by TI 2 pulses into register 9, and the signals from the output of this register confirm the initial state of the device: the absence of recording signals and

errors and reset of the second counter 3. The device is in this state until the moment of changing the address at the input of the memory block 8.

The timing diagram of the operation of the device when the closure of one of the commutation, rational elements 6 is shown in Fig.3. In this case, the address of the first cell appears at the inputs of the memory block 8, the contents of which is recorded in

register 9, the signal from the third output of the register through the second element 12 OR removes the reset signal from the input of the second counter 3, allowing it to count the pulses of TI 1. The first pulse of TI 1 leaves the zero state and the second input is set to the reset input of memory block 8 memory cells. The contents of this cell does not change the state of register 9, allowing the counter 3 to count pulses TI 1, the width of the first counter 2 and the number of lower bits of the second counter are the same and are determined by the number of switching elements of the keyboard 6. Since the address is at the input of memory block 8 and, accordingly, the state of register 9 does not change, then the second counter continues to count TI 1 pulses until the appearance of level 1 at the output of the high bit. At this moment, if the switching element of the keyboard 6 is already open, the fourth cell address is set at the input of the memory, the contents of which is written to register 9 and sets the device to its initial state. If the switching element is still closed, then the address of the fifth cell is set at the inputs of the memory block 8, the contents of which is written to the register 9 and from its first output to the device output, and the fourth input of the memory block 8 is given a write signal, the signal from the third output register allows the second counter 9 due to the pulses of TI 1. Further, when cyclically changing the state. neither the second counter 3, and if the switching element is closed, the addresses of the following cells alternate at the inputs of the memory unit 18: 14.9, 10.13. The content of these cells is the same and coincides with the content of the 5 cells, i.e. device state does not change. In the event that the switching element opens, one of the following addresses appears at the inputs of memory block 8, depending on the opening time: 8 or 12. The contents of these cells are the same and after writing them to register 9 the device is reset .

The time diagram of the device when two or more switching elements of the keyboard 6 are closed at once is shown in FIG. 4. In this case, the device starts operating at the moment when the address of the first cell is set at the inputs of the memory block 8. The address of this cell is set when the code of the nearest

0

five

0

five

the closed switching element 6 with the code of the first counter 2. Next, the device operates as in the case of closing one switching element until the next closed switching element of the keyboard 6 matches the code of the first counter 2. At this moment, the third cell address is set at the inputs of the memory 8, the contents of which are recorded in register 9, and from its second output, the signal goes to the fifth input of memory block 8, the second input of element 11 I, and to an external device, indicating the closure of several clocks mutation elements 6, the signal from the third output is fed to the second input of the second element 12IL | Since the information at the outputs of register 9 appears as the leading edge of pulse TI 2, during the high level of this pulse at the third input of element 11 and at the other two of its inputs there are also high level signals that ensure the passage of pulse TI 2 to the reset input of the second counter 3. With this impulse, the second counter 3 is nullified and at the end of its operation again goes out of the zero state, and the address of the cell 18 is set at the inputs of the memory block 8, if the next order is the switching element of the keyboard 6 open, or 19 if it is closed. The contents of these cells are the same as cells 3, and the state of register 9 does not change. At cell address 19, the second counter 3 is reset by the TI 2 impulse passing through the elements 11 AND and 12 OR to its reset input, and the addresses 18 or 19 are set to the inputs of the memory 8 depending on from the state of the following in order of com-unit elements. At the address 18 at the input of the memory block 8, the zeroing of the second counter 3 does not occur, the address at the input of the memory block 8 does not change, it does not change.

Further, if the next ordering key element of the keyboard 6 is closed, then the address 19 of the cell is set again at the inputs of memory block 8, the second counter 3 is reset and depending on the state of the next key switch element 6 on

0

five

0

five

0

20

25

memory address is set to address 18 or 19 cells. If all the following switching elements are in order open, then the output of the high bit of the second counter 3 is set to level 1, and the input of memory block 8 is the address of one of the cells 20 or 21.

Cell address 21 is set at the inputs of memory block 8, if the last switching element of the keyboard 6, at which the reset has occurred, is tO. The second counter 3 remains in the closed state. In this case, the second t5 counter 3 is reset (since the contents of cell 21 are the same as the contents of cell 3), and then at the inputs of memory block 8 is set depending The status of the following switching elements is address 18 or 19 cells,

The address 20 of the cell is set if all the switching elements of the keyboard 6 are open and in register 9 the pulse TI 2 records the contents of this cell. The contents of this cell are the same as cells four. The device is reset. Thus, when the device closes two or more switching elements of the keyboard 6 at once, it does not output a write signal to the device output and indicates this state of the switching elements 6 by error signals.

In addition, if, with one closed switching element 6, the device outputs a recording signal, and then one or more other contactless elements 6 are closed, the device removes the recording signal, generates an error signal -1bki (see the contents of cells 15 and 11 in the table on Fig. 2) and it comes to a standstill only when all switching elements of the keyboard 6 are opened, as in the case of two or more of its switching elements 8,

When a circuit fails or when a failure occurs, the address of one of these cells (the contents of these cells are the same) appears at the inputs of memory block 8 and its contents are written to register 9. Signals from the first, second and third codes of register 9 return the device to the initial state, and from the fourth, a level error signal is output to the external device. 1 for display.

Claims (1)

Invention Formula thirty The monitoring of the device’s operability is ensured by the contents of the cells 6, 7, 16, 22-31 of the memory block 8. During the nominal operation of the device (all elements of the circuit are intact and there are no failures) the addresses of the cells at the inputs of the memory block 8 do not occur. In case of malfunction, an information input device containing a pulse generator, a serially connected decoder and a keyboard, two counters, an element, the first output of the pulse generator is connected to the first input of an element, the first group of outputs of the first counter is connected to the inputs of the decoder, the first and second groups of outputs of the first The counter is informational outputs of the device, characterized in that, in order to increase the reliability of the input of information, a multiplexer, a memory block, a register, two elements are entered into it. nA And, the second group of outputs of the first counter is connected to the address inputs of the multiplexer, the keyboard outputs are connected to the information inputs of the multiplexer, the output of which is connected to the first address input of the memory block and the second input of the I element, the outputs of the memory block are connected to the information inputs of the register, The first output of the pulse generator is connected to a control input of the register, the reset input of which is the device reset input, the group of outputs of the second counter is connected to the inputs of the first RSHI element, the output Expensive - connected to source 45 by the address input of the memory unit, the output of the second counter is connected to the third address input of the memory block, the second output of the pulse generator is connected to the counting inputs of the counters, the first output of the register is connected to the fourth address input of the memory block and is the transducer Record device, the second register output is connected to the fifth address input yy memory block, the third input element 50 This AND, the third output of the register is connected to the first input of the second element OR, the output of the element AND is connected to the second input of the second element 1Sh, the circuit output, or in the event of failure, the address of one of these cells (the contents of these cells are the same) appears at the inputs of memory block 8 and its contents are recorded in register 9. Signals from the first, second, and third codes of register 9 return the device to its original state, and from the fourth, the level error signal is output to the external device. 1 for display. Invention Formula This AND, the third output of the register is connected to the first input of the second element OR, the output of the element AND is connected to the second input of the second element 1SHI, I32770868 the stroke of which is connected to the reset input; the register outputs are the outputs of the second counter, the second and fourth devices. FIG. 2 lJlJlJIJlJbJl.nJlJlJlJb fLJIJTJl-JLJLJI EXIT) register 9 Vshod H-ff Bi ifodmHIS Eysmvwfa 3 outputs Closed PU8. 3 Editor K. Kopcha Compiled by I. Karpova Tehred A. Kravchuk Proofreader L.Pata Order 3389/44 Circulation 672 Subscription, VNIIPI State Committee-USSR for inventions and discoveries M3035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 FIG.