SU1265779A1 - Device for simulating faults and failures of digital computer - Google Patents

Abstract

The invention can be used in computing for testing and debugging software and hardware monitoring, diagnostics and restoring the efficiency of digital computing devices by simulating various types of failures and malfunctions at specified points in time during their work. The purpose of the invention is to expand the functionality due to the possibility of error signals of any duration. The device contains two comparison circuits, one of which, due to the connection of the inputs with the information outputs of the first and second registers, provides a linkage of the time at which the error signal is generated to the multi-bit input signal. A second comparison circuit, by connecting the inputs to the output of the first counter and the information output of the third register, provides a predetermined delay from the above-mentioned point in time, as well as the required repetition period of the error signal in the multiple failure mode. The OR element, by connecting the first and second inputs to the second information input of the device and the output of the first comparison circuit, respectively, controls the first trigger by one bit and (L multi-input input signal, respectively. The required error signal duration is provided by the second counter, the outputs of which are connected to The first 4 contacts of the first switch, which commutes the input N9 to zero the second trigger. The second O switch commutes the reset input of the first trigger, h m is ensured by the repeated failures odnokratnyhi yl mode 1 (;.. of

Description

The invention relates to computing and can be used to test and debug software and hardware monitoring, diagnostics and recovery of digital computing devices to simulate various types of failures and faults at specified points in time during their work.

The purpose of the invention is to expand the functionality of the device by generating an error signal of any duration.

The drawing shows a block diagram of the device.

The device contains the first 1 and second 2 address registers, the register of 3 cycles, the address comparison circuit 4, the cycle comparison circuit 5, triggers 6 and 7, the element OR 8, the first element AND 9, the counter of 10 cycles, the counter 11, the second element And 12, the second 13 and first 14 switches, address output 15 of the digital computer, strobe device input 16, device clock input 17, initial setup input 18 and information output 19.

The device works as follows.

Switch 14 is closed. A reset signal is applied to the input 18 of the device, setting the first 6 and second 7 triggers and the counter 11 to the zero state. In this case, the single signal from the inverse output of the trigger 6 sets the zero clock counter to the zero state, and the zero signal from the direct trigger output 6 enters the second input element And 9, the third input of which receives a single signal from the inverse output of the second trigger 7.

In the first register 1, the addresses fix the current addresses of commands and programs executed by the digital computers, if one of them coincides with the address specified in the second register 2 addresses, the comparison circuit 4 operates, the output signal of which through the OR element B sets the first trigger 6 to one A logical one appears at its direct output and, therefore, at the second input of the AND 9 element. The zero signal received at the first counter 10 from the inverse output of trigger 6 is removed and the first counter 10 starts counting pulses blunt to the clock input 17 of the device. When the code counted on the first counter 10 coincides with the delay code specified on register 3, the comparison circuit 5 operates, the output signal from which, passing through element 9, sets the second trigger 7 to one state. In this case, at its inverse output, a logical O is established, which is fed to the third input of the element AND 9 and prohibits further passage of signals through it. Single signal from direct

The 5 outputs of the trigger 7 are fed to the output 19 of the device, which corresponds to the beginning of the appearance of the error signal. At the same time, the same signal arrives at the first input of the And 12 element and allows the passage of pulses from the clock input 17 of the device through the And

12 to the counting input of the counter 11. Counter 11 and the second switch

13determine the type of generated error signal corresponding to the simulation of a malfunction or failure, as well as the duration of the failure. When the device operates in the mode of generating error signals to simulate failures of a small

0 of the duration, the movable contact of the switch 13 is closed to the output of the low bit of the counter 11. After the start of the counting, a single signal appears at the output of the low bit of the counter 11, which is fed to the zeroing input of the counter 11 and the second trigger 7. At the same time, the second trigger 7 and, respectively, at the output 19 of the device is set

0 is a zero signal that determines the time of the end of the simulated failure. The same signal prohibits further passage of the counting pulses through the element 12 to the counter 11. In the case

5, the single-fault simulation switch 14 remains in the closed position. In this case, a single signal from the output of the counter 11 is also fed to the zeroing input of the first trigger 6,

0 a zero signal from the direct output of which prohibits the passage of signals through the three-input element 9, and the signal from the inverse output of the first trigger 6 embraces the first counter

5 50. The system returns to its original state and the next failure can be simulated only when the signals at the device input reappear.

In the case of generating error signals to simulate repeated failures, the second switch 14 is open. In this case, the signal to zero from the output of the counter 11 to the first trigger 6 is not received. The 10 clock counter continues to run until it overflows, it zeroes out and when the counted code repeatedly coincides with the one specified in the third register 3, a single signal appears again at the output of the comparison circuit 5, which, passing through the AND 9 element, again sets the second state to one. trigger 7, from the direct output of which an error signal again arrives at the device output 19. The error period of the error signals of repeated failures is determined by the digit of the counter 10 and is equal to, where T is the period of the pulses at the input 17 of the device; h number of bits

To simulate failures of an increased duration, the movable contact of the switch 1 3 closes, for example, to the output of the higher bits of the counter 11. The increased duration of the fault is provided by a later occurrence of 1 at the output of the higher bit compared to the output of the lower bit of the counter 11. To simulate a constant malfunction the moving contact of the first switch 13 is set to the neutral position. In this case, the signal zeroing on the second. trigger 7 is not received and a constant error signal of unlimited duration is saved at the output 19 of the device.

In the case when it is necessary to tie in the moment of forming the error signal to the appearance of a single signal in any of the digital computers circuits available for connection, the input 16 of the device is used. In this case, the first I and second 2 registers and the comparison circuit 4 do not work. The rest of the device is similar to that described.

Claims (1)

Invention Formula A device for simulating failures and malfunctions of a digital computer, comprising first and second address registers, a comparison circuit addresses, clock counter, clock register, clock comparison circuit, first trigger, first AND element, the input of the first address register is connected to the address output of the digital computer, the outputs of the first and second address registers are connected to the first and second inputs of the address comparison circuit, counting the input of the clock counter is connected to the clock input of the device, the outputs of the clock counter and clock register are connected respectively to the first and second inputs of the clock comparison circuit, the equality output of which is connected to the first The first input of the first element, the second input of which is connected to the direct output of the first trigger, the inverse output of which is connected to the reset input of the clock counter, characterized in that, in order to expand the functionality by generating an error signal of any duration, a second trigger is inserted into the device , the OR element, the counter, the second element AND, and two switches, the output of the equality of the address comparison circuit, is connected to the first input of the OR element, the second input of which is connected to the device's input, element OR is connected to e: the single input of the first trigger, the zero input of which is connected to the fixed contact of the first switch, the moving contact of which is connected to the reset input of the counter and the zero input of the second trigger and connected to the input of the initial installation of the device of the single input of the second trigger connected to the output of the first And, the third input of which is connected to the inverse output of the second trigger, the direct output of which is connected to " the first input of the second element And is the information output of the device, the second input and the output of the second element And are connected respectively to the clock input of the device and the counting input of the counter, the discharge outputs of which are connected to a group of fixed contacts of the second switch, the movable contact of which is connected to the beginning input device installation.