SU1164715A1 - Device for simulating faults - Google Patents

Abstract

A TROUBLESHOOTING DEVICE, containing two address registers, an address comparison unit, a first clock counting unit, a pulse shaper, the input address group of the first address register is a group of device address inputs, the output groups of the first and second address registers are connected respectively to the first and second groups of inputs the address comparison unit, the counting input of the first clock counting unit is connected to the clock input of the device, and the pulse driver output is the first information output of the device, Distinguished by the fact that, in order to expand its functionality by simulating faults such as short circuit, open circuit, two registrars of code, code comparison block, cycle counter, cycle register, cycle comparison block, fault encoder, address counter were entered into it. , address number register, address number comparison block, second clock counting block, OR element, three AND elements, two malfunction signal conditioners, the input group of the first code register being a group of information inputs The output groups, the output groups of the first code register and the second code register are connected respectively to the first and second groups of inputs of the code comparison unit, the output of which is connected to the counting input of the cycle counter, the output group of which is connected to the first group of inputs of the cycle comparison unit, the second group of inputs that are connected with the group of outputs of the register of cycles, the output of the address comparison unit is connected to the counting input of the address counter, group (L pa whose outputs are connected with the first group of inputs of the number comparison unit ad AIAM second group of inputs of which is connected with the group address number register outputs output address number comparing unit soedanen per- with data input, D) Vågå block counting n clock cycles first with 4 informatsionsh 1M encoder input does not; H JV properly. The second information input of which is connected to the output of the cycle comparison unit and with the information input of the second clock counting unit, the counting input of which is connected to the counting input of the first counting block, that clock, the first, second, third information outputs of the fault encoder are connected respectively to the first inputs of the first , the second, third And elements, the outputs of the first and second counting blocks as follows: these are connected respectively to the second input of the OR element,

Description

the output of which is connected to the second inputs of the first, second, third elements And, the output of the first element And is connected to the input of the first generator of the fault signal, the output of which is the second information output of the device, the output

The second element And is connected to the input of the second fault generator, the output of which is sent to the third information input of the device,. the output of the third element And is connected to the input | pulse yrmirovatel.

The invention relates to computing and can be used in the development of equipment and programs that monitor and diagnose faults. It is known a device for monitoring digital blocks, containing a simulator of combinational circuitry, 1 sectioned for I141 tions in the case of relay-contact fault circuits of type break and short closure1 and in the case of contactless circuits - faults of type O or I at the output of the element ij. However, fault management is performed by a complex logic circuit that is included in the device for controlling digital blocks and performing other functions besides this. In addition, the device is designed to simulate faults of combinational circuits and does not allow simulating faults in external signals of digital computers. The closest to the proposed technical entity is a device for (fault) digital computer 2, generating single pulses of zero potential, containing two address registers, the outputs of which are connected to the address comparison unit, the output of which is connected to the trigger, the transition 1 to a single state when comparing addresses, an estimator and a register of cycles, the outputs of which are connected to a block of comparison of cycles, the output of which through the AND element, the second input of which is the single output trigger a is connected to the pulse driver f2j. However, the moment of inputting faults is determined only by the single address of the digital computer command and the command execution cycle, and the device can only specify one type of failure. The purpose of the invention is to enhance the functionality of the device by simulating faults. type of short circuit and open circuit. The goal is achieved by the fact that the device for simulating malfunctions of a digital computational map, containing two registers of the address, an address comparison unit, the first clock counting unit, the forg pulse generator, where the group of inputs of the first address register is an address group of device inputs, the output groups of the first and second address addresses are connected respectively to the first and second groups g of the address comparison unit inputs, the counting input of the first clock counting unit is connected with a clock input of the device, and the pulse driver output is the first information output of the device, the EIB has two code registers, a code comparison block, a cycle counter, a cycle register, a comparison block clock, fault coder, address counter, address number register, address number comparison unit, second clock counting unit, OR element, three AND elements, two fault signal conditioners, the input group of the first code register is a group of information inputs of the device, the output group of the first the code register and the second code register are connected respectively to the first and second groups of inputs of the code comparison unit, the output of which is connected to the counting input of the loop counter, the group and whose inputs are connected and with the first group of inputs of the cycle comparison block, the second group of inputs of which is connected to the output group of the cycle register, the output of the address comparison unit is connected with the counting input of the address counter, the output group of which is connected with the first group of inputs of the number comparison address block, the second group of inputs connected to the group of outputs of the register of the number of addresses, the output of the block of comparison of the number of addresses is connected to the information input of the first block of clock counting and the first information input of the fault generator It is the second information input of which is connected to the output of the cycle comparison block and to the information input of the second clock counting block, the counting input of which is connected to the counting input of the first clock counting block; the first, second, third information outputs of the fault encoder are connected respectively to the first the inputs of the first second, third elements AND, the outputs of the first and second blocks of counting cycles are connected respectively to the first and second input of the element OR whose output is connected to the second inputs of the first, second, third About elements And, the output of the first element And is connected to the input of the first generator of the fault signal, the output of which is the second information output of the device, the output of the second element And is connected to the input of the second generator of the fault signal, the output of which is the third information input of the device the output of the third element And is connected to the input of the former and pulses. FIG. 1 shows a block diagram of the proposed device; on. FIG. 2 is a block diagram of the fault encoder. The device contains the first and second registers of addresses I and 2, connected 154 nge with. the address comparison unit 3, the address counter 4, the register of the number of addresses 5 connected to the comparison unit of the number of addresses 6, the first and second registers of code 7 and 8 connected to the comparison unit of code 9, the cycle counter 10, the register of cycles 11 connected to the comparison unit cycles 12, the fault coder 13, the first and second blocks of the clock counting 1A and 15, connected via the IL 16 element with the three elements And 17, 18, and 19 connected to the first and second malfunctioning signal generator 20 and 21, and the pulse shaper 22, clock count block 14 contains trig ep, clock counter and register bars connected via bars with the comparator element I. Counter inputs 14i cycles counting unit 15 are connected to a clock input of the device. The information input of the first counting block of the tact device 14 is connected to the output of the block for the comparison of the number of addresses and the first information input of the fault coder 13, the information input of the second block of the clock cycles 15 is connected to the second information input of the fault coder 13, the outputs of the blocks of the clock count 14 and 15 are connected to the first and second blocks input element OR 16, respectively. The device works as follows. When preparing a device for operation, the group of address inputs of the first register of address 1 connects to the transmission circuits of the address of commands, the information input of the first register 7 of the code is connected to the transmission of code words. The clock input of the device is connected to the even inputs of the counting blocks as 14 and 15 and is connected to the clock generator. Outputs, devices are connected to the selected point of the digital computer circuit, or to external connections of digital computers, in which it is necessary to simulate a fault. In the initial state, the first register is 1 addresses, the counter is 4 addresses, the first register is 7 codes, the counter is 0 cycles, the trigger and the counter are in the pen and the second blocks of the counts 4 and 15 are reset; the second register 2 addresses, the register 5 of the number of addresses, the second register 8 of the code, the register of 11 cycles, the fault coder 3, the registers in two blocks of the clock counts 14 and 15 are in an arbitrary state. To introduce a specific malfunction in the desired clock cycle and command execution cycle or transfer the specified code Yctanavlivac initial conditions: in the second register 2 addresses - the address of the command, in register 5 of the number of addresses - the code word, in the register I1 cycles - the number of repetitions of the code word in the fault coder 13 - the type of malfunction when the above conditions are fulfilled; in the registers of cycles of each block of the cycles 14 and 15 - the number of cycles. Initial conditions are set manually by the switches before starting work. When programs are executed) at a certain point in time, an address equal to the address recorded in the second address register 2 is recorded in the first address register 1; At the output of the address comparison unit 3, a comparison signal appears, which is fed to the address counter 4. Counter 4 addresses starts counting the addresses of the DVR commands. If the number of addresses in the counter is 4, the address is equal to 4 and the number of addresses in register 5, the comparison circuit 6 outputs signals to the fault coder 13 and to the first block of clock counts 14. At the same time, when transmitting code words via external communications, a digital computer can ., to be simultaneously with the output the returned address) the code word in the first register of the 7 code becomes equal to the code word in the second register 8, then the comparison block of code 9 generates a comparison signal that goes to the counter of 10 cycles. The counter of 10 cycles starts counting the transmission cycles of the specified code. In case of equal number of cycles in the cycle counter and in the register I1 of cycles of the circuits of comparison 12, a signal is sent to the encoder malfunction 3 and to the second clock count block 15. Under the influence of signals from the comparison block of the bis addresses of the comparison block 12, received at the information inputs the first and second blocks of the clock ticks 14 and 15. a signal is formed at the output of, (, de blocks of the clock ticks 14 and 15, which goes to the element OR 16. In the case of a signal from either or from both blocks of the clock ticks 14 and 15, OR 16 gives a signal to the element And you are 17, 18 and 19. When the signal comes from the fault malfunction 13 and the element OR 16 on the element I 17, the first driver of the signal for health 20, which simulates an open circuit, is triggered, and on receipt of signals on the element And 18, the second driver of the fault signal 21 , imitating short circuit: e, when signals arrive at element And 19, pulse shaper 22 is triggered, imitating a single impulse of zero potential, affecting the selected point of the circuit, which is perceived as a fault at this point ( olozhitelny substitutions signal -; is zero). Thereafter, the device is reset (the installation circuits are not shown in the drawing), and is prepared for the next malfunction task. It is proposed to use units of comparable type of serial adders modulo two signals from the counter and register- (or two registers), and the outputs of the adder are combined by an AND element, using normally open electronic switches and simulating a break, when the output impedance of the former 20 becomes infinitely large, and normally closed - to simulate a short circuit, respectively. The fault coder 13 is six switchable switches that connect the output of the compare block of cycles 12, or the output of the block of the comparison of the number of addresses 6 with one or more circuits (17, 18, and 9). An example of the implementation of the schemes of the fault coder can be considered as an example, which is shown in FIG. 2 .. The fault coder can be a set of six toggle switches 23-28 and three elements OR 29, 30 and 31. By means of toggle switches 23-28, before starting, the outputs of the quantity comparison unit

addresses 6 and the outputs of the comparator cycles 12 are connected through the elements of the IPs 29, 30. and 31 and the elements 17, 18 and 19 to the inputs of the first 20 and second 21 switches and to the pulse shaper 22. Thus, it is possible to specify three types of faults by matching address or the same faults by matching the cycle code.

For example, by switching on the toggle switches 25, 26, and 28, according to the coincidence of the addresses in the comparison block, the number of addresses 6 simulates 2 types of faults — open circuit (first switch 20) and short circuit (second switch 21). The short lock is also simulated by the coincidence of the 1fl codes in the comparison block of cycles 12. By the coincidence of the cycle codes in the comparison block of cycles 12 also

11647158

simulates impulse interference form the global impulse maker 22.

Introduction to the device for simulating faults of the address counter 4, the register of the number of addresses 5, the compare block 6, the registers of code 7 and 8, the compare block of codes 9, the counter 10 and the register of 11 cycles, the compare block of cycles 12, the fault coder 13, switches 20 and 21 provides a reduction in the time of complex debugging of programs due to the increased accuracy of the time when various types of faults are introduced into the digital computers and its external

communication, which allows an accurate assessment of the behavior of the digital computer and its associated devices in the presence of specific malfunctions, and consequently, improve the quality and reduce the time required for equipment and software testing.

From block S compare the number of addresses

On the element H17 On the element Ya18 On the elements

fPus.2

S5lok 12 leveled cycles

Claims (1)

A device for simulating malfunctions, comprising two address registers, an address comparison unit, a first cycle counting unit, a pulse shaper, wherein the group of inputs of the first address register is a group of address inputs of the device, the output groups of the first and second address registers are connected respectively to the first and second groups of inputs of the block address comparison, the counting input of the first block of the clock count is connected to the clock input of the device, and the output of the pulse shaper is the first information output of the device, different which, in order to expand its functionality by simulating faults such as short circuit, open circuit, two code registers, a code comparison unit, a cycle counter, a cycle register, a cycle comparison unit, a fault encoder, an address counter, a quantity register are introduced into it addresses, a unit for comparing the number of addresses, a second clock counting unit, an OR element, three AND elements, two fault signal generators, and the group of inputs of the first code register is a group of information inputs of the device, groups The outputs of the first code register and second code register are respectively connected to the first and second groups of inputs of the code comparison unit, the output of which is connected to the counting input of the loop counter, the group of outputs of which is connected to the first group of inputs of the cycle comparison unit, the second group of inputs. which is connected to the group outputs of the register of cycles, the output of the address comparison unit is connected to the counting input of the address counter, the group of outputs of which is connected to the first group of inputs of the address number comparison unit, the second group is the input of which is connected to the group of outputs of the register of number of addresses, the output of the unit for comparing the number of addresses is connected to the information input of the first, first cycle counting unit and to the first information input of the fault encoder, the second information input of which is connected to the output of the loop comparison unit and with the information input of the second block counts of clocks, the counting input of which is connected to the counting input of the first block of counts, those clocks, the first, second, third information outputs of the fault encoder are connected respectively with the first inputs of the first, second, third AND elements, the outputs of the first and second blocks of the count clock are connected respectively to the first and second inputs of the OR element, SU ... 1164715 whose output is connected to the second inputs of the first, second, third elements And, the output of the first element And is connected to the input of the first driver of the fault signal, the output of which is the second information output of the device, the output of the second element And is connected to the input of the second driver of the fault signal the output of which is the third information input of the device,. the output of the third element And is connected to the input of the pulse shaper.