SU1536387A1 - Device for simulation of faults - Google Patents

Abstract

The invention relates to digital computing and can be used in the development of diagnostic computer tools. The purpose of the invention is to expand the functionality of the device by introducing different types of faults in arbitrary order into arbitrary moments of time adjustable to the clock. An introduction to the device to simulate faults, containing registers, comparison circuits, a counter, fault formers of an RS-flip-flop, JK-flip-flop, D-flip-flop, switch block, AND and OR circuits, registers, and clock comparison circuits with links provides an arbitrary adjustable the order of submission of the issuance of different types of fault signals with adjustable moments of the issuance of these signals, which are accurate to the clock cycle. 4 il.

Description

The invention relates to computing, in particular, can be used in the development of equipment and programs that monitor and diagnose faults.

The aim of the invention is to extend the functionality of the device to simulate faults by eliminating the limitations in setting the time points for fault insertion, the sequence for introducing the type of faults and the time intervals between them.

FIG. 1 is a block diagram of a device for simulating faults; figure 2 - timing diagrams illustrating the operation of the device;

3, an example of the construction of the circuit of the second block of switches; on the example of construction of the scheme of the first block of switches.

The device for simulating faults contains the first 1 and second 2 address registers, address comparison block 3, address counter 4, address number register 5, address comparison block 6, first 7 and second 8 code registers, code comparison block 9, 10 cycles counter, register 11 cycles, cycle comparison block 12, first element OR 13, RS trigger 14, third element 15, second element 16 or 16, counter 17 cycles, first register 18 cycles, first cycle comparison block 19, even

with about

00 00

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second element 20, D-flip-flop 21, IK-flip-flop 22, second 23 and third 24 clock registers, second 25 and third 26 clock comparison blocks, second switch block 27 first 28 and second 29 And blocks (pulse shaper 30, drivers 31 and 32 fault signals and the first block of 33 switches., The switch blocks (Fig 3 and 4) contain switches 34-36 and 37-39 „

The device works as follows.

In preparing the device for operation, the group of address inputs of the first register 1 of the address is connected to the transmission circuits of the address of commands, the group of information inputs of the first register

7 code is connected to the code word transmission circuit. The clock input of the device is connected to a clock generator. The outputs of the device are connected to the selected point of the digital computer circuit or to external connections of the digital computer in which it is necessary to simulate a fault. In the initial state, the first register of the 1 address, the counter of the 4 address, the first register of the 7 code, the counter of 10 cycles, the RS flip-flop, the D-flip-flop, the IK-flip-flop, the counter of 17 cycles reset to zero, the second register 2 of the address, the register

5 number of addresses, second register

The 8 codes, the register of 11 cycles, the registers of 18, 23, and 24 cycles are in an arbitrary state determined by the task of debugging the user of the device.

To add a specific fault or chain of faults in the desired cycle or after executing the required number of commands. a certain address sets the initial conditions after the required number of cycles and at predetermined intervals between the moments of fault insertion: in the second register 2 addresses are the address of the command, in register 5 the number of addresses is the number of repetitions of addresses, in register 7 codes the code word, in register 11 cycles - the number of repetitions of a code word, in the register of 18 clocks the number of clock ticks to the introduction of the first malfunction from the moment of appearance of the desired cycle or the number of repetitions of addresses, in the register of 23 clocks - the number of clock ticks from m ment introducing first abnormality until introducing second abnormality in the register 24 cycles - number of cycles

0

five

0

five

0

five

0

five

0

five

between the second and third faults, the order of issue of fault types is entered into the switch block 27

Initial conditions are set by manual switches before starting work. When the program is executed at certain points in time, the first register 1 of the address records the address equal to the address recorded in the second register 2 of the address. A comparison signal appears at the output of the address comparison block 3, which arrives at the counter 4 of the address. compared with the set in the initial conditions. In case of equal number of addresses in the counter 4 addresses and in the register 5 of the number of addresses, the comparison circuit 6 outputs a signal to the OR circuit 13 and the generation time condition for the number of specified addresses performed is fixed by the RS flip-flop 14, i.e. 1 and at its direct output a level equal to „

The signal 1 is fed to the first input of the element 15, the second input of which receives the signal 1 from the inverse output of the D-flip-flop and the output from the element 15 allows the clock counter to be counted. The signal 1 from the direct output of the RS-flip-flop 14 goes to the enabling input of block 19 comparing clocks and allows comparing the contents of the counter 17 clocks with the contents (given the initial condition.m) of the first register 18 clocks. At zero register contents 18 clocks, the counter of 17 clocks counts FT pulses arriving at its counting input from the clock generator output, and when The counting of the contents of the counter is 17 clocks and the contents of the register is 18 clocks. The signal from the output of block 19 is compared to the input of the element I 20, the other output of which is opened by a high level signal from the inverse output of the IK trigger 22. The high signal from the output of the element 20 goes to D - input of D-flip-flop 21 and with the appearance of the first positive difference of the clock pulse FT arriving at the clock input, ORHOT active D-flip-flop 21 switches to one state. The high level signal from the output of D-flip-flop 21 is fed to the I-input two jk-trigger

pa 22, which switches to the single state when the nearest negative differential of the FT pulse arrives at its sync input 0

The inverse output of the IK-flip-flop by a low level removes a high level from the D-input of the D-flip-flop 21 "through the element 20. Thus, at the direct output of the D-flip-flop 21 a high pulse with a duration of one cycle is formed, through which OR 16, the counter of 17 clocks is zeroed, and the pulse from the inverse output of D-Trigger 21 is prohibited for the time of zeroing through the element. And 15 counting pulses counter 17 cycles. A single output of the L-flip-flop 22 permits operation of the blocks 25 and 26 of the comparison of ticks. A delay of 1/2 tick switches to the 1K-flip-flop of the unit of state relative to the D-flip-flop eliminates false triggering of the blocks 25 and 26 of the comparison of the ticks during transients when the counter is reset to zero 17 clock pulses from the D-flip-flop 21 "The single output of the IK-flip-flop is fed to the input of the block 33, the output of which appears

a combination of signals that determines the types of faults that will be generated in a given program start. The signal from the first output of the block 33 enters the input of the second element I 28, from the second output to the input of the first element I 29, from the third output to the input of the block 27 "Using the block 27 it determines the sequence in the time of entering the faults. block 27 is shown in, and in fig. 4 a variant of construction of the block 33 is shown. Manual switches can be used as switching elements.

In the example shown in Figs. 3 and 4, block 33 sets all three types of faults, block 27 sets the order of issuing fault signals in the order shown in Fig. 2, and the fault conditioner 31 generates a Short Circuit, shaper 32 - Open, shaper 30 - single pulse.

Figure 2 shows a time diagram of the generation of a chain of faults after repeating a certain specified number of addresses with a delay of the first fault relative to

Q 0 0

about

0

e

five

but the operation of block 6 of the comparison of addresses for 5 clocks, the second relatively V first and third relative to the second by the number of clocks listed in blocks 23 and 24 of the register of clocks, i.e. after counting the first time interval before the first fault is issued, the 17 clock counter is zeroed and starts the clock count until the second and third faults are issued. The moments of signaling faults are determined by the pulses that occur at the input of blocks 25 and 26 of the clock comparison when the contents of the counter of 17 clock cycles compare with the value of the number of clock cycles specified in the registers 23 and 24 clock cycles.

The counter 17 in the proposed device is used twice in one program start. / After the last fault signal was issued by an external signal, the Setting 0 device is reset to the initial state (traditional setting circuits, not shown in Fig. 1) and is prepared for the next malfunction task.

For comparison blocks, it is proposed to use modular two modulo adders such as the outputs of the adder are combined by circuit I. It is proposed to use electronic commutators, which in two opposite states, change the output resistance from zero to infinitely large

As a pulse shaper, any scheme such as a delayed multivibrator, a pulse normalizer, etc. can be used.

Introduction to the device to simulate faults RS-flip-flop 14, D-flip-flop 2.1, IK-flip-flop 22, block 27, blocks 19, 25 and 26 comparison of ticks, registers 18, 23 and 24 ticks, elements OR 13 and 16, elements AND, 15 and 20 reduces the time required for complex debugging of programs, which means that it is possible to introduce different types of faults in arbitrary order into arbitrary moments of time that are adjustable to the same clock rate, which allows to improve the quality of diagnostic computer diagnostic tools;

Claims (1)

Invention Formula Device for imitation of faults, containing two registers of addresses, address comparison block, address number register, address counter, address number comparison block, code register, comparison block K (), loop counter, cycle- register, cycle comparison block, two ele - i-device AND, two fault signal drivers, a pulse driver, the output of which is the first information output of the device, the first block of switches, the OR element and the clock counter, the group of inputs of the first address register is a group sing unit address inputs, outputs group the first and second address registers are connected respectively to the first and second groups of inputs of the address comparison block, the input group of the first cfd register is a group of information inputs of the device, the output group of the first and second code registers are connected, respectively, by the first and second groups of code comparison block inputs, the output of which is connected to the counting input of the Cycles counter, the output group of which is connected to the first group of inputs of the cycle alignment unit, the second group of inputs of which is connected to the output group p cycles hysteres, the output of the Address comparison block is connected to the counting Input of the address counter., the output group of which is connected to the first group of inputs of the comparison number of addresses, the second group of inputs of which is connected to the output group of the address number register, the first and the Blind outputs of the first switch block are connected respectively, with the first inputs of the first and second elements And, the output of the first element And g is connected to the input of the first fault generator, the output of which is the second information in The output of the device, the output of the second element I is connected to the input of the second generator of the malfunction signal, the output of which is the third information output of the device, which is different in that, c. the purpose of extending the functionality by removing the restrictions on setting the time points of malfunctions, the sequence of insertion of the type of malfunction and the time intervals between them; it contains the second element OR, RS trigger, TC trigger, D trigger, the third and fourth AND elements, three blocks of comparison of the number of ticks, the second block of switches, three registers of the number of ticks the output of the number of addresses comparison block is connected to the left input of the first OR element, the output of the cycle comparison block is connected to the second input of the first OR element, the output of which is connected to the S input of the RS flip-flop, the forward output of which is connected to the first input One of the third element And, the second input of which is connected to the inverse output of the D-flip-flop5, the direct output of which is connected to the I-input of the IK-flip-flop, whose sync input, the counting input of the clock counter and the clock input of the D-trigger enable the input the clock counter is connected to the output of the third element AND, and the zero input is connected to the output of the second OR element, the first input of which is connected to the direct output of the D-flip-flop., the second input of the second OR element, the R-input of the RS-flip-flop, K-input IK -trigger connected to the installation input into the device O, the D input of the D flip-flop is connected to the output of the fourth element I, the first input of which is connected to the output of the first clock comparison unit; the first group of inputs of which is connected to the output group of the first register of the number of cycles, and the second group of inputs, the first groups the inputs of the second and third blocks of the comparison of the number of clock cycles are connected to the output group of the clock counter, the second groups of inputs of the second and third blocks of the comparison of the number of clock cycles are connected to the output groups of the second and third registers of the number of clock cycles Respectively, the enabling inputs of the second and third blocks of the number of cycles and the input of the first switch block are connected to the direct output of the IK flip-flop, the third output of the first switch block is connected to the first input of the second switch block, the second and third inputs of which are connected to the outputs of the second and third blocks comparing the number of cycles, respectively, the first output of the second block of switches is connected to the second input of the second element AND, the second output to the second input of the first element AND, and the third output to the input of the pulses ovatel allowing input of the first block comparing cycles connected to the direct output of the RS flip-flop, the second input of the fourth element I is connected to the inverse output of the IK-flip-flop. Set ZG Ottomans ppppppppppppppppppppp-ppppp-pppg Dr. My Quit C - Trigger Send my 3ti-trigger output Output 5/7 about 3 Rjl Lr my bbtxoff rs-trigger Blon exit / 3 8woffHff3u. $ exit „impulse Exit ti Oyor breather 6 l 25 exit 76 P P P FIG. 2 Fu.Z 38 On TO 59 On Section 18 57 On bull N ..J