SU1562919A1 - Device for simulation of malfunctions and troubles of digital computer - Google Patents

Abstract

The invention relates to computer aids and can be used in setting up equipment and debugging programs. The purpose of the invention is to increase the reliability of the device by eliminating unauthorized signals at its output, as well as expanding the field of application. The device contains blocks 1 and 2 of deciphering the initial and final conditions, triggers 3-5 and element 6. It is possible to use the device in synchronous and asynchronous processes, since the duration of the fault is not determined in advance by the number of computer clock cycles. 2 Il.

Description

The invention relates to computer facilities and can be used for debugging equipment and programs, as well as for training Per-Sonal, computer maintenance services, for diagnostics of a Computing system in the event of a malfunction or failure during the operation of a computing system.

The aim of the invention is to improve the reliability of the device by eliminating unauthorized signals at its output and expansion

its field of application due to the possibility of imitation of digital computer failures during asynchronous operation modes.

FIG. 1 shows a general diagram of a device for simulating failures and malfunctions of a digital computer; FIG. 2 is a block diagram of the decoding of the final conditions of imitation.

The device (Fig. 1) contains the decryption blocks of the initial 1 and final 2 simulation conditions, the first 3, the second 4, and the third 5 triggers, element 6, taKTOBbtf input 7 and input 8 of the device reset.

Block 2 (figure 2) contains the elements NOT 9, the switches 10 and the element And And.

The device works as follows

In the initial state, the reset circuit switch is in the Earth position. All device triggers are reset. At the output of element 6 there is a logical one. At the input of blocks J and 2, the selected signal is switched from the digital circuits available for connection. An element output, AND 6 is connected to a suppressed signal or to another malfunction signal conditioner. Actual input 7 is switched with signals of an unsupported clock series. Digital computer The device reset circuit switch is set to the Open position. Thus, triggers can be triggered when information signals arrive at their inputs. The trigger 5 is set to 1 if during the switching of the reset circuit of the device, the block 1 decrypts the initial conditions and the block 2 decrypts the end conditions do not recognize either the initial or the end conditions of the operation, which prevents

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switching element 5 on or off. After trigger 5 is set, if unit 1 recognizes the initial trigger conditions, trigger 3 is set to 1 and a logical O appears at the output of element 6, which corresponds to the beginning of the fault.

Trigger 4 is set to 1 (O at the inverse output) after setting the triggers 3 and 5 under the condition that unit 2 recognizes the final trigger conditions and switches element 6 (the logical unit at the output of element 6), which corresponds to the end of the fault.

Claims (1)

Invention Formula A device for simulating failures and malfunctions of a digital computer, comprising a decryption block for initial simulation conditions, a decryption block for imitation end conditions, first and second triggers, AND element, the inputs of decryption blocks for initial and final simulation conditions being information inputs of the device, the initial conditions of the simulation is connected to the first information input of the first trigger, the first output of the decryption block of the final conditions of the simulation is connected to the first information the second trigger input, the inverse output of which and the direct output of the first trigger are connected respectively to the first and second inputs of the element I, the device reset input is connected to the reset inputs of the first and second triggers, characterized in that, in order to increase the reliability of the device by eliminating unauthorized signals at its output and expansion of its application area, due to the possibility of simulating digital computer failures during asynchronous operation, it contains a third trigger, the direct output of which is connected to the second by the first and second trigger trigger inputs, the first and second third trigger information inputs are connected to the second outputs, respectively, of the decryption block of the initial simulation conditions and the decryption block of the final simulation conditions, the synchronization inputs of the first, second and The device's input input, the reset input of which is connected to the reset input of the third trigger, the forward output of the second trigger input, the inverse output of the And element is the output of simulating device failures. Fg / r2