SU1660231A1 - System with redundancy and delay - Google Patents

Abstract

The invention relates to automation and can be used to build discrete devices with increased reliability. The purpose of the invention is to increase the stability of the device while expanding its functionality - by introducing D-flip-flop 13, set-up unit 15, one-shot 11, OR-NOT element 14. The device also contains redundant devices 1, 2, registers 3, 4 shifts, adder 5 modulo 2, ICK-trigger 6, 7, elements AND 8 - 10, element OR 12, input 16 discrete devices, bus 17 synchronization, output tires 18, 19. 1 Il.

Description

The invention relates to automation and can be used to build discrete devices with increased reliability.

The aim of the invention is to increase the stability of the operation of the device while expanding its functionality.

The drawing shows a diagram of the duplicated system with a delay.

The duplicated system with a delay contains two redundant devices 1.2, two shift registers 3.4, an adder 5 modulo 2, two 1SK-triggers 6.7, three elements AND 8-10, a one-shot 11, element OR 12, a D-trigger 13, the element OR NOT 14, the installation unit 15, the input of 16 discrete devices, the bus 17 synchronization, the output bus 18, 19.

As a D-flip-flop, synchronous triggers can be used that switch at the clock cut.

The purpose of the input elements:

one-shot 11 - to form a pulse in case of failure of one of the discrete devices of the 1st or 2nd,

unit 15 is for setting the flip-flops in the O state and may contain a capacitor and a charging resistor;

D-flip-flop 13 - to form a logical 1 in the event of a failure of the second discrete device 2 and a logical O in the failure of the first discrete device 1;

the OR-NO 14 element is for signaling the failure of the second ICK trigger 7 (logical O at its forward and inverse output), leading to the failure of the entire device.

The duplicated delayed system works as follows.

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When the power is turned on, the triggers 6, 7, 13 are set to the O state by applying a high level signal to the S inputs and a low level signal to the R inputs, since the capacitor of the unit 15 is discharged. As the capacitor charges through the charging resistor of the installation unit 15, the triggers 6, 7, 13 are prepared for operation via control inputs (the S R 1 signal appears on the setup inputs).

In the normal mode of operation, when both discrete devices 1.2 are operational, the processed information is sequentially recorded in the shift registers 3 and 4 on the falling edge of the pulses from the bus 17, i.e. the accumulation of the time reserve is made and the triggers 6, 7, 13 are installed in the O state, so after filling the registers 3, 4 the information on the output of the device will come from the second shift register 4 through the element 9 (at the second input of which the logical 1 second inverse trigger output 7) and element OR 12. In this mode, the output of the adder 5 will be logical O, since both devices 1,2 are healthy, which ensures maintenance of the 1SK-6.7 trigger in the zero state, and hence the transmission of information from the device 2

In the event of a failure of the elements of the device 2, an open or short circuit, which leads to the appearance of stable false information at its output in the form of logical O or 1 at the output of the adder 5, 1 appears, which is written to the trigger 6 by the pulse 17 output, allowing passing the logical 1 from the output of the O-flip-flop 13 to the I input of the flip-flop 7 through the element-10. At the same time, the one-shot 11 is triggered, the output of which generates a pulse of less duration than the time created using shift registers 3 and 4, which should be determined according to the maximum possible series of consecutive 1 and O at the output of discrete devices 1.2. From the output of the single-vibrator 11, logical 1 is applied to the D input of the flip-flop 13 and at the instant of decay (i.e. on the cut) of the pulse at the output of the discrete device 1 translates the flip-flop 13 into one state. As a result, logical 1 appears at the output of AND 10, which is written down by trigger pulse 7 from the bus 17 to trigger 7, which switches the device bus 18 to the healthy output of the first discrete device 1, feeding logical 1 to the second input of the first And 8 element and logical O to the second input of the element I 9.

If the first discrete device 1, which manifests itself in the form of stable false information at its output -logical O or logical 1, fails, the trigger is set to one state; a single pulse is generated at the output of the one-shot 11 in the same way as if the second discrete device 2 fails however the output of trigger 13 is logical

0 1 will not be, since at its synchronizing input C there will be no drop of the pulse from the output of the first discrete device 1, and the D-flip-flop 13 is triggered by a pulse cut at the synchronizing input.

5 Therefore, at the output of the element And 10, a logical O will be saved and the trigger 7 will save the zero state and information will be transmitted to the output of the device from the output of the working discrete device 2

0 through the shift register 4 and the elements AND 9 and OR 12. The element OR NOT 14 fixes the failure of the trigger 7 (logical O at its forward and inverse outputs), leading to the failure of the entire device, and reduces

5 average recovery time of the operational state of the duplicated system with a delay.

Claims (1)

Claims of the invention Duplicate system with a delay, 0 containing two redundant discrete devices, the inputs of which are combined and connected to the input bus, and the outputs are connected respectively to the control inputs of the first and second registers 5 shifts, the outputs of which are connected to the first inputs of the first and second And elements, respectively, whose outputs are connected respectively to the first and second inputs of the OR element, the output of which 0 is the output of the device, the outputs of the first and second redundant discrete devices are connected respectively to the first and second inputs of the modulo-2 adder, the output of which is connected to the 1-input 5 of the first ICK flip-flop, the direct output of which is connected to the first input of the third element I, the output of which is connected to the 1-input of the second ICK flip-flop. the direct and inverse outputs of the latter are connected to 0 by the second inputs of the first and second elements, respectively; And, To the inputs of both SC triggers are connected to the common bus; the sync bus is connected to the clock inputs C of the first and second shift registers and the first and second ICK triggers, increase the stability of the device while expanding the functionality introduced D-trigger unit installation one-shot, element OR-NOT, the clock input C of the D-flip-flop is connected to the output of the first discrete device, a D input is connected to the output of the one-shot, the input of which is connected to the output of modulo 2 adder, the direct output of the D-flip-flop is connected to the second input of the third element And, the first output block The installation is connected to the S installation inputs of all three flip-flops, the installation inputs F of which are connected to the second output of the installation unit, the direct and inverse outputs of the second ICK flip-flop are connected respectively to the first and second inputs of the OR-NOT element, the output of which is the device alarm output.