SU1457147A1 - Device for monitoring redundancy generator - Google Patents

Abstract

The invention relates to devices of pulsed technology and can be used in synchronization devices when reserving by replacing common-mode frequency generators. The purpose of the invention is to increase the reliability of monitoring signals from a redundant generator. The device containing the element 1, the counter 5 pulses, the generator 6 pulses, the driver 9 of the switching signals controlling the failure to zero, the driver 7 of the diagnostic sequence and the driver 8 of the reference diagnostic sequence are entered. This allows you to further control failures to a logical unit in all channels of the output buses. The description provides examples of the execution of a diagnostic sequence generator 7, a reference diagnostic sequence generator 8, and a switching signal generator 9. 3 з.п, ф-л, 10 Il. i cl

Description

four

SP

u

2 3 v

(fiue.i

20

25

The invention relates to automation and impulse technology and can be used in synchronization devices when replacing; common-mode frequency generators.

The aim of the invention is to increase the reliability of monitoring the signals of the redundant generator by increasing the completeness of monitoring (detection of failures to logical 1 in all channels of output common-mode frequency gains) and the redundant generator.

Fig, 1 shows a block diagram 15 of the device; FIG. 2 is a diagram of a diagnostic sequence former; Fig, 3 is a diagram of the reference diagnostic sequence; FIG. 4 is a switching driver circuit; Figures 5 and 10 are voltage diagrams explaining the operation of the device.

A device for monitoring a redundant generator (Fig. 1) contains an element AND 1, whose inputs are connected to input terminals 2-4 of the common-mode frequencies of a redundant generator, and the output is connected to the installation input of a pulse counter 5, the counting input of which is connected to a generator of 6 pulses . The inputs of the imaging unit 7 diagnostic sequence (LP) is connected to the corresponding input buses 2-4 in-phase 35 tfacTOT, and the reset input is connected to the output element And 1, Each input of the imaging unit 8 diagnostic sequence (FELP) connected to the outputs of the corresponding bits 40

counter 5 pulses. First entry. the driver 9 of the switching signals (FSP) is connected to the output of the element I 1, and the second and third inputs are connected to the outputs of the FEDP 8 and LDP 7 45, respectively,

“LDP 7 contains n inputs (according to the number of input units of the device, in FIG. 2, so far three inputs), n-1 channels 7.1 and 7.2, each of which includes 50 first D-flip-flop 10 (10.2) The inverse output of which is connected to the first input of the element, 1 (11.2) and to the input of the installation of the second D-flip-flop 12.1 (12.2), the direct output of which 55 is connected to the second input of the element 11.1 (11.2), D-inputs both triggers are connected to the zero potential bus, the synchronization input is first

five

;

five

0 5 0

five

0 5

th D-flip-flop 10.1 (10.2) is connected to the corresponding input bus and through the inverter 13.1 (13.2) - to the synchronization input of the second D-flip-flop 12.1 (12.2), the outputs of the elements And 11, 1 (11.2) is connected to the corresponding inputs of the OR 14 element, the synchronization input of the additional D-flip-flop 15 is connected to the pth bus, the D-input is connected to the zero potential bus, the inverse output is connected to the corresponding input of the OR 14 element, whose output is output dp 7, the reset input FDP 7 through the one-shot 16 is connected to the inputs of the unit in the first D-flip-flops of all channels, as well as Dalar D-flip-flop 15, I i

The FZ / U (Fig. 3) contains a decoder 17, whose inputs are the inputs of the forps of the drivers and the outputs through the single vibrators 18.1, 18.2 and 18.3 connected to the corresponding inputs of the element OR 19, the output of which is the output of the imager.

i i

Fig. 4 shows an electrical circuit of the SP 9, which contains a single vibrator 20, the input of which is connected to the first input of the imaging unit, and the output - to the third inputs of the first 21, second 22 And | third 23 And elements, the second input of the imaging device is connected directly and through the inverter 24 with the synchronization inputs of the first 25 and second 26 D-flip-flops, the third input of the driver is connected to the synchronization input of the third D-trigger 27, the inverse output of which is the output of the driver, and the direct output is connected to the second input of the second element And 22, the third the input of which is connected to the inverse; the output of the first T-trigger 25 and the second input of the third element And 2.3, the output of which is connected to the installation input to the unit of the third D-flip-flop 27, whose D-input is connected to the zero potential bus, the output of the second element And 22 is connected to the installation input to the second unit D-flip-flop 26, the D-input of which is connected to the zero-potential bus, and the output to the second input of the first element 21, the output of which is connected to the input of the installation to the O of the first D-flip-flop 25, whose D-input is connected to the logical unit bus.

14

The device for monitoring the redundant generator operates as follows.

"At the output of gaine 2-4, synchronic pulse sequences with different follow-up periods are obtained (plots 1-3 in Fig. 5). At the output of the element And 1 there are pulses with a follow-up period equal to the largest period of the input pulses (plot 4 in Fig. 5). The pulse slices of this sequence are reset to the initial state by a 5-pulse counter, FDP 7, FN.GSHCH 8, FSP 9. FDP 7 forms a sequence of pulses of the lowest frequency and the first pulses of each input sequence after plot zeroing 5 (Fig. five).

FZDP forms a similar sequence of signals arriving at its input from the outputs of the bits of the counter 6 pulses (plot 6 in Fig. 5). Unlike the diagnostic sequence, the pulses in the reference sequence have a variable duration. The duration of the pulse 2 generated by the LEDP at time t depends on the instability of the repetition period of the master signal of the redundant generator (/ ITpr / T pg), the instability of the repetition period of the pulse generator 6 (TTC / TH) and the instant t of the formation of the reference pulse at output "b3 / u 8

(

4Trg

4Thgg.

TrgT.m

) t.

With the permissible frequencies of the signals of the redundant generator and generator 5 of the pulses, the edges of the pulses generated by the FDP 7 are within the range of the vertices of the pulses of the sequence of signals generated by the FEDP (plots 5 and 6 in FIG. B).

The signals from the outputs of the FDP 7 and FEDP 8 are fed to the inputs of SP 9, when the fronts of the pulses taken from the output of the FDP 7 (plot 5 in fig.b) coincide with the tops of the pulses generated by the FEDP 8 (plot 6 in FIG. , b), at the output of the FSP 9 there is a logical level of O (plot 7 in FIG. b). Thus, the signal for switching a redundant generator. missing.

0 5 0

5 0 5

0

B

0 e

474

When reducing (increasing) the frequency of the signals from the redundant generator, coming from the input buses 2-4 of the device by an amount less (greater) than the maximum allowed, the pulses generated by FEDP 8 coincide with the edges of the pulses generated by the FDP 7.

As a result, at the output of the FSP 9, a logic level of 1 is set, which leads to switching the redundant generator to the reserve. Switching the reserve is carried out on the positive difference of the output voltage of the FSP 9.

Let at time points t (plot 7 in FIG. 6) fail to the logical

the signal of the redundant generator arriving at the input bus 3 of the device with normal signals to the second (plot 1) and fourth (plot 3) input signals. If the moment of time takes place before the appearance of the first pulse from the sequence of pulses after the moment of reset (voltage plot 4 at the output of the element I 1) arriving at bus 3, then after the time of the triggering of the PDF 7 Osr, a logic level 1 appears at its output ( apure 5 fig.b). Since the positive differential signal at the output of the FDP 7 (plot 3) in this case does not coincide with the pulse generated by the FEDP 8 (plot 6), the output of the FSP 9 (plot 7 in fig.b) sets the level of logical I, the positive differential of which causes connection of the reserve of the reserved generator. As a result, a normal pulse train appears on the input bus 3 (plot 2 in FIG. 6). Delays associated with transients when connecting a reserve in the FSP 9 and in the device connecting the redundant generator itself, until the device returns to its initial state at time t ffp by cutting the output pulse of the And 1 element (plot 4 las.6) .

Consider the case when a failure in logical 1 occurs after the passage of the first pulse of the input sequence following the device reset point. Plots, po51457

deactivating devices, in this case are shown in FIG. 7,

Let at the moment of time tcTK following the appearance of the first pulse g in the input sequence arriving at the second input of the device, the signal fails in logic 1 (plot 2 on f-, 1G. 7). In this case, the failure of the redundant generator is detected in the next cycle of operation of the device. Indeed, plot 1-5 in FIG. 7 shows that the pulse sequence of the device shown in diagram 15 5 in the cycle of occurrence of a failure is the same as in the case of malfunctioning of the redundant generator (compare diagram 5 in figure 5). In the next cycle of failure of the device 20, there will be no coincidence of the pulse front at the time tcofln formed by the FDP 7 with the pulse forming the FSP 8 (plots 5 and 6 in Fig. 7). At the time t "(, d, at the output of FSP 9, a logic level of 1 is generated, the leading edge of which is a signal to connect the reserve. The time r back of the pulse shear on the second input bus of the device is determined by 30 time between the appearance of a pulse slice at the output of the FEDP 8 and the moment when the pulse slice of the signal sequence on the second input bus appears after switching to the reserve, 35

Fig. 8 shows voltage plots explaining the operation of the FLD 7 circuitry.

The one-shot 16 is triggered by a pulse from the output of the AND 1 element (plot 1). The signal from the output of the one-shot 16 (plot 2) sets the first 10 of each of the p-1 channels 7-1, 7-2 (plots 3 and A) and, additionally 15 (plot 6) D-flip-flops to one state. The logic levels O from the Q outputs of the first Dtriggers of each of the channels, entering the S-inputs of the second D-flip-flops 12 of each of the channels 7-1 and 7-2, establish them in a single state (plots 7 and 10). With the arrival of the first channels in each of the p-1 channels and the additional triggers of the fronts of the first channels after resetting the pulses from the input buses (plots 3-5), these triggers are set to the zero state.

476

At the output of AND 11.1 (plot 8) of the first channel, the logical level 1 is present when the first lOil and the second 12.1 D triggers of the first channel 7-1 are in the one and zero state, respectively. Similarly, for elements 11.2 of another channel (plot 10).

The second D-flip-flops 12 of each channel return to zero states when they are affected by the C-inputs of the first slices after the reset of the pulses coming from the first and second input units of the device through the inverters 13.

The signals from the outputs of the AND 1I elements of each of the channels and the 0 outputs of the additional D-flip-flop are combined on the OR 14 element, at the output of which the signal shown in plot 13 is generated, the PEDP operates as follows.

The signal from the p-inputs of the device counter 5 goes to the p outputs of the decoder 17. With three combinations of signals at the inputs of the decoder 17, pulses are formed at the first, second and third outputs of the device, so that their edges are tied to the starting points of the pulses at the output of the PDP 8, the signals from the outputs of the decoder 17 trigger one-shot 18.1, 18.2 and 18.3, which form pulses, the duration of which is selected in accordance with the given expression. The signals from the outputs of the single vibrators are combined on the element SHTI 19,

In FIG. 9, a reduction: a diagram of the stresses, explaining the operation of the FSP 9 in the normal sequence of signals arriving at its third input from the output of the FDP. Figure 10 shows the voltage plots showing the operation of the FSP 9 in the event of a failure recording of the redundant PDP 7 generator.

The signal from the output of one-shot 20 (plot 2) sets the first D-flip-flop 25 (plot 5) to zero, and the second 26 (plot 6) and the third 27 (plot 7) D-flip-flops to one. The front of the pulses arriving at the second input of the FSP 9 transfers the first D-flip-flop 25 to the one state, which allows the second D-flip-flop 26 to translate into the zero state, the Q-output of which sets the first D-flip-flop 25 to zero condition. The signal fed to the input of the one-shot 20 is shown in plot 1.

If the sequence of pulses from the output of the imaging unit diagnostic sequence 7 to the third input of the FSP 9,

signal from the Q output of the third D-flip-flop of the second D-flip-flop, outputs

Hera 27 (plot 7) blocks the zero and one states of the first 25 and second 26 D-flip-flops, respectively. When a next reset pulse is output from the one-shot 20 (plot 2), the switch driver 9 returns to its original state.

Claims (1)

Formula of 1, A device for controlling a regenerated generator containing input busses, an And element, a counter of elements And all channels are connected to the corresponding inputs of an OR element, the clock input of the additional I-flip-flop is connected to the nth input-15 bus, the D-input connected to the zero potential bus, inverse output to the corresponding input of the element OR, the output of which is the output of the former, the reset input of the acquisition of the 20 former via the one-shot connected to the inputs of the installation of the first 1 B-flip-flops of all channels, as well as an additional D-flip-flop, 3. Device pop, 1, cast, that the shape of the pulses, the signal generator Porek-25 can be switched, the pulse generator, the connector of the reference diagnostic the counting input of the counting counter contains a decoder, pulses, the setup input of which-inputs are the entrances are connected to the output of the element I, the worldviewer, and the outputs through the single-inputs of which are connected to the corresponding JO-rators are connected to the corresponding input buses, the first input of the switching signal generator is connected to the output of the element I, o t is similar to the fact that, in order to increase the reliability of the control, the diagnostic sequence generator and the reference diagnostic sequence generator, the output of which is connected to the second with the input of the formate-40, the input of the imager is connected directly to the switching signal, the third input and through the inverter with the inputs Nost whose reset input is connected to the output of the element I, and the information of the third D-flip-flop, the inverse output inputs are connected to the corresponding output of the forming generator, the inputs of the reference diagnostic sequences connected to exits the inputs of the OR element, the output of which is the output of the former, 4, device pop, 1, characterized in that the switch signal generator 35 comprises a one-shot, the input of which is connected to the first input of the driver, and the output is connected to the first inputs of the first, second and third elements, and the second synchronization of the first and second D-triggers, the third input of the imaging device is connected to the synchronization input bodies, and the direct output is connected to the second input of the second element, And, the third input of which is connected to the inverse .the corresponding bits of the counter im 50 output of the first D-flip-flop and the second bullets, 2, The device according to claim 1, characterized in that the diagnostic sequence generator contains n inputs according to the number of device input buses, the n-1 channel, each of which includes the first B-trigger, the inverse output of which is connected to the first input of the element And and with the installation input of the second D-flip-flop, the direct output of which is connected to the second input of the element I, D- the inputs of both triggers are connected to the zero potential bus, the synchronization input of the first D-flip-flop is connected to the corresponding input bus and through the inverter to the synchronizer input the tori are connected to the corresponding input of the imager connected directly and through an inverter to the inputs the inputs of the OR element, the output of which is the output of the former, 4, a device pop, 1, characterized in that the switch shaper comprises a one-shot, the input of which is connected to the first input of the shaper, and the output to the first inputs of the first, second and third elements And the third D-flip-flop, the inverse output of which is the output of the synchro-synchronization of the first and second D-triggers, the third input of the driver is connected to the synchronization input bodies, and the direct output is connected to the second input of the second element, And, the third input of which is connected to the inverse the input of the third element And, the output of which is connected to the input of the installation in 1 of the third D-flip-flop, the D-input of which is connected to the zero potential bus, the output of the second element And is connected to the input of the installation in 1 of the second D-flip-flop, the D-input of which connected to the zero potential bus, and the output to the second input of the first 9t457U710 element And, the output of which is connected to the trigger, the D-input of which is connected to the input of the installation in O of the first D- with the bus Logical unit.   Reset T 7 F) P Phases. 2 Phys.d 7 F) P Jimif 65 - No i FIG. 6 IT 6 7 3 d w 11 p “, Ji IT IT Jl -Tl Jt FIG. 9 i) ig.yu