RU1781816C - Device to form trains of pulses - Google Patents

Description

1

(21) 4859836/21

(22) 13.08.90 (46) 15-12.92. Bul, 46

(71) Irtysh Experimental Design Bureau

(72) E.G. Grossfeld

(56) Copyright certificate of the USSR Mg 1465950, cl. H 03 K 3/64, 1986.

USSR author's certificate N 919065, cl. H 01 K 3/64, 1978.

(54) DEVICE FOR FORMING SERIES OF PULSES

(57) The invention relates to a pulse technique and can be used in devices for forming and processing information. The device comprises an AND element, an OR element, an inverter, a key with storing a control signal, an OR-NOT element, a control bus, a clock bus, an output bus with corresponding functional connections. 3 ill.

The invention relates to a pulse technique and can be used in devices for forming and processing information.

A device for generating a series of pulses is known, comprising an inverter, an AND element, an OR-NOT element, a control bus, clock buses and an output bus.

A disadvantage of the known device is the design complexity, since thirty simple logic elements are required for its implementation. The indicated disadvantage provides this device with low reliability indicators in terms of the number of possible failures and the energy efficiency of the energy source. In addition, another significant disadvantage of this device is the low stability of the last output pulse of the generated pulse series, since distortion of the last pulse in the pulse series is possible with the asynchronous input of the control signal .

A pulse train forming apparatus is known which comprises an inverter, a control bus, a clock bus and an output bus.

The known device has a simple design, but its significant disadvantage is the low speed when generating the output signal and the low phase stability of this signal. The first is due to the fact that the maximum delay of the output pulses relative to the clock pulses is equal to three times the elementary delay of signal propagation through the simplest logic element. It is precisely this that does not allow one to obtain a small inertia in the formation of output pulses, and, therefore, to achieve high performance of the device as a whole. The second is due to the fact that the delay of pulses in different series relative to clock pulses is not constant. So, for example, if the output signal of the device is formed from pauses of the clock signal, then the delay of the series pulses in this case relative to the pauses of the clock signal is equal to twice the elementary delay of signal propagation through the simplest logical logic

WITH

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moment, if the output signal of the device is formed from clock pulses, then the delay of the series pulses in this case is equal to the triple elementary delay of signal propagation through the simplest logic element.

A pulse train forming apparatus is known comprising a control bus, a clock bus connected in series, an AND element, an OR element, and an output bus.

A disadvantage of the known device is the design complexity, which is due to the fact that it includes a D-trigger and an EC-trigger, the first of which consists of six and the second of eight simple logic elements. Thus, the total amount of hardware required to implement this device is seventeen of the simplest logical elements. The specified disadvantage provides this device with low reliability indicators in terms of the number of possible failures and the economy of energy resources. In addition, a significant disadvantage of this device is the low speed when generating the output signal. This is due to the fact that the maximum delay of the series pulses relative to clock pulses is equal to the sum of the signal propagation delays in the D-trigger (or in the DK-trigger), in the AND element and in the OR element, and cannot be less than four elementary signal propagation delays through the simplest logical element.

Closest to the technical nature of the present invention is a device for generating a series of pulses containing a control bus, an element And, the first input of which is connected to the clock bus, the output is connected to the first input of the OR element, the output of which is connected to the output bus, an inverter.

The disadvantage of this device is the low speed when generating the output signal. This is due to the fact that the maximum delay of the first pulse of the series formed by it relative to the clock signal is quite large, since it is equal to four elementary delays of signal propagation through the simplest logic element. In addition, if the output signal of the device is generated from pauses in the clock signal, then the maximum delay of the second and each subsequent pulse of the generated series relative to the pauses of the clock signal is equal to three times

elementary delay in signal propagation through a simple logic element, i.e. also quite significant. These features of the known device do not allow to obtain a low inertia in the formation of output pulses, and therefore, to achieve high speed of the device as a whole.

0 An object of the invention is to increase speed by reducing the maximum delay of the output signal relative to the clock signal.

The goal is achieved in that

5 into the device for forming a series of pulses containing a control bus, an element And, the first input of which is connected to the clock bus, the output is connected to the first input of the OR element, the output of which is connected to the output bus, an inverter, a key with the control signal and the element are entered OR NOT, the output and the first input of which are connected respectively with the second input of the OR element and with

5 by the inverter output, the second input is connected to the clock bus and to the control input of the key with storing the control signal, the first information input and the first output of which are connected respectively to

0 control bus and with the second input of AND element, the second output is connected to the inverter input, and the second information input is connected to the output bus.

In FIG. 1 shows an electrical

5 is a functional diagram of an apparatus for generating a series of pulses; in FIG. 2 - time diagrams explaining its operation; in FIG. 3 is a possible embodiment of a key with a memory of a control signal.

The device for generating a series of pulses contains an AND 1 element, an OR element 2, an inverter 3, a key 4 with a control signal memory, an OR-NOT 5 element, an equalizing bus 6, a clock bus 7 and an output bus 8.

The first input of the element And 1 is connected to the bus 7, with the second input of the element OR NOT 5 and with the control input of the key 4, the first

0 the output of which is connected to the second input of the element AND 1, the second output is connected through the inverter 3 to the first input of the element OR NOT 5, the first information input is connected to the bus 6, and the second information

5, the input is connected to the bus 8 and to the output of the element OR 2, the first and second inputs of which are connected to the outputs of the elements AND 1 and OR NOT 5, respectively.

A device for forming a series of pulses operates as follows

In the initial state, on the buses b (Fig. 2, a) and 8 (Fig. 2.g), the O levels act, and on the bus 7 (Fig. 2,6) a clock signal is received, Since the first (Fig. 2, c) and the second (Fig. 2, d) outputs of the key 4 there are levels O, then the outputs of the elements And 1 (Fig, 2, e) and OR NOT 5 (Fig 2.e) also operate levels O.

If the edge of the control pulse, the duration of which is required to be converted into a series of pulses, is formed on bus 6 during the inter-pulse pause in the clock signal (i.e., if there is an O level on bus 7), then this control pulse is switched to the first - the key switch 4 moves to the second input of the element And 1. However, this does not lead to a change in the state of the signal at the output of this element, since for the duration of the current inter-pulse pause of the clock signal, the element And 1 is closed by the signal O at its first input The closestEach subsequent clock pulses arriving on bus 7 do not interrupt the process of switching the control pulse from the first information input to the first output of key 4 and pass through the open element AND 1 and through the element OR 2 to bus 8. As a result, on bus 8 a series of pulses is allocated, each pulse of which is generated from a pulse of the bus signal 7. A level O is set at the first information input of the key 4. At the same time, the level O is formed at the first output of the key 4 either directly from the middle y control pulse (if used during the action of this shear layer is formed by a pulse on line G on the bus 8). or, due to the feedback from the output of the OR element 2 to the second information input of the key 4. by cutting the current pulse of bus 8 (if a slice of the control pulse is formed on bus b during the operation of level 1 on bus 8).

If the front of the control pulse, the duration of which is required to be converted into a series of pulses, is formed on bus 6 during the action of the clock pulse (i.e., if there is level 1 on bus 7), then this control pulse is switched to the second output of key 4. In this case at the output of inverter 3, level O is set, which is fed to the first input of the element. OR NOT 5 However, this is not

leads to a change in the state of the signal at the output of this element, since for the duration of the current clock pulse, the OR-NOT 5 element is closed by signal 1 at its second input. The subsequent changes in the level of the clock signal on bus 7 do not interrupt the process of switching the control pulse from the first information input to the second output of key 4, which ensures the action of level O at the first input of the OR-NOT 5 element. Thanks to this, the OR-NOT 5 element inverts the nearest and subsequent inter-pulse pauses of the clock signal A. As a result, a series of pulses is allocated on bus 8, each pulse of which is generated from a pause of the clock signal of bus 7. By cutting the control pulse, the level O is set on the first information input of key 4. At the same time, the level O is formed on the second output of key 4 or directly by the control an impulse (if a slice of this impulse is formed on the bus 6 during the operation of the O level on the bus 8), or due to the feedback from the output of the OR element 2 to the second information input of the key 4, by cutting the current pulse of the bus 8 (ec and slice control pulse is generated on the tire 6 during the action of the level 1 bus 8).

Claims (1)

SUMMARY OF THE INVENTION A device for generating a series of pulses containing a control bus, element I. The first input of which is connected to the clock bus, the output is to the first input of the OR element, the output of which is connected to the output bus, an inverter, characterized in that, in order to increase speed by reducing the maximum delay of the output signal relative to the clock signal, a key is entered into it with the control signal and the OR-NOT element, the output and the first input of which are connected respectively to the second input of the element and OR and with the inverter output, the second input is connected to the clock bus and to the key control input with the control signal memorized, the first information input and the first output of which are connected respectively to the control bus and to the second input of the And element, the second output to the inverter input and the second information input is with the output bus