SU363201A1 - LIBRARY - Google Patents

Description

one

Known multichannel digital-to-analog converters that contain, for all channels, a code recorder, an address selector block, a control block, and output channels, each of which contains a register, a code-analog converter, and an amplifier, do not provide the required accuracy of the conversion.

The purpose of the invention is to increase the reliability of the conversion.

This is achieved by the fact that the device contains a false information detection unit, made in the form of a current comparator and a key, the outputs of which are connected respectively to the nerve input of the comparator and to the common bus, and the input to the first input of the control unit, and sequential chains from a resistor, capacitor and the key at the output of the amplifier of each output channel, the outputs of the keys included in the chains are combined and connected to the output of the current room, and the inputs are connected to the corresponding outputs of the channel address block, and the check block recording ostovernosti configured similarly as the output channel with an additional key between the output of the amplifier and the second input current komnaratora, additional key input coupled to the second input of the control unit.

The drawing shows a block diagram of the proposed device.

The following symbols are used in the diagram; unit / control; block 2 address channel selection; block 3 zannsi codes; output channel 4 register 5; Converter code analogue 6; output amplifier 7; false information detection unit 8; block 9 check validity of the record; current comparator

W; key //; resistor 12 capacitor 13; key 14, 15; control signal 16; channel address code 17; code 18 new information; code 19 differences of values; interrupt signal 20; output channels 21.

In the control mode, the block 2 of address channel selection continuously generates signals of sequential channel selection, which are fed to the control inputs of the keys 14. In this sense, the key 11 is open,

and the input of the current comparator 10 is connected to ground. When a channel is selected, a circuit consisting of a resistor 12, a capacitor 13, a public key 14, an internal resistance of the current comparator 10, which is a small value, and a public key 11 is connected to its output. Since in the previous clock cycle the capacitor 13 along this circuit, charges up to a voltage equal to the output voltage of the channel, and for the elapsed time between

If the discharge channel for the node of the capacitor 13 does not require a significant current, the current room number 10 will not work. If, however, there is any malfunction, failure or erroneous recording, leading to information corruption, then in the next channel selection current of the surgeon and capacitor 13 will be significant and the current comparator 10 will give a false information signal in this channel.

Simultaneously with the recording of new information from the computational mas- sage in the form of control signals 16, the channel address code 17 and the new information code 18, the difference code 19 values recorded in the channel and intended for new recording is also received. This conversion is performed by block 9 validation of the recording using register 5, code-analog converter 6 and output amplifier 7. In this mode, key 15 is open and key 11 is closed, so that voltage must be applied to the input of current comparator 10 change channel output signal. As a result, in the absence of failures or faults, almost no current flows through the current comparator 10, and if the output signal of the channel is not equal to the sum of the voltages on the capacitor 13 and on the output of the recording validation unit 9, a significant overcurrent of the capacitor 13 flows through the current comparator to the operation of the current comparator 10, indicating the incorrect recording of information.

The signal from the output of the current comparator 10 enters the unit / control. This unit generates an interrupt signal 20 for the computer. This signal takes action to eliminate the false

information on the output channels 21. After performing the write control and code conversion, the capacitor 13 is recharged. To do this, the key 15 is closed and the key 11 is opened by signals from the control unit 1.

Thus, the device performs continuous detection of the occurrence of false information in all output channels 21 and verifies the accuracy of the recording and conversion of new information.

Subject invention

A multi-channel digital-to-analog converter containing a block of code writing, a block of address channel selection, a control block and output blocks common to all channels.

channels, each of which contains a register, a code-analogue converter and an amplifier, characterized in that, in order to increase the reliability of the conversion, it contains a false information detection unit, made in the form of a current comparator and a key, the outputs of which are connected respectively to the first input of the comparator and with a common length, and the input with the first input of the control unit, and successive chains of a resistor, a capacitor and a key at the output of the amplifier of each output channel, the outputs of the keys included in the chains are combined and under lyucheny to the output of the current comparator, the inputs connected to the respective channel address output unit and the recording unit validation configured similarly as the output channel with an additional key between the output of the amplifier and the second input of the current comparator input

an additional key is connected to the second input of the control unit.